CN1708811A - Magnetic tunnel junction memory cell architecture - Google Patents
Magnetic tunnel junction memory cell architecture Download PDFInfo
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- CN1708811A CN1708811A CN 200380102411 CN200380102411A CN1708811A CN 1708811 A CN1708811 A CN 1708811A CN 200380102411 CN200380102411 CN 200380102411 CN 200380102411 A CN200380102411 A CN 200380102411A CN 1708811 A CN1708811 A CN 1708811A
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Abstract
A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.
Description
The application requires the pending trial U.S. Provisional Application No.60/422 that submitted on October 30th, 2002,225 right of priority based on 35U.S.C 119 (e) (1), and be included in this as a reference.
Technical field
The present invention relates to field of data storage, more specifically, relate to a kind of magnetic tunnel junction device memory cell architecture.
Background technology
Magnetic-resistance random access storage (MRAM) is a kind of high speed, low-voltage, high density, nonvolatile memory, wherein by applying magnetic field, information bit is stored in magnetic tunnel-junction (MTJ) structure, and from MTJ, obtain this information bit by measuring its magnetic resistance.MRAM comprises with respect to the advantage of other technologies: read fast and write, non-volatile, near the combination of unlimited circulation ability, full bit modifiability and simple cellular construction.
MTJ is clipped between two ferromagnetic (FM) layer that is separated by thin dielectric layer.Useful especially mtj structure is wherein by exchange biased one of the ferromagnetic layer (ispinned) that pins to antiferromagnetic layer.For the application of MRAM, mtj structure is designed to have stable magnetic state, corresponding to the parallel and antiparallel of the FM layer in the MTJ equipment towards.More specifically, the MTJ bing is made of two magnetospheres that thin dielectric barrier layer separates usually.(for example FeMn or IrMn are set to contact with end magnetosphere, pin it in one direction will to have the antiferromagnetic material layer of strong exchange coupling.This layer separates with next magnetosphere by the thin layer of Ru, created synthetic anti-ferromagnet.Strong exchange between the magnetosphere in this synthetic anti-ferromagnet structure fixes the magnetic polarization of fixed bed with a direction, and prevents that fixed bed from switching during write operation.Suppose the following fact: the MTJ filling apparatus depends on the variohm of aforesaid free magnet to two discrete magnetic resistance values of the relative direction of pinning magnet when having, and by estimation MTJ magnetic resistance, the state that circuit obtains MTJ equipment is read in use.
But integrated memory cell has and is used to make the MTJ extended architecture and handles and be used for the circuit that MTJ is write and be used to read the circuit of MTJ.As most of integrated processing, handle and/or the minimizing memory cell surface area by the quantity, the simplified construction that reduce assembly, can realize lower cost.
Summary of the invention
Memory device comprises magnetic tunnel junction memory cell, has magnetic tunnel junction structure and read switch.In one example, read switch links to each other with electric conductor, is used for magnetic tunnel junction structure is write.In another example, described read switch is the transistor that is electrically connected with magnetic tunnel junction structure by deep via contact.
In another example, described memory device comprises a plurality of magnetic tunnel junction memory cells and related with described unit respectively a plurality of electric conductors, so that information is write related magnetic tunnel junction structure.Each read switch links to each other with the electric conductor related with other magnetic tunnel junction cells except the unit that wherein has read switch.
Description of drawings
In order more completely to understand the present invention, reference is below in conjunction with the detailed description that accompanying drawing adopted, wherein:
Fig. 1 shows traditional MTJ mram cell;
Figure 1A shows the synoptic diagram of the part of MTJ mram cell shown in Figure 1;
Fig. 2 shows the magnetic memory architecture of the exemplary embodiments according to the present invention;
Fig. 2 A shows magnetic memory architecture according to another embodiment of the present invention;
Fig. 3 shows the synoptic diagram of the magnetic memory architecture shown in Fig. 2 and Fig. 2 A.
Embodiment
A large amount of innovation enlightenments of the application will be described with reference to current preferred exemplary embodiments.Yet, should be appreciated that such embodiment only provides several examples of various preferable use and innovation enlightenment.Usually, the statement of being carried out in the application's instructions needn't be defined the invention of various requirement protection arbitrarily.And some statements can be applied to some inventive features, but cannot be applied to other features.In whole accompanying drawing, should be noted that and to use identical reference number or letter to specify similar or equivalence element with identical function.For the sake of simplicity, omitted the detailed description that can make unclear known function of theme of the present invention and structure.
Fig. 1 shows the xsect of the conventional example of MTJ mram cell 100.This figure is parallel to and/or cuts logical each element, as described below.The element of unit 100 comprises MTJ114; Conductive layer 102 " writes " line as the bit at the bit of being stored among the MTJ 114 and operates with " reading " line; Conductive layer 104 " writes " the line operation as word; And FET 106, have source electrode 108, drain electrode 110 and grid 112, operate as the switch that is used to read the bit of being stored.Typically, writing line 102 and 104 is perpendicular to one another, and as from the unit 100 top seeing, and is positioned at the parallel plane of separation.
MTJ 114 is formed at the intersection point place of writing line 102 and 104, and is described as other places.The side of MTJ 114 and line 102 are electrically connected continuous, and by power path 116, and it is continuous that the source electrode 108 of opposite side and FET106 is electrically connected, as described further below.Line 104 and MTJ 114 are that electricity interrupts.
The drain electrode 110 of FET 106 links to each other with ground 118.Usually, normally not conducting of FET 106, thereby do not have electric current can from line 102 by MTJ 114, path 116 and source electrode 108 flow into " ".When with suitable current selective ground is instantaneous when being applied to line 102 and 104, it has created quadrature field in MTJ 114.These are with the low magnetic resistance state (R of MTJ 114
PARALLEL) or its high magnetic resistance state (R
ANTIPARALLEL), optionally write or be provided with MTJ 114.Subsequently, can apply signal by applying to line 102 from the electric current of current source and to the grid 112 of FET, read the state of MTJ 114, described signal acts on source electrode 108 and the conduction between 110 of draining.Read flow through-low or high-MTJ 114, path 116 and conducting FET106 to " " amplitude of 118 electric current, to determine that MTJ 114 is in high-impedance state or low resistive state.High-impedance state causes that the electric current lower than low resistive state passes through element 114,116 and 106.
MRAM can comprise word line (WL) 104 a large amount of parallel bit line (BL) 102 and quadrature, that be parallel to each other with the MTJ 114 that is positioned at each word line-bit line point of crossing place.
Come manufacturing cell 100 by typical integrated circuit technique, wherein utilize photoetching (lithographic), mix and other handle zone and the layer that forms various conductors, semiconductor and insulator.For example, ground 118 among Fig. 1 comprises column conductive metal contact 120, at one end the diffusion region 110 (i.e. drain electrode) with FET is electrically connected continuous, and it is continuous to be electrically connected at the other end and public conduction ground wire 122 outside the plane neutralization that extends among the figure, and is electrically connected continuous with the similar contact 120 of other unit 100 (not shown).Similarly, path 116 parts comprise post-like electrical contact 124, link to each other with the source electrode 108 of FET 106 at one end, link to each other with the hardware 126 of a part of serving as path 116 at other end place.
As shown in the figure, contact 120 and 124 is coplanes; In addition, hardware 126 and metal earth 122 are coplanes.In fact, form element 120,124 simultaneously, and form hardware 122,126 by the metal level (M1) that deposits simultaneously after a while.Particularly, after forming FET 106, in silicon substrate 128 and on, by traditional doping and deposition technique, the peripheral region of FET 106 and substrate is covered by electric insulation layer 130.Described layer 130 is used for protecting FET 106 during manufacturing cell and in use after a while.Finally, layer 130 has the degree of depth of the height that equals contact 124,120.Typically, this is slightly larger than the required degree of depth by layer 130 is deposited as, and removes unnecessary part by planarization technique (for example chemical-mechanical polishing) then and realizes.
After making layer 130, come optionally it to be etched with to make through hole or hole 132,134 by known photoetching technique and other similar techniques, extend by layer, and in its bottom-exposed source electrode and drain electrode 108 and 110.Then, metal is deposited or is filled in the through hole 132,134, thereby make the contact 120,124 of such formation be electrically connected continuous with contact 110 and source electrode 108 respectively.
Next, form metal level M1, the end of overlayer 130 and contact 120,124, conductive layer M1 and described end are electrically connected continuous.Finally, because the application of planarization steps, the degree of depth of layer M1 adopts the desired thickness of element 126 and ground wire 122.Next, use photoetching technique to remove the excess metal of layer M1, stay element 126 and ground wire 122.
Next, second metal level (M2) is coated on the top surface of layer 144 and contact 142, subsequently, carries out lithography selective etch or other removal technology, so that remove the selected portion on the layer M2, to make word writing line 104 and the coplane conductive member 150 that is electrically connected continuous with contact 142.Next, online 104 and the complanation top surface of member 150 on and online 104 and the interval of member 150 in, form insulation course 152.Next, in the through hole 156 that extends by layer 152, form top surface with the member 150 continuous contact 154 that is electrically connected.
On the top of the complanation top surface of insulation course 152, depositing metal layers 160 subsequently, stays hardware 162 to the selective removal of layer 160, top with contact 154 is electrically connected at one end, and has and the top surface interval of member 104 and " freedom " end of electrical isolation.Use similar techniques on the top surface of " freedom " end of member 162, to make MTJ 114, and be electrically connected with " freedom " end of member 162.In addition, realize that known technology is provided with additional metal layer (M3), form MTJ bit line (BL) 102, be positioned at the top of MTJ 114 and be electrically connected continuous with MTJ 114 by it.
At last, realize that known technology is provided with another metal level (M4), form metal wire 300 by it, usually perpendicular to metal BL 102 and with metal BL 102 electrical isolations.The metal wire 300 that use has relatively low resistance reduces the resistance of polymerization word line 112.Polymerization will provide harmful long RC to postpone to word line 112 separately.Usually, metal wire 300 has the sheet resistance of about 0.1ohm/sq, switches to the polymerization word line 112 of the sheet resistance with about 5ohm/sq.Shown in Figure 1A, per 128 bit lines switch to polymerization word line 112 with metal wire 122, and this is the typical scenario of traditional MRAM configuration.For example, can use the technology that is called as stitch (stitch) known from the DRAM technology that this bypass is provided.Described stitch has been realized the ohmic combination of metal wire 300 and polymerization word line 112, and this has reduced total RC delay, has therefore increased the access time.
Notice that metal level M1 comprises element 122 and 126, M2 comprises element 104 and 150, and M3 comprises element 102, and M4 comprises element 300.As can be seen, the structure of traditional MTJ MRAM comprises a plurality of detailed levels and processing.Layer and correlative sediments operation, etching and other minimizings of removing the quantity of operation and/and other lithography operations will reduce manufacturing cost, and/or the per unit capacity provides more storage.One aspect of the present invention has reduced the number of plies, and more specifically, metal level thus, is advantageously realized reducing manufacturing cost and/or reducing cell capability.
Fig. 2 shows the xsect of the MTJ memory device 200 of the exemplary embodiments according to the present invention.Memory device 200 comprises bit line 102 and word line 104, is used for operating as mentioned above MTJ 114.In addition, can make memory device 200 by above-mentioned traditional integrated circuit technique.Yet, use connection of the present invention and activation scheme, from current memory device 200, eliminated layer M1 and M4 (from Fig. 1).In order to remain on preferred low ohm word line and the low ohm ground of reading set in traditional mram cell 100 by metal level (promptly being respectively M4 and M1), the line 104 that makes the current connection and the scheme of activation is for multi-functional.That is, except the line 104 in the magnetic field that is used for realizing MTJ 114, also use line 104 to reduce the high ohm property of polymerization WL 112, and low ohm ground is provided.
In order to provide the low ohm word line that reads, the metal word lines 104 of each unit is switched to its polymerization WL 112 according to current connection and activation scheme.Fig. 2 and 3 is shown item 33 with this bypass.Fig. 3 shows the synoptic diagram of MTJ memory device 200 shown in Figure 2.For example, can provide bypass, be similar to stitch at the described metal wire 300 to polymerization WL112 of Figure 1A by the stitch technology.Being connected (after this be called as and be expressed as Adr (n) 104 at Fig. 3) (as described below) with the advanced signal of the line 104 of corresponding activation scheme combination is used to cancel M4 (Fig. 1).
For low ohm ground is provided, also in stitch is handled, the Adr (n) 104 of each unit is switched to diffusely 110 of an adjacent cells (be shown 35 in Fig. 3, and illustrated by the dotted line among Fig. 2).Therefore, also carry out the function of the metal earth 122 of M1 (among Fig. 1), therefore, can cancel it with the Adr (n) 104 of the activation scheme combination of the following stated.Therefore, contact 150 can be directly applied to the top surface of contact 124, further cancel contact 142, further reduce the overall height of device 200.
The typical read/write of below having described according to the magnetic memory architecture shown in Fig. 2 and 3 activates scheme.At first, for specific MTJ unit 114 is write, optionally suitable electric current is applied to instantaneously writing line BL (n) 102 and the Adr (n) 104 related with MTJ unit 114.For example, for the unit among Fig. 3 " A " write, (for example, about 5mA) is applied to Adr (1) and BL (0) with write current.Here, the voltage of Adr (1) is approximately 0.25V, equals 5mA * 50ohm.In addition since with polymerization WL (1) stitch 33 to Adr (1), the output of switch " D " and " E " must be remained on low-voltage (for example 0.25V) and during writing, be switched on preventing.Because the diffusion region stitch of each switch 106 is to adjacent writing line Adr (n) 104, therefore, by 0.25 necessary volt signal is applied to every other Adr (n), the output of switch " D " and " E " is remained on low level.
For reading unit " A ", electric current is applied to BL (0), and by activation signal being applied to grid via Adr (1), and ground is exported with reference to being applied to switch via other Adr (n), actuating switch " D ", so that " D " realizes conducting by switch, it is carried out the state of sensing with the MTJ of determining unit " A ".More specifically, will move on the Adr (1) high level (for example, approximately 1.8V), and make every other Adr (n) that low level (for example, ground=0V) with connection is provided with providing.Can comprise that the amplitude that traditional circuit comes sense current to flow through is in high-impedance state or low resistive state with definite MTJ 114.High-impedance state has caused the electric current lower than low resistive state.
The combination of the current connection and the scheme of activation provides the function of metal level M1 and the M4 and the writing line of traditional MTJ configuration of cells in the single multi-function metal line, shown in Figure 1.
With reference now to Fig. 2 A,, shows another embodiment of the present invention.In this embodiment, with contact 154,150 and 124 (shown in Figure 2) by being combined in the single dark contact 250.Typically, traditional integrated circuit (IC) design need (be shown " X ") to metal distance such as the metal between the hardwares such as 104 and 150 among Fig. 2 in the scope of about 0.24 μ m.Use deep via contact 250, reduced distance X (up to reducing with 1/3) significantly, the result has greatly reduced the overall width of multiple-unit mtj structure.Traditionally, can make via-contact narrower than hard contact.Shown in Fig. 2 and 2A, conventional via contacts 124,154 and 250 is narrower than the conventional metals member, for example member 150 (approximately narrow 0.16 μ m).Shown in Fig. 2 A, use deep via contact to allow the X size of the about 0.24 μ m from Fig. 2 to be reduced to the corresponding Y size of the about 0.16 μ m among Fig. 2 A.
Deep via contact 250 is applied to electric contact between source electrode 108 and the member 162, and can uses known conventional art to form.
Although described the preferred embodiment of equipment of the present invention and method in shown in the drawings and the detailed description in front, but should be appreciated that, the present invention is not limited to the disclosed embodiments, but under the prerequisite of spirit of the present invention that does not break away from the illustrated and definition of claims, can carry out a large amount of reconstruct, modification and substitute.
Claims (26)
1, a kind of memory device comprises:
Magnetic tunnel junction cell, comprise magnetic tunnel junction structure and the switch that links to each other with described magnetic tunnel junction structure, described switch has the control input, and the described control input of described switching response is so that allow to read institute's canned data in the described magnetic tunnel junction structure from described magnetic tunnel junction structure;
Electric conductor links to each other with described magnetic tunnel junction structure, is used for information is write described magnetic tunnel junction structure; And
Described switch links to each other with described electric conductor.
2, equipment according to claim 1 is characterized in that described electric conductor is a word line.
3, equipment according to claim 1 is characterized in that described control input links to each other with described electric conductor.
4, equipment according to claim 3 is characterized in that described switch is a field effect transistor, and described control input is the grid of described field effect transistor.
5, equipment according to claim 4 is characterized in that described electric conductor is a word line.
6, equipment according to claim 4 is characterized in that described grid is a polysilicon gate.
7, equipment according to claim 3 is characterized in that being included in the bypass of extending and being electrically connected described control input and described electric conductor between described control input and the described electric conductor.
8, equipment according to claim 7 is characterized in that described bypass is the stitch bypass.
9, equipment according to claim 3, organize described magnetic tunnel junction cells more it is characterized in that comprising and distinguish related a plurality of described electric conductor with described group, each described electric conductor links to each other with the described magnetic tunnel junction structure of associated group, be used for information is write the described magnetic tunnel junction structure of associated group, each each described control of described group is imported and is linked to each other with described group of related electric conductor.
10, equipment according to claim 9 is characterized in that the described control input in each described group is linked together.
11, equipment according to claim 10 is characterized in that described switch is a field effect transistor, and described control input is the polysilicon gate of described field effect transistor.
12, equipment according to claim 9, it is characterized in that comprising a plurality of bypasses that are connected respectively to described control input, each described bypass association control input and with electric conductor that related control input links to each other between the electric conductor that extends and be electrically connected related control input and link to each other with related control input.
13, a kind of memory device comprises:
A plurality of magnetic tunnel junction cells, each magnetic tunnel junction cell comprises magnetic tunnel junction structure and the switch that links to each other with described magnetic tunnel junction structure, described switch has the control input, the described control input of described switching response is so that allow to read institute's canned data in the described magnetic tunnel junction structure from described magnetic tunnel junction structure;
A plurality of electric conductors, related with described magnetic tunnel junction cell respectively, each described electric conductor links to each other with described related magnetic tunnel junction structure, is used for information is write described magnetic tunnel junction structure; And
Each described switch with except with link to each other comprising one of described electric conductor the related electric conductor of the magnetic tunnel junction cell of described switch.
14, equipment according to claim 13, it is characterized in that each switch has first and second nodes, its the described control input of each described switching response, be used to allow electric current between its described first and second nodes, to flow, each described first node links to each other with corresponding magnetic tunnel junction structure, each described Section Point with described in the described electric conductor related one link to each other.
15, equipment according to claim 14, it is characterized in that comprising the described magnetic tunnel junction cell of many groups, described a plurality of electric conductor is related with described group respectively, each described electric conductor links to each other with the described magnetic tunnel junction structure of associated group, be used for information is write the described magnetic tunnel junction structure of associated group, and each described Section Point with except with link to each other comprising one of described electric conductor the related electric conductor of the group of Section Point.
16, equipment according to claim 15, it is characterized in that first described group each described Section Point with link to each other with second described group of related electric conductor.
17, equipment according to claim 16, it is characterized in that the 3rd described group each described Section Point with link to each other with described first group of related electric conductor.
18, equipment according to claim 15, it is characterized in that comprising related with described Section Point respectively a plurality of bypasses, each described bypass related Section Point and with electric conductor that related Section Point links to each other between extend and be electrically connected related Section Point and the electric conductor that links to each other with related Section Point.
19, equipment according to claim 15 is characterized in that each described group interior described Section Point links together.
20, equipment according to claim 19 is characterized in that the described Section Point ground connection in each described group.
21, equipment according to claim 14, it is characterized in that each described switch is a field effect transistor, have the grid that has defined its described control input, have the source electrode that has defined its described first node, and have the drain electrode that has defined its described Section Point.
22, equipment according to claim 13 is characterized in that described electric conductor is a word line.
23, equipment according to claim 13, it is characterized in that each described switch with comprising the related electric conductor of the magnetic tunnel junction cell of described switch link to each other.
24, equipment according to claim 23, it is characterized in that each described switch has and with the control that links to each other comprising the related electric conductor of the magnetic tunnel junction cell of described switch input, and each described switch have except with other nodes related described in a described electric conductor continuous described control is imported.
25, a kind of memory device comprises:
Substrate;
Be formed on the transistor on the described substrate;
Electrical insulation material layer is used to cover described transistor;
Electric conductor is used to cover described electrical insulation material layer;
Magnetic tunnel junction structure is electrically connected with described electric conductor, and described magnetic tunnel junction structure is formed on described electric conductor and the described electrical insulation material layer facing surfaces; And
Via-contact is extended by described electrical insulation material layer, and described electric conductor is electrically connected with described transistor.
26, equipment according to claim 25 it is characterized in that described transistor is a field effect transistor, and described via-contact links to each other with the source electrode of described field effect transistor.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US42222502P | 2002-10-30 | 2002-10-30 | |
| US60/422,225 | 2002-10-30 | ||
| US10/422,100 | 2003-04-24 |
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| Publication Number | Publication Date |
|---|---|
| CN1708811A true CN1708811A (en) | 2005-12-14 |
| CN100421172C CN100421172C (en) | 2008-09-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2003801024111A Expired - Fee Related CN100421172C (en) | 2002-10-30 | 2003-10-28 | Magnetic tunnel junction memory cell architecture |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105655481A (en) * | 2015-12-24 | 2016-06-08 | 上海磁宇信息科技有限公司 | Super-dense cross matrix array type magnetic random access memory manufacturing technology |
| CN112349322A (en) * | 2019-08-06 | 2021-02-09 | 上海磁宇信息科技有限公司 | Magnetic random access memory architecture and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10050365A1 (en) * | 2000-10-11 | 2002-05-16 | Infineon Technologies Ag | MRAM configuration |
| JP4726292B2 (en) * | 2000-11-14 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | Thin film magnetic memory device |
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2003
- 2003-10-28 CN CNB2003801024111A patent/CN100421172C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105655481A (en) * | 2015-12-24 | 2016-06-08 | 上海磁宇信息科技有限公司 | Super-dense cross matrix array type magnetic random access memory manufacturing technology |
| CN112349322A (en) * | 2019-08-06 | 2021-02-09 | 上海磁宇信息科技有限公司 | Magnetic random access memory architecture and manufacturing method thereof |
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| Publication number | Publication date |
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| CN100421172C (en) | 2008-09-24 |
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