CN112349322A

CN112349322A - Magnetic random access memory architecture and manufacturing method thereof

Info

Publication number: CN112349322A
Application number: CN201910722857.7A
Authority: CN
Inventors: 戴瑾
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2019-08-06
Filing date: 2019-08-06
Publication date: 2021-02-09

Abstract

Each memory cell of the magnetic random access memory architecture is arranged at the intersection of a word line and a bit line and comprises a vertical field effect transistor and a magnetic tunnel junction, wherein the vertical field effect transistor consists of a grid electrode, a fin-shaped structure and an N + + semiconductor region. The grid electrode is formed along two sides of the fin-shaped structure, and the part of the grid electrode corresponding to the bit line is connected with the magnetic tunnel junction through the conductive component. The gate is formed along the fin-shaped structure, so that the vertical field effect transistor is compatible to be used in a fin-shaped design, the forming density of the memory unit of the memory is improved, and the memory capacity of the memory is improved.

Description

Magnetic random access memory architecture and manufacturing method thereof

Technical Field

The present invention relates to the field of memory technology, and more particularly, to a magnetic random access memory architecture and a method of manufacturing the same.

Background

Magnetic Random Access Memory (MRAM) is applied to an embedded memory structure, and basically, a Complementary Metal-Oxide Semiconductor (CMOS) process of a logic chip is still required, and the area of one mos is much larger than that of a Dynamic Random Access Memory (DRAM), while a fin field effect transistor (FINFET) technology has a channel which is three-dimensional, but a source and a drain are planar, and the problem of large tube size is more prominent, so that the large size of the mos is limited, namely, capacity is increased and cost is increased. By using the prior art, the area can be greatly reduced if the metal oxide semiconductor tube is made into a vertical structure. But are not suitable for use in magnetic random access memory and are not compatible with cmos processes.

Disclosure of Invention

In order to solve the above-mentioned problems, an objective of the present invention is to provide a magnetic random access memory architecture based on vertical metal oxide semiconductor (mos) transistors, which is compatible and used for finfet design by vertical fet design.

The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme.

According to the present invention, a magnetic random access memory architecture comprises a plurality of memory cells, wherein in the structure of each memory cell, a bit line and a word line are arranged in a mutually perpendicular manner, wherein one end of the memory cell is connected with the bit line, and the other end is connected with the word line through a via/connection point, so that each memory cell is arranged at the intersection of the bit line and the word line, and each memory cell comprises: a semiconductor region of a first doping type; a fin structure of a second doping type disposed on the semiconductor region, a top end of the fin structure being disposed as a drain, a bottom end of the fin structure contacting a source formed by the semiconductor region; the grid electrode is arranged on two sides of the fin-shaped structure and isolates the fin-shaped structure from the semiconductor region through an insulating medium, wherein the insulating medium is silicon oxide; and a magnetic tunnel junction connected to the drain by a conductive element.

The technical problem solved by the application can be further realized by adopting the following technical measures.

In an embodiment of the present application, the fin structure serves as a conductive channel, and the gate controls on or off of the conductive channel.

In one embodiment of the present application, the word lines are formed such that the gates are connected along the fins.

In an embodiment of the present application, the semiconductor region of each memory cell includes a source, and the sources of the semiconductor regions of the plurality of memory cells are connected to form a source line.

In an embodiment of the present application, the fin structures of the plurality of memory cells corresponding to the same word line are adjacent interconnects, and the gate outside the fin structures of the interconnect region is replaced by a partial surrounding manner.

In an embodiment of the present application, the magnetic tunnel junction top contacts the bit line.

In one embodiment of the present application, the conductive element is a via or a contact and the material thereof includes titanium, tantalum, tungsten, titanium nitride, tantalum nitride, and combinations thereof.

In an embodiment of the present application, the first doping type is N + + type, and the second doping type is P type.

Another object of the present application is a method of manufacturing a magnetic random access memory, comprising: forming a semiconductor region of a first doping type in a semiconductor substrate of a second doping type; etching the semiconductor substrate to form a fin-shaped structure on the surface of the semiconductor substrate; forming an insulating medium on the surface of the fin-shaped structure; forming a gate at a periphery of the fin structure, the fin structure being isolated from the fin structure and the semiconductor region by the insulating dielectric; covering the semiconductor region and the fin structure with an insulating medium; etching part of the insulating medium and the grid electrode, and filling the insulating medium to form an etching small hole exposing part of the fin-shaped structure; forming a conductive element in the etching small hole; forming a magnetic tunnel junction over the conductive element; and connecting the magnetic tunnel junctions through bit lines.

In an embodiment of the present application, the semiconductor region is formed in the semiconductor substrate by an ion implantation method.

In an embodiment of the present application, a bottom of the fin structure is formed by etching the semiconductor region.

In an embodiment of the present application, in the step of etching the insulating medium and the gate of the portion, the portion to be etched is a corresponding bit line.

In an embodiment of the present application, the step of forming the conductive element in the etching small hole further includes: doping the fin-shaped structure part exposed by the etching small hole with a first doping type; and filling the etching small holes with a conductive material to form the conductive component.

In an embodiment of the present application, the above steps further include: and polishing the surface of the conductive component.

In one embodiment of the present application, the gate and the conductive element are formed of conductive materials, including polysilicon or conductive metal materials.

In an embodiment of the present application, the material of each of the aforementioned semiconductors includes a silicon (Si) material or a silicon carbide (SiC) material.

In one embodiment of the present application, the insulating medium and the dielectric can be selectively made of insulating materials including silicon dioxide or benzocyclobutene (BCB) or Polyimide (PI), a composite layer of silicon dioxide and other materials, such as a composite layer of silicon dioxide and silicon nitride, a composite layer … of silicon dioxide and Polyimide (PI), and the like.

Another objective of the present invention is to provide a magnetic random access memory architecture, comprising a plurality of memory cells, each memory cell being disposed at a crossing of a bit line and a word line, wherein each memory cell comprises: a semiconductor region doped in an N + + type, the semiconductor region of the plurality of memory cells being adjoined to form a source line; a P-type doped fin structure disposed above the semiconductor region, a top end of the fin structure being disposed as a drain, a bottom end of the fin structure contacting a source formed by the semiconductor region; the gate is arranged on two sides of the fin-shaped structure and isolates the fin-shaped structure from the semiconductor region through an insulating medium, wherein the insulating medium is silicon oxide; the grid electrode, the fin-shaped structure and a source electrode formed by the semiconductor region form a vertical field effect transistor, the grid electrode controls the opening or closing of a conductive channel of the vertical field effect transistor, and the grid electrodes of the plurality of memory cells are mutually adjacent to form the word line; and a magnetic tunnel junction disposed above the fin structure to connect to the bit line and to a drain through the conductive element.

The gate is formed along the fin-shaped structure, so that the vertical field effect transistor is compatible to be used in a fin-shaped design, the forming density of the memory unit of the memory is improved, and the memory capacity of the memory is improved.

Drawings

FIG. 1 is a schematic diagram of an exemplary MRAM cell structure;

FIG. 2 is a schematic diagram of an exemplary magnetic tunnel junction structure in an MRAM memory cell;

FIG. 3 is a schematic diagram of an exemplary 3 MRAM cell structure;

FIG. 4 is an exemplary MRAM chip architecture diagram;

FIG. 5 is a schematic diagram of an exemplary 3D MRAM cell structure for FINFET technology;

FIG. 6A is a schematic diagram of a memory cell of an embodiment of the present invention;

FIG. 6B is a cross-sectional view of a memory cell perpendicular to a word line according to an embodiment of the present invention; and

fig. 7A to 7H are schematic structural changes in the manufacturing process of the memory cell according to the embodiment of the present application.

Description of the symbols

Low resistance state 01; 02, high resistance state; 03, a memory layer; 04 a tunnel barrier layer; 05 reference layer; 06: Bit lines (NMOS gate; Bit lines); 07 Magnetic Tunnel Junction (MTJ); 08: Word lines (Word lines); 09 source line connection point; 10 through holes/connection points; an N + doped region; a P-type substrate (P-type semiconductor substrate); MRAM array 13; a column address decoder 14; 15, column address interface device; address acquisition; 17, reading and writing control; 18, output and input control; source (Source); drain (Drain) 20; 21, a grid (Gate); fin (Fin structure); p-type Fin (P-type Fin structure); 24, a contact; 25: N + + region; 26 dielectric (oxide layer; oxide insulating layer); 27 source line; 28, long groove (trench); 29, small holes; s01, address; s02, other signals; s03 data

Detailed Description

The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. In the present invention, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc. refer to directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.

The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present invention is not limited thereto.

In the drawings, the range of configurations of devices, systems, components, circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of a magnetic random access memory architecture and a method for manufacturing the same according to the present invention, and the detailed implementation, structure, features and effects thereof will be made with reference to the accompanying drawings and embodiments.

FIG. 1 is a schematic diagram of an exemplary MRAM cell structure. As shown in FIG. 1, a schematic diagram of a magnetic tunnel junction in low resistance state 01 and high resistance state 02 is shown. The Magnetic Random Access Memory (MRAM) includes a memory layer 03, a tunnel barrier layer 04, and a reference layer 05, and the process of reading the Magnetic Random Access Memory (MRAM) is to measure the resistance of a magnetic tunnel junction 07 (MTJ). Using the newer STT-MRAM technology, writing the magnetic tunnel junction 07 is also simpler: a stronger current than reading is used for writing across the magnetic tunnel junction 07. A bottom-up current places the variable magnetization layer in a direction parallel to the fixed layer, and a top-down circuit places it in an anti-parallel direction.

FIG. 2 is a schematic diagram of an exemplary magnetic tunnel junction structure in an MRAM memory cell. As shown in fig. 2, the most basic Magnetic Random Access Memory (MRAM) cell consists of a magnetic tunnel junction 07 and a MOS transistor. The gate of the MOS transistor is connected to the word line 08 of the chip to turn on or off the cell, and the magnetic tunnel junction 07 and the MOS transistor are connected in series to the bit line 06 of the chip. Read and write operations are performed on bit line 06.

FIG. 3 is a schematic diagram of an exemplary 3 MRAM cell structure. As shown in fig. 3, the mos transistor is typically an NMOS transistor fabricated by a standard etching process, using a P-type semiconductor substrate 12 as a base, a magnetic tunnel junction 07 connected to a drain 20 through a via/contact 10, the drain 20 and a source 19 both being N + doped regions 11, the other end of the magnetic tunnel junction 07 being connected to a bit line 06, the N + doped region 11 being located on the P-type semiconductor substrate 12.

FIG. 4 is an exemplary MRAM chip architecture diagram. As shown in fig. 4, a Magnetic Random Access Memory (MRAM) chip is composed of one or more arrays 13 of MRAM memory cells, each array 13 having a number of external circuits, such as: the row address decoder 15: changing the received address S01 to the selection of word line 06, column address decoder 14: change the received address S01 to the selection of the bit line 06, the read/write control 17: controls read (measure) write (add current) operations on bit line 06, input output control 18: and external exchange data S03.

FIG. 5 is a schematic diagram of an exemplary 3D MRAM cell structure using FINFET technology. As shown in fig. 5, the FINFET has been used in higher process node mos technologies (below 14 nm), and the mos transistors have been semi-three-dimensional to provide satisfactory performance in smaller planar dimensions. The channel of the FINFET metal oxide semiconductor transistor is built on a three-dimensional Fin 22, with a gate 21 surrounding the Fin 22 on three sides.

FIG. 6A is a schematic diagram of a memory cell of an embodiment of the present invention, and FIG. 6B is a cross-sectional view of the memory cell perpendicular to a word line, for understanding. The MRAM architecture includes a plurality of memory cells, each memory cell having a structure in which bit lines and word lines are arranged in a perpendicular manner, wherein one end of the memory cell is connected to the bit line, and the other end is connected to the word line through a via/connection, so that each memory cell is disposed at a position where the bit line 06 intersects the word line 08, and each memory cell includes: a semiconductor region 25 of a first doping type; a fin structure 23 of the second doping type disposed on the semiconductor region 25, wherein a top end of the fin structure 23 is a drain, and a bottom end of the fin structure 23 contacts a source formed by the semiconductor region 25; a gate 21 disposed on two sides of the fin structure 23, wherein the gate 21 isolates the fin structure 23 from the semiconductor region 25 through an insulating medium 26, wherein the insulating medium is silicon oxide; and a magnetic tunnel junction 07 connected to the drain (the top portion of the fin structure 23) by a conductive element 24.

In some embodiments, the first doping type is N + + type and the second doping type is P-type.

In some embodiments, the semiconductor region 25 is constructed on a silicon wafer.

In some embodiments, the fin structures 23 of the plurality of memory cells corresponding to the same word line 08 are adjacent interconnects, and the gate 21 outside the fin structures 23 of the interconnect region is replaced by a partial wrap-around configuration. That is, the gate 21 is a three-sided ring disposed on the top and two sides of the fin structure 23 and extends along the fin structure 23. However, the opening of the gate 21 corresponds to the bit line 06, and the gate 21 is disposed on both sides of the fin 23 as if it is a structure of the memory cell. But in combination with the connecting regions of adjacent memory cells, the gate 21 is considered as a one-piece design.

In some embodiments, the fin structure 23 serves as a conductive channel with P-type doping inside. The gate 21, the fin-shaped structure 23 and the semiconductor region 25 form a metal oxide semiconductor field effect transistor (MOSFET, abbreviated as MOS transistor) with a vertical structure. The gate 21 controls the conduction channel of the MOS transistor to be turned on or off.

In some embodiments, the semiconductor regions 25 of a plurality of memory cells are connected to form a source line 27. The source line 27 may be formed by: (1) a plurality of memory cells, wherein the fin structures 23 are parallel and can be connected to the same bit line 06 as being in the same row; the semiconductor regions 25 of the memory cells in the same column are connected to each other to form source lines 27 corresponding to the memory cells in the same column; (2) several columns of semiconductor regions 25 may be connected to form a common source line 27.

As shown in fig. 6A-6B, in some embodiments, the top of the magnetic tunnel junction 07 contacts the bit line 06 and is electrically connected to the top of the fin 23, i.e., the drain, via the conductive element 24.

In some embodiments, the conductive element 24 is a via or contact of a material including titanium, tantalum, tungsten, titanium nitride, tantalum nitride, and combinations thereof.

Fig. 7A to 7G are schematic structural changes in the manufacturing process of the memory cell according to the embodiment of the present application. Method for manufacturing a magnetic random access memory, comprising at least the following steps:

as shown in fig. 7A, a semiconductor region 25 of the first doping type is formed in the semiconductor substrate 12 of the second doping type. In some embodiments, the semiconductor region 25 is formed in the semiconductor substrate 12 by ion implantation.

As shown in fig. 7B, the semiconductor substrate 12 is etched, and a fin structure 23 is formed on the surface of the semiconductor substrate 12. In some embodiments, the bottom of the fin structure 23 is formed by etching the semiconductor region 25.

As shown in fig. 7C, an insulating dielectric 26 is formed on the surface of the fin structure 23. A gate 21 is formed at the periphery of the fin structure 23, and the fin structure 23 is isolated from the fin structure 23 and the semiconductor region 25 by the insulating medium 26.

As shown in fig. 7D, the semiconductor region and the fin structure are covered by an insulating dielectric 26. The insulating medium is made of insulating materials and dielectric materials such as silicon oxide.

As shown in fig. 7E to 7G, a portion of the insulating dielectric 26 and the gate 21 are etched, and then the insulating dielectric 26 is filled, so as to form an etched hole 29 exposing a portion of the fin structure 23.

As shown in fig. 7E, in some embodiments, the step of etching the portions of the insulating medium 26 and the gate 21 is to etch the portions corresponding to the bit lines 06. At the location of the bit line 06 is an etched elongated slot, which is etched to expose a portion of the gate 21 (word line).

As illustrated in fig. 7F, in some embodiments, the gate 21 is further selectively etched within the etching trenches, so that a small portion of the fin structure 23 is exposed.

As shown in FIGS. 7G and 7H, FIG. 7H is a schematic view along section line A of FIG. 7G. In some embodiments, the etched slot is filled with an insulating dielectric 26 (or dielectric) to expose the fin structure 23 and the gate 21, and an etched hole 29 is formed at the location where the conductive element is needed to form the etched slot to expose the fin structure 23.

Conductive elements 24 are formed in the etched holes 29. In some embodiments, the step of forming the conductive element 24 in the etching small hole 29 further comprises: doping the fin-shaped structure 23 exposed by the etching small hole 29 with a first doping type (such as N + +); and filling the etched holes 29 with a conductive material to form the conductive elements 24. However, if desired, the surface of the conductive element 24 may be polished flat, such as by Chemical Mechanical Polishing (CMP).

FIG. 7D is a schematic view taken along the section line B of FIG. 7G. In some embodiments, one of the fin structures 23 may be elongated to form one row structure. The word line 08 is formed by connecting the gate 21 along a fin portion of the fin structure 23. As mentioned above, the gate 21 is extended from the fin structure 23, and the gate 21 of each memory cell is also structurally connected to each other.

The difference between the present application and a conventional Fin-like Field Effect Transistor (FINFET) is that the gate and Fin structure of the FINFET are perpendicular to each other, the gate 21 disclosed in the present application is grown along the Fin structure 23, the semiconductor region 25 on the silicon chip is connected to form a source line 27, and the bit line 06 is perpendicular to the Fin structure 23 and the word line 08. In the memory cell, the gate 21 is on both sides of the fin structure 23, and the gate 21 may alternatively surround the fin structure 23 on three sides in the connection region of the memory cell. Thereafter, a magnetic tunnel junction 07 is formed over the conductive element 24, and the magnetic tunnel junction 07 is connected by a bit line 06, as shown in fig. 6A-6B.

Referring to fig. 6A-6B, a magnetic random access memory architecture of the present application includes a plurality of memory cells, each memory cell disposed at an intersection of a bit line 06 and a word line 08, wherein each memory cell includes: a semiconductor region 25 doped in an N + + type, the semiconductor region 25 of the plurality of memory cells being adjacent to form a source line 27; a P-type doped fin structure 23 disposed above the semiconductor region 25, wherein a top end of the fin structure 23 is a drain and a bottom end of the fin structure 23 contacts a source formed by the semiconductor region 25; a gate 21 disposed on two sides of the fin structure 23, wherein the gate 21 isolates the fin structure 23 from the semiconductor region 25 through an insulating medium, such as silicon oxide, sources formed by the gate 21, the fin structure 23 and the semiconductor region 25 constitute a vertical field effect transistor, the gate 21 controls the on/off of a conductive channel of the vertical field effect transistor, and the gates 21 of the plurality of memory cells are adjacent to each other to form the word line 08; and a magnetic tunnel junction 07 disposed above the fin structure 23 to connect to the bit line 06 and to connect to a drain through the conductive element 24.

The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This phrase generally does not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.

Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.

Claims

1. A magnetic random access memory architecture, comprising a plurality of memory cells, each memory cell disposed at a location where a bit line intersects a word line, wherein each memory cell comprises:

a semiconductor region of a first doping type;

a fin structure of a second doping type disposed on the semiconductor region, a top end of the fin structure being disposed as a drain, a bottom end of the fin structure contacting a source formed by the semiconductor region;

the grid electrode is arranged on two sides of the fin-shaped structure and isolates the fin-shaped structure from the semiconductor region through an insulating medium; and

a magnetic tunnel junction connected to the drain by a conductive element.

2. The magnetic random access memory architecture of claim 1, wherein the fin structure acts as a conductive channel, the gate controlling the opening or closing of the conductive channel.

3. The magnetic random access memory architecture of claim 1 wherein the word lines are formed for the gates connected along the fins.

4. The MRAM architecture of claim 1, wherein the semiconductor region of each memory cell comprises a source, the sources of the semiconductor regions of the plurality of memory cells being connected to form a source line.

5. The MRAM architecture of claim 1, wherein the fins of the plurality of memory cells corresponding to a same word line are adjacent interconnects, and wherein the gate outside the fin of the interconnect region is replaced by a partial wrap-around configuration.

6. The magnetic random memory architecture of claim 1, wherein the magnetic tunnel junction top contacts the bit line.

7. The magnetic random access memory architecture of claim 1, wherein the conductive element is a via or a contact.

8. The magnetic random access memory architecture of claim 1 wherein the first doping type is N + + type and the second doping type is P-type.

9. A method of fabricating a magnetic random access memory, comprising:

forming a semiconductor region of a first doping type in a semiconductor substrate of a second doping type;

etching the semiconductor substrate to form a fin-shaped structure on the surface of the semiconductor substrate;

forming an insulating medium on the surface of the fin-shaped structure;

forming a gate at a periphery of the fin structure, the fin structure being isolated from the fin structure and the semiconductor region by the insulating dielectric;

covering the semiconductor region and the fin structure with an insulating medium;

etching part of the insulating medium and the grid electrode, and filling the insulating medium to form an etching small hole exposing part of the fin-shaped structure;

forming a conductive element in the etching small hole;

forming a magnetic tunnel junction over the conductive element; and

the magnetic tunnel junctions are connected by bit lines.

10. The method of manufacturing a magnetic random access memory according to claim 9, wherein the semiconductor region is formed in the semiconductor substrate by an ion implantation method.

11. The method of claim 9, wherein a bottom of the fin structure is formed by etching the semiconductor region.

12. The method of claim 9, wherein the etching of the portion of the insulating dielectric and the gate is performed to etch the portion of the corresponding bit line.

13. The method of claim 9, wherein the step of forming a conductive element in the etched hole further comprises:

doping the fin-shaped structure part exposed by the etching small hole with a first doping type; and

filling the etched holes with a conductive material to form the conductive component.

14. The method of manufacturing a magnetic random access memory of claim 13, further comprising: and polishing the surface of the conductive component.

15. A magnetic random access memory architecture, comprising a plurality of memory cells, each memory cell disposed at a location where a bit line intersects a word line, wherein each memory cell comprises:

a semiconductor region doped in an N + + type, the semiconductor region of the plurality of memory cells being adjoined to form a source line;

a P-type doped fin structure disposed above the semiconductor region, a top end of the fin structure being disposed as a drain, a bottom end of the fin structure contacting a source formed by the semiconductor region;

the grid electrode is arranged on two sides of the fin-shaped structure, the fin-shaped structure and the semiconductor region are isolated by the grid electrode through an insulating medium, a vertical field effect transistor is formed by the grid electrode, the fin-shaped structure and a source electrode formed by the semiconductor region, the grid electrode controls the opening or closing of a conducting channel of the vertical field effect transistor, and the grid electrodes of the plurality of storage units are adjacent to each other to form the word line; and

a magnetic tunnel junction disposed above the fin structure to connect to the bit line and to a drain through a conductive element.