CN114203897A

CN114203897A - Magnetic random access memory architecture and manufacturing method thereof

Info

Publication number: CN114203897A
Application number: CN202010912776.6A
Authority: CN
Inventors: 戴瑾; 吴关平
Original assignee: Shanghai Information Technologies Co ltd
Current assignee: Shanghai Information Technologies Co ltd
Priority date: 2020-09-02
Filing date: 2020-09-02
Publication date: 2022-03-18

Abstract

The present application provides a magnetic random access memory architecture and a manufacturing method thereof, wherein at least one of a source line of a memory and a contact point connected with a magnetic tunnel junction is formed by a self-alignment technology, so that the distance between the source line and a word line can be effectively compressed, and the density of memory cells of the magnetic random access memory architecture is further improved.

Description

Magnetic random access memory architecture and manufacturing method thereof

Technical Field

The present invention relates to the field of memory technology, and more particularly, to a magnetic random access memory architecture and a method of manufacturing the same.

Background

A Magnetic Random Access Memory (MRAM) is applied to an embedded memory structure, and has a very small silicon area occupied by unit capacity and great advantages compared with an SRAM; the number of additional photomasks required in the manufacturing process is small, and the cost advantage is larger than that of the embedded NOR Flash. MRAM also has a relatively good performance, with read and write latencies close to SRAM, and power consumption much lower than flash memory. Also MRAM is not compatible with standard CMOS semiconductor processes like DRAM and Flash. The MRAM may be integrated with the logic circuit in one chip.

However, the MRAM is still limited by the limitations of the general CMOS process (logic process). The CMOS design rule requires that the connection point of the MOS tube and the grid electrode keep a certain distance, which prevents the miniaturization of the memory cell. According to the prior art, the MTJ is typically seated on a layer of copper metal. The design rule for copper metal requires a minimum area for each piece of copper metal. This rule also further prevents miniaturization of the memory cell.

For example, U.S. Pat. No. US9129893 discloses a magnetic random access memory, in which a metal oxide semiconductor transistor, typically an NMOS transistor, is fabricated by a standard etching process, using a P-type semiconductor substrate as a base, a magnetic tunnel junction is connected to a drain through a via/connection point, the drain and a source are both N + doped regions, the other end of the magnetic tunnel junction is connected to a bit line, and the N + doped region is located on the P-type semiconductor substrate. Wherein two memory cells share a source line.

Disclosure of Invention

In order to solve the above-mentioned problems, it is an object of the present invention to provide a magnetic random access memory architecture and a method for manufacturing the same, which forms a design of a memory cell through a self-aligned fabrication process.

The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme.

According to the present application, a magnetic random access memory architecture includes a memory array disposed in a plurality of active regions, the memory array comprising: a plurality of word lines parallel to each other and arranged over the plurality of active regions; inserting a dummy word line into every two word lines; a plurality of source lines which are parallel to each other and cross over the plurality of active regions; a plurality of contact points which are parallel to the plurality of source lines and are separately arranged above the plurality of active regions; a plurality of magnetic tunnel junctions distributed above the plurality of contact points in a manner corresponding to the positions of the plurality of contact points; at least one of the source lines and the contact points is formed between the word lines or between the dummy word lines by a self-alignment technique.

The technical problem solved by the application can be further realized by adopting the following technical measures.

Optionally, in the plurality of source lines, each source line is disposed between adjacent word lines to form a common source line structure.

Optionally, the shape of the plurality of contact points is selectively at least one of square, circle, rectangle and ellipse.

Optionally, a contact point is arranged between the word line and the dummy word line, and the magnetic tunnel junctions of two adjacent rows across the dummy word line are arranged in a staggered manner.

Optionally, the contact and the source line are formed of tungsten.

Alternatively, part or all of the plurality of source lines may be replaced by an alternative configuration in which elongated contacts straddling the source region are disposed in adjacent rows of the contacts, and the elongated contacts are bridged with the contacts to form the source lines.

Alternatively, part or all of the plurality of source lines may be formed by extending and connecting the plurality of active regions instead of the following alternative configuration.

Another object of the present application is a method of manufacturing a magnetic random access memory, comprising: forming a plurality of word lines and more than one dummy word line on the active region, and forming a doped region connecting the word lines and the dummy word lines; covering the plurality of word lines and the dummy word line by a first medium; etching the first medium according to the preset positions of the source line and the contact point to form a groove part; filling through the groove part to form a contact point and a source line; forming a magnetic tunnel junction on the contact point by deposition and etching, and filling a second medium to surround the periphery; a bit line is disposed over the magnetic tunnel junction.

Optionally, the positioning of the etching and doping is assisted by a mask, including: arranging a mask above the first medium; etching the mask according to the preset positions of the source line and the contact point by a self-alignment technology to form a first opening; etching a preset position of the first medium through a first opening to form a groove part; ion implantation is carried out on the groove part through the first opening, and a doped region is formed in the active region; filling through the first opening to form the source line and the contact point; and removing the mask.

Optionally, a via is disposed above the magnetic tunnel junction and connected to the bit line through the via.

Optionally, the positioning is assisted by a mask, including: arranging a mask above the second medium; etching the mask according to the preset position of the magnetic tunnel junction to form a second opening; etching the second dielectric through a second opening to form the recess; depositing the recess through the second opening to form the magnetic tunnel junction; and removing the mask.

Optionally, the first medium and the second medium are made of the same or different materials.

The self-aligned word line structure is formed through a self-aligned technology, so that the distance between the word line and the word line can be effectively compressed, and the density of the storage unit of the magnetic random access memory structure is improved.

Drawings

FIG. 1 is a schematic diagram of an exemplary MRAM cell structure;

FIG. 2 is a schematic diagram of an exemplary magnetic tunnel junction structure in an MRAM memory cell;

FIG. 3 is a schematic diagram of an exemplary 3 MRAM cell structure;

FIG. 4 is an exemplary MRAM chip architecture diagram;

FIG. 5A is a schematic diagram of a memory array of an embodiment of the present invention;

FIG. 5B is a schematic diagram of a memory array of an embodiment of the present invention;

FIG. 5C is a schematic diagram of a memory array of an embodiment of the present invention;

FIGS. 6A-6E are schematic views illustrating a manufacturing process of a memory cell according to an embodiment of the present invention;

fig. 7A to 7D are schematic views illustrating the mask etching and doping assistance according to the embodiment of the present disclosure.

Detailed Description

The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. In the present invention, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc. refer to directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.

The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present invention is not limited thereto.

In the drawings, the range of configurations of devices, systems, components, circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of a magnetic random access memory architecture and a method for manufacturing the same according to the present invention, and the detailed implementation, structure, features and effects thereof will be made with reference to the accompanying drawings and embodiments.

FIG. 1 is a schematic diagram of an exemplary MRAM cell structure. As shown in FIG. 1, a schematic diagram of a magnetic tunnel junction in low resistance state 01 and high resistance state 02 is shown. The Magnetic Random Access Memory (MRAM) includes a memory layer 03, a tunnel barrier layer 04, and a reference layer 05, and the process of reading the Magnetic Random Access Memory (MRAM) is to measure the resistance of a magnetic tunnel junction 07 (MTJ). Using the newer STT-MRAM technology, writing the magnetic tunnel junction 07 is also simpler: a stronger current than reading is used for writing across the magnetic tunnel junction 07. A bottom-up current places the variable magnetization layer in a direction parallel to the fixed layer, and a top-down circuit places it in an anti-parallel direction.

FIG. 2 is a schematic diagram of an exemplary magnetic tunnel junction structure in an MRAM memory cell. As shown in fig. 2, the most basic Magnetic Random Access Memory (MRAM) cell consists of a magnetic tunnel junction MTJ and a MOS transistor. The grid of the MOS tube is connected to the word line of the chip to switch on or switch off the unit, and the upper and lower parts of the magnetic tunnel junction are connected with the MOS tube in series to the bit line of the chip through a via hole (top/bottom electrode), a metal layer and a contact point respectively. The read and write operations are performed on bit lines. Wherein two memory cells share a source line.

FIG. 3 is a schematic diagram of an exemplary MRAM cell structure. As shown in fig. 3, the mos transistor is generally an NMOS transistor fabricated by a standard etching process, and is based on a P-type semiconductor substrate, a magnetic tunnel junction is connected to a drain through a via (top/bottom electrode), a metal layer and a contact, the drain and the source are both N + doped regions, the other end of the magnetic tunnel junction MTJ is connected to a bit line, and the N + doped region is located on the P-type semiconductor substrate. Wherein two memory cells share a source line.

FIG. 4 is an exemplary MRAM chip architecture diagram. As shown in fig. 4, a Magnetic Random Access Memory (MRAM) chip is composed of one or more arrays 13 of MRAM memory cells, each array 13 having a number of external circuits, such as: the row address decoder 15: changing the received address S01 to the selection of word line 06, column address decoder 14: change the received address S01 to the selection of the bit line 06, the read/write control 17: controls read (measure) write (add current) operations on bit line 06, input output control 18: and external exchange data S03.

FIG. 5A is a schematic diagram of a memory array of an embodiment of the present invention. The magnetic random access memory architecture comprises a memory array arranged in a plurality of Active Areas (AA), and the memory array comprises: a plurality of Word Lines (WL) parallel to each other and arranged over the plurality of active regions; inserting a Dummy word line (Dummy WL) for every two word lines; a plurality of Source Lines (SL) parallel to each other and arranged over the plurality of active regions; a plurality of contacts (Contact) spaced apart from and disposed above the plurality of active regions in parallel with the plurality of Source Lines (SL); a plurality of Magnetic Tunnel Junctions (MTJ) disposed above the plurality of contacts (contacts) in a manner corresponding to the positions of the plurality of contacts (contacts); wherein at least one of each of the plurality of Source Lines (SL) and each of the plurality of contacts (Contact) is formed between the Word Line (WL) and the Word Line (WL) or between the Word Line (WL) and the Dummy word line (Dummy WL) by a self-alignment technique.

Optionally, in the plurality of source lines, each Source Line (SL) is disposed between adjacent Word Lines (WL) to form a shared source line structure.

Optionally, the shape of the plurality of Contact points (contacts) is at least one of square, circle, rectangle and ellipse.

Optionally, a Contact (Contact) is disposed between the Word Line (WL) and the Dummy word line (Dummy WL), and the magnetic tunnel junctions of two adjacent rows across the Dummy word line are disposed in a staggered manner, so that the space can be utilized more effectively.

Alternatively, the contact, between the Word Line (WL) and the Dummy word line (Dummy WL), is made of tungsten as in the contact of the general MOS. More preferably rectangular/elliptical, in addition to square/circular. Made using self-aligned techniques, the distance between the Contact (Contact) and the Word Line (WL) is compressed.

Optionally, a source line. Between two Word Lines (WL), made of tungsten as in the case of the contacts of a normal MOS, but elongated to span multiple columns, forming Source Lines (SL). Made using self-aligned techniques, the distance to the Word Lines (WL) is compressed.

Optionally, the Magnetic Tunnel Junction (MTJ) is formed above the Contact (Contact), and the distance is more uniform by designing the two adjacent rows to have a dislocation.

Optionally, the Dummy word line (Dummy WL) is a Dummy word line, and a direct low voltage is used for isolation.

FIG. 5B is a schematic diagram of a memory array of an embodiment of the present invention. Alternatively, a part or all of the plurality of source lines SL may be replaced with an alternative configuration in which elongated contacts (Extended contacts) straddling the source region AA are disposed in adjacent rows of the contacts (contacts), and the elongated contacts (Extended contacts) and the contacts (contacts) are bridged to form the source lines SL. This architecture reduces the adjacent length of the MTJ contact and the source line SL contact, thereby reducing the likelihood of shorting the two and improving yield.

FIG. 5C is a schematic diagram of a memory array of an embodiment of the present invention. Alternatively, part or all of the plurality of source lines SL may be formed by extending and connecting the plurality of active regions AA in an alternative configuration as follows. That is, the active region AA is extended such that adjacent source regions (regions between two word lines) in the same row are connected to each other by forming a Bridge structure (AA Bridge). However, the drain region between the word line WL and the Dummy word line (Dummy WL) remains separated, thereby forming a source line SL. The method has the advantage of being beneficial to further improving the yield of products. Alternatively, the resistance may be reduced by covering a silicide (salicide) layer on the source lines SL. At this time, a free column may be added every plural columns, and at the position of the free column, source line SL contacts (contacts) leading to metal source lines SL of lower resistance are still provided by the self-alignment method described above.

Fig. 6A to 6E are schematic structural changes of a memory cell manufacturing process according to an embodiment of the present application. Method for manufacturing a magnetic random access memory, comprising at least the following steps:

as shown in fig. 6A, a plurality of word lines WL and one or more Dummy word lines (Dummy WL) are formed on the active area AA, and then a doped region connecting the word lines and the Dummy word lines is formed. The formation of the word line WL and the dummy word line is not limited. The active region is illustrated as a P-type substrate. The plurality of word lines WL and the Dummy word line (Dummy WL) are covered by a first medium. Optionally, the first dielectric is a dielectric or an insulating dielectric.

As shown in fig. 6B, a self-aligned technique is used to etch the first dielectric to form a trench according to the predetermined position of the source line SL and the Contact (Contact).

As shown in fig. 6C, the source lines SL and the contacts (contacts) are formed by filling the trenches with tungsten. Optionally, after Contact fabrication is completed, a CMP polishing process may be used to planarize the surface.

As shown in fig. 6D, a magnetic tunnel junction MTJ is formed on the Contact point (Contact) by deposition and etching, and a second medium is filled to surround the periphery. Optionally, the second dielectric is a dielectric or an insulating dielectric. Optionally, the second medium is the same as or different from the first medium.

As shown in fig. 6E, a Bit Line (BL) is disposed above the magnetic tunnel junction MTJ.

Fig. 7A to 7D are schematic views illustrating the mask etching and doping assistance according to the embodiment of the present disclosure. Please refer to fig. 6C to fig. 6E. The method comprises the following steps:

as shown in fig. 7A, a mask is disposed over the first dielectric.

As shown in fig. 7B, the mask is etched to form openings according to the predetermined positions of the source lines SL and the contacts (contacts). And etching the preset position of the first medium through the opening to form a groove part.

As shown in fig. 7C, the source line SL and the Contact (Contact) are formed by filling the opening.

As shown in fig. 7D, the mask is removed.

Optionally, a via is disposed on the magnetic tunnel junction MTJ and connected to the bit line BL through the via.

Optionally, the magnetic tunnel junction MTJ may be formed by mask-assisted positioning, including: arranging a mask above the second medium; etching the mask according to the preset position of the Magnetic Tunnel Junction (MTJ) to form a second opening; etching the second dielectric through a second opening to form the recess; depositing the recess through the second opening, forming the magnetic tunnel junction MTJ; and removing the mask.

In an embodiment of the present application, the material of each of the aforementioned semiconductors includes a silicon (Si) material or a silicon carbide (SiC) material.

In one embodiment of the present application, the insulating medium and the dielectric can be selectively made of insulating materials including silicon dioxide or benzocyclobutene (BCB) or Polyimide (PI), a composite layer of silicon dioxide and other materials, such as a composite layer of silicon dioxide and silicon nitride, a composite layer … of silicon dioxide and Polyimide (PI), and the like.

The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This phrase generally does not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.

Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.

Claims

1. A magnetic random access memory architecture comprising a memory array disposed in a plurality of active regions, the memory array comprising:

a plurality of word lines parallel to each other and arranged over the plurality of active regions;

inserting a dummy word line into every two word lines;

a plurality of source lines which are parallel to each other and cross over the plurality of active regions;

a plurality of contact points which are parallel to the plurality of source lines and are separately arranged above the plurality of active regions;

a plurality of magnetic tunnel junctions distributed above the plurality of contact points in a manner corresponding to the positions of the plurality of contact points;

at least one of the source lines and the contact points is formed between the word lines or between the dummy word lines by a self-alignment technique.

2. The MRAM architecture of claim 1, wherein the plurality of contact points are selectively at least one of square, circular, rectangular, and elliptical in shape.

3. The MRAM architecture of claim 1, wherein a contact point is disposed between the word line and the dummy word line, and the magnetic tunnel junctions of two adjacent rows across the dummy word line are offset.

4. The magnetic random access memory architecture of claim 1, wherein the contact and source lines are formed of tungsten.

5. The MRAM architecture of claim 1, wherein some or all of the plurality of source lines are alternatively configured such that adjacent columns of contacts are provided with elongated contacts that span the source region, the elongated contacts bridging the contacts to form source lines.

6. The MRAM architecture of claim 1, wherein some or all of the plurality of source lines are alternatively configured to be formed by the plurality of active region extension connections.

7. A method of fabricating a magnetic random access memory, comprising:

forming a plurality of word lines and dummy word lines on the active region, forming a doped region connecting the word lines and the dummy word lines, and filling a first medium;

etching the first medium to form a groove part according to the preset positions of a source line and a contact point by a self-alignment technology;

filling through the groove part to form a contact point and a source line;

forming a magnetic tunnel junction on the contact point by deposition and etching, and filling the periphery surrounded by a second medium;

a bit line is disposed over the magnetic tunnel junction.

8. The method of claim 7, wherein a via is disposed above the magnetic tunnel junction and connected to the bit line through the via.

9. The method of claim 7, wherein the first medium and the second medium are the same or different materials.

10. The method of claim 7, wherein the magnetic tunnel junctions of two adjacent rows are in a staggered arrangement; the contact and source line are formed of tungsten.