CN1707695A - Memory device with memory matrix used for multi-bit inputting/outputting - Google Patents

Memory device with memory matrix used for multi-bit inputting/outputting Download PDF

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Publication number
CN1707695A
CN1707695A CNA200510073763XA CN200510073763A CN1707695A CN 1707695 A CN1707695 A CN 1707695A CN A200510073763X A CNA200510073763X A CN A200510073763XA CN 200510073763 A CN200510073763 A CN 200510073763A CN 1707695 A CN1707695 A CN 1707695A
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China
Prior art keywords
plate
memory bank
storage unit
data line
semiconductor
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CNA200510073763XA
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Chinese (zh)
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高桥弘行
加藤义之
园田正俊
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NEC Electronics Corp
NEC Corp
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NEC Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

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  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

In a semiconductor apparatus for a multi-bit input/output function, a semiconductor memory chip includes 3<SUP>m </SUP>rows, 3<SUP>m </SUP>columns (m=1, 2, . . . ) of memory banks, each having a plurality of input/output terminals. The memory banks are adapted to carry out the same operation so that a predetermined number of bits are accessed from the input/output terminals of each of the memory banks.

Description

Memory device with the memory matrix that is used for many bits I/O function
Technical field
The present invention relates to a kind of semiconductor devices, more specifically, relate to a kind of semiconductor storage unit, for example dynamic RAM (DRAM) device.
Background technology
People have developed the DRAM device with high functionality and high integration.
A kind ofly realize that the method for high functionality is many bits I/O function.For example, the 32 bit I/O functions of having developed the 4 bit I/O functions that are associated with a check bit, the 8 bit I/O functions that are associated with a check bit, the 16 bit I/O functions that are associated with two check bits and being associated with four check bits.In addition, will develop 2 nBit (n=6,7 ...) the I/O function.This many bit function will increase at the peripheral edge place of semi-conductor chip or the number of the input/output terminal that its long side (long-side) edge is provided with.
On the other hand, when improving integrated level significantly, also precise construction storage unit and transistorized circuit, simultaneously, increased chip-scale.When increasing chip-scale, make connection longer, this can increase its capacity.As a result, because the transmission speed of control signal and data-signal reduces, can't expect access at a high speed.
By the memory cell array that is divided into a plurality of plates (plate) (sub-piece) and a plurality of I/O contacts construct the 8 bit I/O functions that are associated with a check bit the prior art semiconductor storage unit (referring to: JP-8-315578-A).In this case, outer peripheral is provided with half I/O contact on memory cell array, and second half I/O contact is arranged on the following exterior circumferential of memory cell array.This will describe in detail subsequently.
Yet in above-mentioned prior art semiconductor storage unit, in concrete job step (step), although only need one of activating plate, two have all been activated, and have therefore increased power consumption.
In addition, in above-mentioned prior art semiconductor storage unit, owing to the distance between I/O contact and the unit greatly fluctuates, and the plate skewness that is activated, can not expect access at a high speed.
Summary of the invention
The purpose of this invention is to provide a kind of semiconductor storage unit that is used for many bits I/O function, can reduce power consumption and increase access speed.
According to the present invention, at a kind of semiconductor equipment that is used for many bits I/O function, semiconductor memory chips comprise 3 mRow, 3 mRow (m=1,2 ...) and memory bank, each memory bank has a plurality of input/output terminals.Memory bank is suitable for carrying out identical operations, so that from the bit of the input/output terminal access predetermined number of each memory bank.
Description of drawings
With reference to the accompanying drawings, compared with prior art, can more be expressly understood the present invention from following explanation, wherein:
Figure 1A, 1B show the frame circuit diagram of prior art semiconductor storage unit;
Fig. 2 A to 2D be used for key drawing 1 semiconductor storage unit * figure of 36b4 operation;
Fig. 3 A to 3D be used for key drawing 1 semiconductor storage unit * figure of 18b4 operation;
Fig. 4 A to 4D be used for key drawing 1 semiconductor storage unit * figure of 9b4 operation;
Fig. 5 A and 5B are the figure of problem that is used for the semiconductor storage unit of key drawing 1;
Fig. 6 shows the frame circuit diagram according to the embodiment of semiconductor storage unit of the present invention;
Fig. 7 is the detailed frame circuit diagram of one of memory bank of Fig. 6;
Fig. 8 is the detailed frame circuit diagram of one of plate of Fig. 7;
Fig. 9 and 10A to 10D be used for key drawing 7 and 8 semiconductor storage unit * figure of 36b4 operation;
Figure 11 and 12A to 12D be used for key drawing 7 and 8 semiconductor storage unit * figure of 18b4 operation;
Figure 13 and 14 A to 14D be used for key drawing 7 and 8 semiconductor storage unit * figure of 9b4 operation;
Figure 15 A is the sectional view of semiconductor packages that the semiconductor storage unit of Fig. 6 has been installed;
Figure 15 B is the planimetric map of the semiconductor storage unit of Figure 15 A;
Figure 15 C is the planimetric map of the insertion substrate of Figure 15 A; And
Figure 16 and 17 is frame circuit diagrams of modification of the memory bank of Fig. 7.
Embodiment
Before the explanation of preferred embodiment, will be with reference to figure 1,2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, 4A, 4B, 4C, 4D, 5A and 5B, illustrate prior art semiconductor storage unit (referring to: JP-8-315578-A).
In Fig. 1, show the prior art semiconductor storage unit that is used for the 8 bit I/O functions that are associated with a check bit, utilize to be divided into the individual plate 101 in 2 * 4 (=8), 102 ..., 108 and 36 input/output terminals or contact p1, p2, ..., p18, p19, p20, ..., the memory cell array of p36 is constructed this semiconductor storage unit.In this case, the outer peripheral place is provided with I/O contact p1 on memory cell array, p2 ..., p18, and I/O contact p19 is set at the following outer peripheral place of memory cell array, p20 ..., p36.
By a plurality of memory features (mat) m1, m2... constructs each plate 101,102 ... 108, each memory feature is by nine data unit u1, u2 ... u9 forms, and each data cell comprises two data lines.Data cell u1, u2 ... u9 respectively with selector switch s1, s2 ... s9 links to each other.In addition, selector switch s1 with write amplifier/sense amplifier circuit a1 and link to each other, selector switch s2 with write amplifier/sense amplifier circuit a2 and link to each other ..., and selector switch s9 with write amplifier/sense amplifier circuit a9 and link to each other.
I/O contact p1 is set, p2 ..., p9 is used for plate 101 and 102.Promptly, plate 101 links to each other with I/O contact p1 with 102 the amplifier/sense amplifier circuit a1 that writes, plate 101 links to each other with I/O contact p2 with 102 the amplifier/sense amplifier circuit a2 that writes, ..., plate 101 links to each other with I/O contact p9 with 102 the amplifier/sense amplifier circuit a9 that writes.
I/O contact p10 is set, p11 ..., p18 is used for plate 103 and 104.Promptly, plate 103 links to each other with I/O contact p10 with 104 the amplifier/sense amplifier circuit a1 that writes, plate 103 links to each other with I/O contact p11 with 104 the amplifier/sense amplifier circuit a2 that writes, ..., plate 103 links to each other with I/O contact p18 with 104 the amplifier/sense amplifier circuit a9 that writes.
I/O contact p19 is set, p20 ..., p27 is used for plate 105 and 106.Promptly, plate 105 links to each other with I/O contact p19 with 106 the amplifier/sense amplifier circuit a1 that writes, plate 105 links to each other with I/O contact p20 with 106 the amplifier/sense amplifier circuit a2 that writes, ..., plate 105 links to each other with I/O contact p27 with 106 the amplifier/sense amplifier circuit a9 that writes.
I/O contact p28 is set, p29 ..., p36 is used for plate 107 and 108.Promptly, plate 107 links to each other with I/O contact p28 with 108 the amplifier/sense amplifier circuit a1 that writes, plate 107 links to each other with I/O contact p29 with 108 the amplifier/sense amplifier circuit a2 that writes, ..., plate 107 links to each other with I/O contact p36 with 108 the amplifier/sense amplifier circuit a9 that writes.
In addition, be provided with controller 109, be used to activate activation signal A1, A2, A3 and the A4 that writes amplifier or sensor amplifier, character group (burst) signal B1, B2, B3 and B4, and X address signal and Y address signal with generation.Notice that activation signal A1, A2, A3 and A4 activate the corresponding amplifier that writes in writing pattern, and in read mode, activate corresponding sensor amplifier.
By the selector switch s1 that character group signal B1 and B2 control and plate 101 link to each other with 105, s2 ..., s9, and write amplifier/sense amplifier circuit a1 by what activation signal A1 activation and plate 101 linked to each other with 105, a2 ... a9.
By the selector switch s1 that character group signal B3 and B4 control and plate 102 link to each other with 106, s2 ..., s9, and write amplifier/sense amplifier circuit a1 by what activation signal A2 activation and plate 102 linked to each other with 106, a2 ... a9.
By the selector switch s1 that character group signal B1 and B2 control and plate 103 link to each other with 107, s2 ..., s9, and write amplifier/sense amplifier circuit a1 by what activation signal A3 activation and plate 103 linked to each other with 107, a2 ... a9.
By the selector switch s1 that character group signal B3 and B4 control and plate 104 link to each other with 108, s2 ..., s9, and write amplifier/sense amplifier circuit a1 by what activation signal A4 activation and plate 104 linked to each other with 108, a2 ... a9.
Next, will with reference to figure 2A, 2B, 2C and 2D illustrate Fig. 1 semiconductor storage unit * 36b4 operation.Here, " * 36 " index is 36 bits according to width, and " b4 " refers to that character group (burst) length is 4.
At first, shown in Fig. 2 A, controller 109 produces activation signal A1 and A3, with activating plate 101,103,105 and 106.In addition, controller 109 produces character group signal B1, so as the selector switch s1 of plate 101,103,105 and 109, s2 ..., s9 selects the left data of data selected unit.
Next, shown in Fig. 2 B, controller 109 produces activation signal A1 and A3, with activating plate 101,103,105 and 106.In addition, controller 109 produces character group signal B2, so as the selector switch s1 of plate 101,103,105 and 109, s2 ..., s9 selects the right side data of data selected unit.
Next, shown in Fig. 2 C, controller 109 produces activation signal A2 and A4, with activating plate 102,104,106 and 108.In addition, controller 109 produces character group signal B3, so as the selector switch s1 of plate 102,104,106 and 108, s2 ..., s9 selects the left data of data selected unit.
At last, shown in Fig. 2 D, controller 109 produces activation signal A2 and A4, with activating plate 102,104,106 and 108.In addition, controller 109 produces character group signal B4, so as the selector switch s1 of plate 102,104,106 and 108, s2 ..., s9 selects the right side data of data selected unit.
Thus, in each step of * 36b4 operation, activated plate 101,102 ..., in 108 four.
Next, will with reference to figure 3A, 3B, 3C and 3D illustrate Fig. 1 semiconductor storage unit * 18b4 operation.Here, " * 18 " index is 18 bits according to width, and " b4 " refers to that character group length is 4.
At first, as shown in Figure 3A, controller 109 produces activation signal A1, with activating plate 101 and 105.In addition, controller 109 produces character group signal B1, so as the selector switch s1 of plate 101 and 105, s2 ..., s9 selects the left data of data selected unit.
Next, shown in Fig. 3 B, controller 109 produces activation signal A1, with activating plate 101 and 105.In addition, controller 109 produces character group signal B2, so as the selector switch s1 of plate 101 and 105, s2 ..., s9 selects the right side data of data selected unit.
Next, shown in Fig. 3 C, controller 109 produces activation signal A2, with activating plate 102 and 106.In addition, controller 109 produces character group signal B3, so as the selector switch s1 of plate 102 and 106, s2 ..., s9 selects the left data of data selected unit.
At last, shown in Fig. 3 D, controller 109 produces activation signal A2, with activating plate 102 and 106.In addition, controller 109 produces character group signal B4, so as the selector switch s1 of plate 102 and 106, s2 ..., s9 selects the right side data of data selected unit.
Thus, in each step of * 18b4 operation, activated plate 101,102 ..., in 108 two.
Next, will with reference to figure 4A, 4B, 4C and 4D illustrate Fig. 1 semiconductor storage unit * 9b4 operation.Here, " * 9 " index is 9 bits according to width, and " b4 " refers to that character group length is 4.That is, Fig. 4 A, 4B, 4C and 4D and Fig. 3 A, 3B, 3C and 3D are identical.
Therefore, in each step of * 9b4 operation, also activating plate 101,102 ..., in 108 two.In this case, I/O contact p1, p2 ..., p9 is effectively, and I/O contact p10, p20 ..., p27 is invalid.As a result,, activated wherein two, therefore increased power consumption although only need one of activating plate 101,102,105 and 106.
In addition, in Fig. 1, I/O contact p1, p2 ..., p9, p10, p20 ..., p27, p28, p29 ..., the distance between p36 and the unit greatly fluctuates.For example, shown in Fig. 5 A, minor increment be between I/O contact p1 and the unit C1 apart from d1.On the other hand, shown in Fig. 5 B, ultimate range is the distance between I/O contact p1 and the unit C2, and it is expressed as
d1+2X+Y
Wherein X is the width (arbitrary unit) of a plate;
Y is the length (arbitrary unit) of a plate.In addition, shown in Fig. 2 A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, 4A, 4B, 4C and 4D, the plate uneven distribution that is activated.As a result, because access speed depends on the above-mentioned ultimate range of the plate that is activated, can not expect access at a high speed.
In Fig. 6, show embodiment according to semiconductor storage unit of the present invention, this semiconductor storage unit is divided into the individual memory bank 1-1 in 3 * 3 (=9) with mutually the same structure, 1-2 ..., 1-9.In addition, at memory bank 1-1,1-2 ..., be provided with (not shown) such as X address buffer, Y address impact damper, test mode circuit, generating circuit from reference voltage between the 1-9.
In Fig. 7, show memory bank 1-i (i=1,2 ..., 9) detailed frame circuit diagram, utilize the individual plates in 2 * 2 (=4) (or sub-piece) 21,22,23 and 24 to construct memory bank 1-i with mutually the same structure.
In addition, plate 21 and 22 and plate 23 and 24 between be provided with data line 25a, 25b, 25c and 25d, described data line also links to each other with pd with I/O contact pa, pb, pc respectively.Notice that I/O contact pa, pb, pc and pd are approximate to be positioned at each memory bank 1-1,1-2 ..., the center of 1-9.
Body controller 26 is carried out the X address that is used for main word line and sub word line driver and is controlled, is used for body selection BS and Y selection Y jY address control, be used to write Writing/Reading control (see figure 8), character group control and the I/O register controlled of amplifier and sensor amplifier.For example, body controller 26 receive have width * 36, * 18 or * 9 and the data of character group length b4 or b2, with activation signal A1, the A2, A3 and the A4 that write amplifier or sensor amplifier (see figure 8) that produces character group signal B1, B2, B3 or B4, control signal C1 and C2 and be used for activating plate 21,22,23 and 24.Note, produce control signal C1, be used for data width * 36 or * 18, and produce control signal C2, be used for data width * 9.
Plate 21 has four sub-data lines 211,212,213 and 214.Subdata line 211 optionally links to each other with data line 25a by selector switch 215 with 212.Subdata line 213 optionally links to each other with one of 25b with data line 25a by selector switch 216 with 214.Control selector switch 216 by selector switch 218, selector switch 218 switches to character group signal B3 and B4 with character group signal B1 and B2, or opposite.In this case, by character group signal B1 and B2 control selector switch 215, by be used for data width * 36 or * 18 character group signal B1 and B2 and the character group signal B3 and the B4 that are used for data width * 9 control selector switch 216, and controls selector switch 217 by control signal C1 (* 36 or * 18) and control signal C2 (* 9).
Plate 22 has four sub-data lines 221,222,223 and 224.Subdata line 221 optionally links to each other with data line 25c by selector switch 225 with 222, and subdata line 223 optionally links to each other with data line 25d by selector switch 226 with 224.In this case, by character group signal B1 and B2 control selector switch 225 and 226.
Plate 23 has four sub-data lines 231,232,233 and 234.Subdata line 231 optionally links to each other with data line 25a by selector switch 235 with 232, and subdata line 233 optionally links to each other with data line 25b by selector switch 236 with 234.In this case, by character group signal B3 and B4 control selector switch 235 and 236.
Plate 24 has four sub-data lines 241,242,243 and 244.Subdata line 241 optionally links to each other with data line 25c by selector switch 245 with 242, and subdata line 243 optionally links to each other with data line 25d by selector switch 246 with 244.In this case, by character group signal B3 and B4 control selector switch 245 and 246.
Notice that data line 25a, 25b, 25c and 25d only are used in the corresponding plate 1-i.Therefore, because I/O contact pa, pb, pc and the pd and the distance between each unit that link to each other with data line 25a, 25b, 25c and 25d are less, can expect the access of high speed.
In Fig. 8, detailed circuit diagram as one of plate of the plate 21 of for example Fig. 7, plate 21 comprises the main word line demoder 31 that is used to receive from the X address of body controller 26, to select to activate a main word line MWL of two sub word line drivers (SWD), each in described two sub word line drivers is used to select two sub-word line SWL 1And SWL 2(SWL 3And SWL 4).In addition, plate 21 comprises and is used to receive Y address signal Y jBit line select circuit 32, to select four bit line BL 1, BL 2, BL 3And BL 4As a result, be positioned at sub-word line SWL 1, SWL 2, SWL 3And SWL 4With bit line BL 1, BL 2, BL 3And BL 4Between four storage unit CL of point of crossing 1, CL 2, CL 3And CL 4Link to each other with 214 with subdata line 211,212,213 respectively.
In addition, will write respectively amplifier/sense amplifier circuit 33-1,33-2,33-3 and 33-4 be arranged on subdata line 211,212,213 and 214 and bit line select to activate described amplifier circuit by activation signal A1 between the circuit 32.Note, in writing pattern, activate and write amplifier circuit 33-1,33-2,33-3 and 33-4, in read mode, activate sense amplifier circuit 33-1,33-2,33-3 and 33-4.
Next, will with reference to figure 9,10A, 10B, 10C and 10D illustrate Fig. 7 and 8 semiconductor storage unit * 36b4 operation.
That is,, activate all memory bank 1-1 at arbitrary steps as shown in Figure 9,1-2 ..., 1-9.In other words, the memory bank that distributes and be activated equably.As a result, from carrying out each memory bank 1-1 of same operation, 1-2 ..., 1-9 access 4 bits, thereby access 36 bits (=9 * 4 bits).Below with one of memory bank of illustrative examples such as memory bank 1-1.
At first, shown in Figure 10 A, body controller 26 produces activation signal A1 and A2, with activating plate 21 and 22.In addition, body controller 26 produces character group signal B1.As a result, the selector switch 215,216 of plate 21 and 218 is selected left side subdata line 211 and 213, and selector switch 217 is selected data line 25b, and simultaneously, the selector switch 225 of plate 22 and 226 is selected left side subdata line 221 and 223.
Next, shown in Figure 10 B, body controller 26 produces activation signal A1 and A2, with activating plate 21 and 22.In addition, body controller 26 produces character group signal B2.As a result, the selector switch 215,216 of plate 21 and 218 is selected right side subdata line 212 and 214, and selector switch 217 is selected data line 25b, and simultaneously, the selector switch 225 of plate 22 and 226 is selected right side subdata line 222 and 224.
Next, shown in Figure 10 C, body controller 26 produces activation signal A3 and A4, with activating plate 23 and 24.In addition, body controller 26 produces character group signal B3.As a result, the selector switch 235 of plate 23 and 236 is selected left side subdata line 231 and 233, and simultaneously, the selector switch 245 of plate 24 and 246 is selected left side subdata line 241 and 243.
At last, shown in Figure 10 D, body controller 26 produces activation signal A3 and A4, with activating plate 23 and 24.In addition, body controller 26 produces character group signal B4.As a result, the selector switch 235 of plate 23 and 236 is selected right side subdata line 232 and 234, and simultaneously, the selector switch 245 of plate 24 and 246 is selected left side subdata line 242 and 244.
Thus, in * 36b2 operation, access all plates 21,22,23 and 24.
Note, only illustrate * the 36b2 operation with reference to figure 10A and 10B.
Next, with reference diagram will with reference to Figure 11,12A, 12B, 12C and 12D illustrate Fig. 7 and 8 semiconductor storage unit * 18b4 operation.
That is,, activate all memory bank 1-1 at arbitrary steps as shown in figure 11,1-2 ..., 1-9.In other words, the memory bank that distributes and be activated equably.As a result, from carrying out each memory bank 1-1 of same operation, 1-2 ..., 1-9 access 2 bits, thereby access 18 bits (=9 * 2 bits).Below with one of memory bank of illustrative examples such as memory bank 1-1.
At first, shown in Figure 12 A, body controller 26 produces activation signal A1, with activating plate 21.In addition, body controller 26 produces character group signal B1.As a result, the selector switch 215,216 of plate 21 and 218 is selected left side subdata line 211 and 213, and selector switch 217 is selected data line 25b.
Next, shown in Figure 12 B, body controller 26 produces activation signal A1, with activating plate 21.In addition, body controller 26 produces character group signal B2.As a result, the selector switch 215,216 of plate 21 and 218 is selected right side subdata line 212 and 214, and selector switch 217 is selected data line 25b.
Next, shown in Figure 12 C, body controller 26 produces activation signal A3, with activating plate 23.In addition, body controller 26 produces character group signal B3.As a result, the selector switch 235 of plate 23 and 236 is selected left side subdata line 231 and 233.
At last, shown in Figure 12 D, body controller 26 produces activation signal A3, with activating plate 23.In addition, body controller 26 produces character group signal B4.As a result, the selector switch 235 of plate 23 and 236 is selected right side subdata line 232 and 234.
Thus, in * 18b2 operation, an access two plates, promptly plate 21,22,23 and 24 half.
Note, only illustrate * the 18b2 operation with reference to figure 12A and 12B.
Next, with reference diagram will with reference to Figure 13,14A, 14B, 14C and 14D illustrate Fig. 7 and 8 semiconductor storage unit * 9b4 operation.
That is,, activate all memory bank 1-1 at arbitrary steps as shown in figure 13,1-2 ..., 1-9.In other words, the memory bank that distributes and be activated equably.As a result, from carrying out each memory bank 1-1 of same operation, 1-2 ..., 1-9 access 1 bit, thereby access 9 bits (=9 * 1 bits).Below with one of memory bank of illustrative examples such as memory bank 1-1.
At first, shown in Figure 14 A, body controller 26 produces activation signal A1, with activating plate 21.In addition, body controller 26 produces character group signal B1.As a result, the selector switch 215 of plate 21 is selected left side subdata line 211.In this case, by selector switch 218 deactivation selector switchs 216, thus chooser data line 213 and 214 not.
Next, as shown in Figure 14B, body controller 26 produces activation signal A1, with activating plate 21.In addition, body controller 26 produces character group signal B2.As a result, the selector switch 215 of plate 21 is selected right side subdata line 212.In this case, by selector switch 218 deactivation selector switchs 216, thus chooser data line 213 and 214 not.
Next, shown in Figure 14 C, body controller 26 produces activation signal A1, with activating plate 21.In addition, body controller 26 produces character group signal B3.As a result, the selector switch 216 of plate 21 is selected left side subdata line 211.In this case, by selector switch 218 deactivation selector switchs 216, thus chooser data line 213 and 214 not.
At last, shown in Figure 14 D, body controller 26 produces activation signal A1, with activating plate 21.In addition, body controller 26 produces character group signal B4.As a result, the selector switch 216 of plate 21 is selected right side subdata line 214.In this case, by selector switch 218 deactivation selector switchs 216, thus chooser data line 213 and 214 not.
Thus, in * 9b4 operation, an access plate, promptly plate 21,22,23 and 24 1/4th.
Note, only illustrate * the 9b2 operation with reference to figure 14A and 14B.
The semiconductor storage unit of Fig. 6 is installed in ball grid array (BGA) the type encapsulation shown in Figure 15 A.
In Figure 15 A, will the semiconductor memory chips identical with the semiconductor storage unit of Fig. 6 facing down pastes on the insertion substrate 1502 that is supported by polyimide etc.In addition, in the gap between semiconductor memory chips 1501 and insertion substrate 1502 sealant of being made by epoxy resin 1503 is set, described sealant 1503 has covered semiconductor memory chips 1501.
Shown in Figure 15 B, except I/O contact pa, pb, pc and pd that heart place therein is provided with along straight line, each memory bank 1-1 of semiconductor memory chips 1501,1-2 ..., 1-9 also has control contact pX.
In addition, as Figure 15 C from shown in, be divided into respectively memory bank 1-1 with Figure 15 B with inserting substrate 1503,1-2 ..., the corresponding spheric region 15-1 of 1-9,15-2 ... 15-9.At each spheric region 15-1,15-2 ... 15-9, be provided with respectively with the corresponding soldered ball Ba of I/O contact pa, pb, pc and pd, Bb, Bc and the Bd of Figure 15 B and with the corresponding soldered ball BB of control contact pX.
Thus, can make the distance between I/O contact pa, pb, pc and pd soldered ball Ba, Bb, Bc and the Bd corresponding with it minimum, this has further realized access more at a high speed.
In the above-described embodiments, although be provided with 3 row, 3 row memory bank 1-1,1-2 ..., 1-9 can be provided with 3 mRow, 3 mRow (m=2,3 ...) memory bank, for example 9 row, 9 row memory banks and 27 row, 27 row memory banks.In addition, although each individuality has been equipped with 2 row, 2 strakes, each individuality can be equipped with that 2n is capable, the 2n row (n=2,3 ...) and plate, for example 4 row, 4 strakes and 8 row, 8 strakes.
In addition, memory bank 1-1,1-2 ..., the scale of 1-9 can differ from one another, and plate 21,22,23 and 24 scale can differ from one another.
In addition, can increase character group length.For example, if character group length is 8, the plate 1-i of Fig. 7 is revised as shown in Figure 6 plate 1-i '.That is, body controller 26 produces additional character group signal B5, B6, B7 and B8.In addition, can add subdata line 211 ', 212 ', 213 ' and 214 ' respectively to the plate 21,22,23 and 24 of Fig. 7, subdata line 221 ', 222 ', 223 ' and 224 ', subdata line 231 ', 232 ', 233 ' and 234 ', subdata line 241 ', 242 ', 243 ' and 244 '.In addition, utilize selector switch 215 ', 216 ', 225 ' and 226 ' to replace selector switch 215,216,225 and 226 respectively, control described selector switch 215 ', 216 ', 225 ' and 226 ' by character group signal B1, B2, B3 and B4, and utilize selector switch 235 ', 236 ', 245 ' and 246 ' to replace selector switch 235,236,245 and 246 respectively, control described selector switch 235 ', 236 ', 245 ' and 246 ' by character group signal B5, B6, B7 and B8.In addition, selector switch 218 switches character group signal B1, B2, B3 and B4 and character group signal B5, B6, B7 and B8.
In addition, can increase data width.For example, if data width is 54, the plate 1-i of Fig. 7 is revised as shown in Figure 7 plate 1-i ".That is, additionally, body controller 26 receives the X54 signal, to produce character group signal A2 ' and A4 '.In addition, added data line 25e and the 25f that links to each other with pf with I/O contact pe.In addition, added and comprised subdata line 221 ', 222 ', 223 ' and 224 ' dish 22 ', and with its selector switch 225 ' and 226 ' by controlling by character group signal B1 and B2, link to each other with 25f with data line 25e, and added and comprised subdata line 241 ', 242 ', 243 ' and 244 ' dish 24 ', and, link to each other with 25f with data line 25e with its selector switch 245 ' and 246 ' by controlling by character group signal B3 and B4.Note, come activating plate 22 ' and 24 ' by character group signal A2 ' and A4 ' respectively.
As mentioned above,, can reduce power consumption, and increase access speed according to the present invention.

Claims (13)

1. semiconductor equipment that is used for many bits I/O function, described semiconductor equipment comprises semiconductor memory chips, described semiconductor memory chips comprise 3 mRow, 3 mRow (m=1,2 ...) and memory bank, each memory bank has a plurality of input/output terminals,
Described memory bank is suitable for carrying out identical operations, so that from the bit of the described input/output terminal access predetermined number of described each memory bank.
2. semiconductor equipment according to claim 1 is characterized in that the approximate center that is positioned at described each memory bank of described input/output terminal.
3. semiconductor equipment according to claim 1 is characterized in that also comprising: be divided into the insertion substrate in a plurality of zones, described each zone is corresponding with one of described memory bank,
At a plurality of outside terminals that described each zone is provided with, described each outside terminal links to each other with the described input/output terminal of one of described memory bank.
4. semiconductor equipment according to claim 1 is characterized in that described each memory bank comprises:
A plurality of plates, each plate are suitable for being activated independently; And
A plurality of data lines, each data line links to each other with one of described input/output terminal, and optionally links to each other with described plate.
5. semiconductor equipment according to claim 4, the number that it is characterized in that described plate be 2n * 2n (n=1,2 ...).
6. semiconductor equipment according to claim 4, it is characterized in that described each plate comprises: optionally a plurality of subdata lines that link to each other with described data line are right.
7. semiconductor equipment according to claim 4 is characterized in that, in described each memory bank, can set up first state that wherein activates all described plates, activates second state of half described plate and activate the third state of 1/4th described plates.
8. semiconductor storage unit that is used for many bits I/O function comprises:
3 row, 3 row memory banks;
Many group input/output terminals, each group terminal is set in one of described memory bank; And
The multi-group data line, each group data line is set in one of described memory bank, described each data line links to each other with one of described input/output terminal, described each organize data line and only be arranged in and be used for one of described memory bank.
9. semiconductor storage unit according to claim 8 is characterized in that described each memory bank comprises a plurality of plates, and each plate is suitable for being activated independently.
10. semiconductor storage unit according to claim 8 is characterized in that described each memory bank also comprises: selector circuit is suitable for described plate is linked to each other with described data line.
11. semiconductor storage unit according to claim 8 is characterized in that described input/output terminal links to each other with the outside terminal that inserts substrate.
12. a semiconductor storage unit that is used for many bits I/O function comprises:
A plurality of memory banks;
A plurality of input/output terminals; And
A plurality of data lines, each data line are suitable for described input/output terminal is linked to each other with one of described memory bank.
13. a semiconductor storage unit that is used for many bits I/O function comprises: 3 row, 3 row memory banks,
The data that comprise at least one check bit, described data are distributed in the described memory bank.
CNA200510073763XA 2004-05-24 2005-05-24 Memory device with memory matrix used for multi-bit inputting/outputting Pending CN1707695A (en)

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