CN1705087A

CN1705087A - Method for forming oxide layer in ONO structure

Info

Publication number: CN1705087A
Application number: CN 200410042687
Authority: CN
Inventors: 王致皓; 陈昕辉; 黄仲仁; 陈仲慕; 刘光文; 邱家荣
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2004-05-31
Filing date: 2004-05-31
Publication date: 2005-12-07
Anticipated expiration: 2024-05-31
Also published as: CN100386853C

Abstract

A method for forming silicon oxide/silicon nitride/silicon oxide (ONO) structure, which contains forming the first silicon oxide and silicon nitride layer covering on the substrate with memory component area and logic component area, patterning the first silicon oxide and silicon nitride layer to define the location of bottom oxide and silicon nitride partially completing the stack structure to expose the substrate of logic component area, making quick heat tempering under free radical oxidant, forming second silicon oxide layer on exposed surface of silicon nitride layer and forming grid oxide layer on substrate, depositing conductive layer on completed ONO stack structure and grid oxide layer. Said invention can prevent the silicon nitride to be exposed in followed process and increase the grid coupling ratio.

Description

Method for forming oxide layer in ONO structure

Technical Field

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device having a silicon oxide/silicon nitride/silicon oxide (O/N/O) structure and a method for forming an oxide therein.

Background

In the conventional process, a device having an ONO structure is formed by covering a tunneling layer, a silicon nitride layer and a top oxide layer on a substrate. An etching process is then performed to pattern the ONO structure.

The top oxide layer in the ONO structure may be formed by oxidizing silicon nitride. However, the conventional silicon nitride oxidation process is time consuming and has a high thermal budget. For example, in some conventional processes, silicon nitride is placed in a furnace tube and maintained at 1000 degrees celsius for 60 minutes to perform a wet oxidation process on the silicon nitride.

In addition, conventional processes typically follow the oxidation step with a cleaning process. During the cleaning process, the top oxide layer may be etched and even corners of the silicon nitride layer may be exposed, thereby causing leakage current from the silicon nitride layer to the polysilicon gate formed thereafter. Therefore, the charge stored in the silicon nitride layer is lost, which causes electrical problems in the device.

To avoid the loss of the top oxide layer during the cleaning process, it is known to deposit the tunneling layer and the silicon nitride layer, pattern them, and then grow the top oxide layer on the silicon nitride layer by wet oxidation. However, the wet oxidation method has a relatively high oxidation selectivity for the substrate and the silicon nitride layer, and thus the oxidation rate of the substrate is much greater than that of the silicon nitride layer. For example, if a top oxide layer with a thickness of 100 angstroms is to be formed by wet oxidation, an oxide layer with a thickness of 1000 angstroms will be formed on the substrate. Therefore, if the top oxide layer is formed by a conventional wet oxidation process, the thick oxide layer on the substrate needs to be removed after the top oxide layer is formed. This increases the process complexity and results in an uneven substrate surface.

One method of forming an oxide layer on a substrate is an In Situ Steam Generation (ISSG) process. The ISSG process heats a substrate (typically a semiconductor wafer) to a sufficiently high temperature to catalyze the reaction between an oxygen-containing gas and a hydrogen-containing gas to form oxygen radicals. The oxygen radicals are effective to oxidize silicon or silicon nitride on the substrate.

U.S. patent No. 6184155 describes a two-step ISSG process suitable for forming an ultra-thin silicon dioxide gate insulation layer in MOSFETs having narrow channel lengths. After a first steam oxidation and in-situ tempering around the nitrogen oxide, a second steam oxidation and in-situ tempering around the nitrogen oxide are carried out. The two-step process forms a silicon dioxide layer having a thickness of between about 10 a and about 20 a that provides a gate insulation layer with reduced leakage current in a preparation or operational mode of the MOSFET device compared to a silicon dioxide layer formed by a non-ISSG process using the two-step process.

One process described in U.S. patent No. 6171911 is to sequentially and selectively form two different thicknesses of thermally grown silicon oxide in MOSFET devices, with field isolation regions defining the areas on the wafer. The conventional method for forming the gate oxide layer is to form a thick oxide layer on all exposed regions of the wafer, then dispose a mask on the wafer, and pattern the mask to expose the regions where the thin oxide layer is to be formed. Then, the thick oxide layer in the exposed region of the mask layer is removed by using hydrofluoric acid through a wet etching method. Then, the mask is stripped off, and the wafer is cleaned by using the aqueous solution without hydrofluoric acid. Then, the wafer is placed in an environment containing hydrogen and nitrogen, and then the native oxide is removed by low-pressure rapid thermal annealing and the silicon surface is passivated, so that the thickness of the residual oxide layer is reduced to about 4 angstroms. Wherein the temperature in the thermal tempering process is about 600 ℃ to 1050 ℃. The method can improve the uniformity of the thickness of the oxide layer and the oxidation quality thereof, and the rest oxide film can become firmer silicon oxide after the annealing process.

Disclosure of Invention

According to the present invention, after the tunneling layer and the silicon nitride layer are formed and patterned, an in-situ steam generation (ISSG) process is performed in an environment containing oxygen radicals to simultaneously form a top oxide layer, a buried drain oxide layer and a gate oxide layer in the MOS region. Exposing the exposed patterned silicon nitride to oxygen radicals may oxidize the silicon nitride in less time, for example, about 1 minute. The time consumed by the process can therefore be much shorter and the thermal budget can be reduced. In addition, because the top surface and the side wall of the silicon nitride layer are covered with the top oxide layer, the silicon nitride can be prevented from being exposed in the subsequent cleaning process. And the contact area of the polysilicon grid and the top oxide layer is increased, so that the coupling ratio of the grid is improved.

In one broad aspect, the present invention features a method of forming an oxide layer in a semiconductor having an ONO structure. The method deposits a tunneling oxide layer and a silicon nitride layer on a substrate and patterns the tunneling oxide layer and the silicon nitride layer by using a photolithography process. Then, a rapid thermal oxidation process is performed in an environment containing oxygen radicals to form a top oxide layer on the top surface and sidewalls of the patterned silicon nitride layer, and simultaneously form a buried diffusion region (source/drain) in the substrate, and a gate oxide layer in the MOS region of the substrate.

By oxygen free radical is meant herein an oxygen containing species containing one or more pairs of unpaired electrons and which is present independently. Whereas unpaired electrons refer to the presence of only one electron in the orbital of an atom or molecule. Oxygen radicals are a strong oxidizing agent that rapidly oxidize silicon nitride. Since the difference between the oxidation rates of the substrate and the silicon nitride layer is small, the oxidation selectivity of the substrate and the silicon nitride layer is also low.

According to the present invention, the top oxide layer, the buried drain oxide layer and the gate oxide layer of the MOS can be formed simultaneously without being divided into a plurality of steps. Therefore, the invention can simplify the process,shorten the process time and reduce the thermal budget of the process.

In another broad aspect, the present invention provides a method of forming a semiconductor device having a silicon oxide/silicon nitride/silicon oxide (O/N/O) structure. The method comprises forming a first silicon oxide layer and a silicon nitride layer on a substrate, and patterning the first silicon oxide layer and the silicon nitride layer. And performing a rapid thermal annealing process in the presence of a free radical oxidizing agent to simultaneously form a second silicon oxide layer on the exposed surface of the silicon nitride and a gate oxide layer on the substrate.

In another broad aspect, the present invention features a method of fabricating a memory device having a silicon oxide/silicon nitride/silicon oxide (O/N/O) structure. The method comprises forming a first silicon oxide layer and a silicon nitride layer on a substrate, wherein the substrate has a memory region and a MOS region. Then, the first silicon oxide layer and the silicon nitride layer are patterned to form the patterned first silicon oxide layer and the patterned silicon nitride layer on the memory cell region. Then, source/drain electrodes are formed on the substrate between the patterned first silicon oxide layers, and then rapid thermal annealing is performed in an environment in which a radical-based oxidizing agent is present, so as to simultaneously form a second silicon oxide layer on the exposed surface of the patterned silicon nitride, form a buried drain oxide layer on the buried source/drain electrodes, and form a gate oxide layer on the MOS region.

In certain embodiments of the present invention, the free radical oxidizing agent comprises an oxygen radical. In a specific embodiment, the oxygen radical is O^-。

In some embodiments of the present invention, the second silicon dioxide layer is formed to have a thickness ratio to the gate oxide layer of about 0.6: 1 to about 0.8: 1. In some embodiments, the device is a memory device having a buried source/drain and a buried drain oxide layer formed to a thickness substantially greater than a thickness of the gate oxide layer.

In certain embodiments of the present invention, the rapid thermal tempering process is an in situ steam generation process. In this process, the temperature of the substrate (e.g., a semiconductor wafer) is heated to a suitable temperature range, and an oxygen-containing gas and a hydrogen-containing gas are introduced for a suitable time while maintaining flow rates within a suitable range to complete the oxidation process. In some embodiments, the oxygen-containing gas and the hydrogen-containing gas are introduced simultaneously, and the ratio of the oxygen-containing gas to the hydrogen-containing gas falls within a suitable range.

In certain embodiments of the invention, the hydrogen-containing gas is hydrogen (H)₂) The oxygen-containing gas is oxygen (O)₂). If a carrier gas is used in the process, the carrier gas is nitrogen (N)₂). Wherein the flow rates of the hydrogen and oxygen are proportional, and the flow rate ratio (H) is₂/H₂+O₂) Between about O.1% and about 40%, preferably between about 5% and about 33%. And in particular embodiments, the hydrogen to oxygen flow rate ratio (H)₂∶O₂) About 1: 19 or 1: 3 or 1: 12. The temperature of the wafer is maintained between about 700 degrees celsius and 1300 degrees celsius, preferably between about 900 degrees celsius and 1150 degrees celsius. The time that the wafer is exposed to the mixed gas depends on the thickness of the oxide layer to be formed, the gas flow rate and the temperature. The exposure time is 1 to 10 seconds for short, 100 to 1000 seconds for long, or even longer. The exposuretime of the wafer to the mixed gas is typically 10 seconds, and in certain embodiments 30 seconds, in some embodiments 120 seconds, in other embodiments 300 seconds, and in still other embodiments 500 seconds. In certain embodiments of the present invention, the temperature used in the process is 850 degrees Celsius, 900 degrees Celsius, 950 degrees Celsius, or 1000 degrees Celsius. Flow rate ratio (H) of oxygen to hydrogen₂/H₂+O₂) About 5%, 25%, or 33% (e.g., 6slm for hydrogen and 12slm for oxygen), the time required for the process is about 30 seconds, 60 seconds, 90 seconds, or 120 seconds.

In another broad aspect, the present invention features a semiconductor device having a silicon oxide/silicon nitride/silicon oxide structure. The element comprises a first silicon oxide layer covering the substrate, a silicon nitride layer covering part of the first silicon oxide layer, a second silicon oxide layer completely covering the silicon nitride layer and contacting with the first silicon oxide layer, and a grid conductor layer covering the second silicon oxide layer.

In another broad aspect, the invention features a memory cell of a non-volatile memory having a silicon oxide/silicon nitride/silicon oxide structure. The memory unit comprises a buried source electrode and a buried drain electrode which are positioned in a substrate, a buried drain electrode/source electrode oxidation layer which covers on the buried drain electrode/source electrode, a first silicon oxide layer which covers on the substrate between the buried drain electrode and the buried source electrode and on part of the buried drain electrode/source electrode oxidation layer, a silicon nitride layer which covers on part of the first silicon oxide layer, a second silicon oxide layer which completely covers the silicon nitride layer and is contacted with the first silicon oxide layer and a grid electrode conductor layer whichcovers on the second silicon oxide layer.

In another broad aspect, the present invention features a memory cell having a silicon oxide/silicon nitride/silicon oxide structure in a non-volatile memory, including buried source and drain regions in a substrate, a buried drain/source oxide layer overlying the buried drain/source regions, a first silicon oxide layer overlying the substrate between the drain and source regions and a portion of the buried drain/source oxide layer, a silicon nitride layer overlying a portion of the first silicon oxide layer, a second silicon oxide layer overlying the silicon nitride layer and contacting the first silicon oxide layer, and a gate conductor layer overlying the second silicon oxide layer.

In some embodiments of the present invention, the thickness ratio of the oxide layer on silicon nitride (SiN) to the oxide layer on silicon (Si) (SiN: Si) is about 0.6: l to about 0.8: 1, and preferably about 0.68: 1 to about 0.78: 1.

In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a flow chart of the steps of a conventional oxidation process.

Fig. 2A to 2G are schematic cross-sectional views of each step in fig. 1.

FIG. 3 is a flow chart of the steps of an oxidation process according to one embodiment of the present invention.

Fig. 4A-4G are schematic cross-sectional views of each oxidation process step in fig. 3.

FIG. 5 is a cross-sectional view of an ONO structure formed according to a conventional process.

FIG.6 is a schematic cross-sectional view of an ONO structure formed by a process in accordance with the present invention.

100: known processes

102 to 116, 302 to 314: process step

202. 402, 502, 602: substrate

204. 404: isolation structure

206. 406: first region

208. 408: second region

210. 410: tunneling oxide layer

212. 213, 226, 412, 426, 427, 526, 626: silicon nitride layer

214. 228, 428, 528, 628: top oxide layer

220. 222, 420, 422, 500, 600: ONO structure

224. 424, 524, 624: bottom oxide layer

230. 430: source/drain region

232. 233, 432, 532, 632: embedded diffusion region (source/drain)

234. 434, 534, 634: buried source/drain oxide layer

236. 436: grid oxide layer

238. 438, 528, 638: polycrystalline silicon layer

300: the process of the invention

421. 423, 522, 622: ONO stack structure

527. 627: edge of silicon nitride layer

529: edge of top oxide layer

Detailed Description

The present invention will be described in detail below with reference to the following description of each embodiment of the present invention. Some of the features of the present invention are shown schematically, and other features and structures associated therewith, not to scale. Although elements of the embodiments of the invention may be readily identified in all of the figures as the same components as in other figures, the description does not refer to all of the same elements as a reference numeral in each figure for clarity.

In accordance with embodiments of the present invention, oxygen radicals are formed by reacting hydrogen and oxygen on a heated wafer surface under ISSG conditions. The in-situ steam generation process is a low pressure process in which oxygen and hydrogen are mixed in a certain proportion and then introduced directly into a process chamber without a prior combustion process. The wafer is heated and then acts as an ignition source, so that the reaction between the hydrogen and oxygen occurs near the wafer surface (in situ). Generally, under the conditions of the ISSG process, oxygen radicals are generated mainly by the following reaction formula.

In the ISSG oxidation process, the presence of hydrogen gas accelerates the dissociation of oxygen molecules to form reactive oxygen atoms. In accordance with the present invention, the rate of oxide formation on silicon nitride (i.e., the thickness of oxide formation relative to the thickness of silicon nitride loss) in an ISSG process manifests itself in the presence of oxygen atoms (oxygen radical O)^-) The concentration is strongly related to other kinds of molecules orThe atoms are not related. Oxygen radical O^-The concentration of (d) is not dependent on the volume of the reactant gas but rather on the pressure, temperature and relative amount of hydrogen in the chamber.

The main function of the pressure and temperature in the chamber is to cause collisions between molecules, the pressure orThe primary function of the flow rate is to recombine the molecules. During the collision and recombination of molecules, the equilibrium of free radical generation allows the oxygen radicals to reach the highest concentration. Therefore, the ISSG process is dependent on the process pressure, gas flow rate and temperature used in the chamber, all within a specified range. Thus, in some embodiments of the present invention, the following parameters are used to achieve better performance: a temperature in a range from about 800 degrees Celsius to about 1000 degrees Celsius, a pressure in a range from about 1 Torr to about 20 Torr, and H₂+O₂Is approximately in the range of 1slm to 40 slm. And H₂/H₂+O₂Is approximately in the range of 0.1% to 40%.

In some embodiments of the invention, a carrier gas is flowed through the chamber along with a mixture of hydrogen and oxygen to improve pressure uniformity. Wherein the carrier gas is for example nitrogen. However, since the carrier gas is not an essential element in the in situ generation process of oxygen radicals, the flow rate may be between 0slm (if no carrier gas is used) and 50 slm.

In known processes, the ratio of hydrogen to oxygen used is relatively high, for example 1/67: 1, and the reaction temperature is, for example, 1000 degrees celsius, the ratio of the growth rate of oxide on silicon nitride to that on silicon (SiN/Si) being, for example, about 0.26. According to the method of the present invention, the ratio of the formation rate of the oxide on the silicon nitride to the formation rate of the oxide on the silicon can be higher, and the oxide can be formed on the surfaces of the silicon nitride and the silicon simultaneously.

The flow chart of fig. 1 illustrates a conventional process 100 for forming oxide for a device having an ONO structure. Fig. 2A to 2G are schematic cross-sectional views of structures formed at different stages in a conventional process. Referring to fig. 1 and 2A, in step 102 of the conventional process 100, an isolation structure 204 is formed in a substrate 202 to define a first region 206 and a second region 208. The substrate 202 is, for example, a silicon wafer, and the isolation structure 204 is, for example, a trench isolation structure. The first region 206 is used to form memory cells, and the second region 208 is used to form logic devices. Next, in step 104, a tunnel oxide layer 210 is formed over the first region 206 and the second region 208, as shown in fig. 2B. In step 106, a silicon nitride layer 212 is deposited over the tunnel oxide layer 210, as shown in FIG. 2C. Then, in step 108, an oxidation process is performed on the silicon nitride layer 212 to form a top oxide layer 214. Since the top of the silicon nitride layer 212 is partially consumed during the oxidation process, the thickness of the remaining silicon nitride layer 213 is relatively thin, as shown in fig. 2D. At this time, the formation of the ONO film is completed. In step 110, a patterning process is performed by using a mask (not shown) to define an ONO structure 220 and an ONO structure 222 on the first region 206 of the substrate 202 and expose the surface of the substrate 202 in the second region 208. Each of the

ONO structures

220 and 222 is formed as an ONO stack structure having a bottom oxide layer 224, a silicon nitride layer 226, and a top oxide layer 228, respectively, from the substrate 202. The ONO stack structure is separated by source/drain regions 230 in this embodiment. In step 112, an ion implantation process is performed to form the buried diffusion region 232 and form a buried source/drain, as shown in fig.2E. An oxidation process is then performed to create a device gate oxide layer 236 and source/drain oxide layers 234 on the second region 208 in step 114. Since part of the buried diffusion region 232 is lost during the oxidation process, a thinner buried diffusion region 233 is generated, as shown in fig. 2F. Under the conditions used here, the increase in the thickness of the top oxide layer in the ONO structure is very small, corresponding to a meaningless quantity, for example a few angstroms. In step 116, a polysilicon layer 238 is deposited overlying gate oxide layer 236,

ONO structures

220 and 222, and buried source/drain oxide layer 234, as shown in fig. 2G.

It should be noted, however, that the removal of the oxide layer 210 overlying the second region makes the overall process more complicated and creates an uneven surface on the second region 208.

FIG. 3 is a flow chart of the steps of an oxidation process according to one embodiment of the present invention. Fig. 4A-4G are schematic cross-sectional views of structures formed at different stages of the oxidation process 300 of the present invention. Referring to fig. 3 and 4A, in step 302 of the process 300, an isolation structure 404 is formed in the substrate 402 to define a first region 406 and a second region 408. The first region 406 is used to form a memory cell; while the second region 408 is used to form logic device isolation structures. The substrate 402 is, for example, a silicon wafer, and the isolation structure is, for example, a trench isolation structure 404. In step 304, a tunnel oxide layer 410 is formed to cover the first region 406 and the second region 408, as shown in FIG. 4B. In step 306, a silicon nitride layer 412 is deposited over the tunnel oxide layer 410, as shown in FIG. 4C. These steps can be performed by conventional techniques. Referring to fig. 4C, the result of these steps is to provide a substrate 402 having regions defined by the isolation structures 404, and a tunnel oxide layer 410 is formed over the regions, and a silicon nitride layer 412 having an exposed surface is formed over the tunnel oxide layer 410. In step 308, a patterning process is performed using a mask (not shown) to define a bottom oxide layer portion 424 and a silicon nitride layer portion 426 of the ONO structure to be formed on the first region 406 of the substrate 402, as shown by

reference numerals

420 and 422, and to expose the surface of the substrate 402 in the second region 408, as shown in fig. 4D. At this point, neither the gate oxide of the logic device in the second region 408 nor the top oxide of the ONO structure is formed. In the present embodiment, a source/drain region 430 is formed between the defined oxide and nitride partially completed ONO stack structure. In step 310, an ion implantation process is performed to form a buried diffusion region in the source/drain region 430 of the substrate 402 to form a buried source/drain 432, as shown in fig. 4E.

Then, in step 312, a Rapid Thermal Oxidation (RTO) process is performed in the presence of an oxygen radical to simultaneously form the top oxide layer 428, the buried drain/source oxide layer 434, and the gate oxide layer 436, as shown in fig. 4F. And a portion of the silicon nitride layer 426 is consumed while the top oxide layer 428 is grown, leaving a thinner silicon nitride layer 427. Each of

ONO structures

421 and 423 formed by the above processes forms an ONO stack structure, and is followed by a bottom oxide layer 424, a silicon nitride layer 427, and a top oxide layer 428 from the substrate 402.

Thereafter, in step 314, a polysilicon layer 438 is deposited overlying gate oxide 436,

ONO stack structures

421 and 423, and buried source/drain oxide 434, as shown in fig. 4G.

Referring to fig. 5, a cross-sectional view of an ONO structure 500 formed ina memory cell region according to a conventional process is shown. ONO structure 500 is formed on substrate 502 and includes an ONO stack 522, wherein ONO stack 522 is formed by sequentially overlying substrate 502 with a bottom oxide layer 524, a silicon nitride layer 526 and a top oxide layer 528. Buried diffusion regions (source/drain regions) 532 are formed in substrate 502 adjacent to ONO stack structure 522, for example, by ion implantation. The source/drain oxide layer 534 is formed by oxidizing the buried diffusion 532. A polysilicon layer 538 overlies top oxide layer 528 of ONO stack structure 522 and source/drain oxide layer 534 adjacent to ONO stack structure 522. It is noted that after top oxide layer 528 of ONO stack 522 is formed using a conventional wet oxidation process, a cleaning process is performed to etch top oxide layer 528 and expose corners or edges of silicon nitride layer 526. Referring again to fig. 5, in ONO stack 522 formed by conventional methods, edge 529 of top oxide layer 538 is etched to expose edge 527 of the silicon nitride layer. When a polysilicon layer 538 is deposited overlying the stack, the exposed edge 527 of the silicon nitride layer contacts the overlying polysilicon layer 538, creating a leakage current path from the silicon nitride layer 526 to the polysilicon layer 528, and thus reducing the performance of the ONO structure 500.

The invention can avoid the problem of leakage current. Figure 6 is a cross-sectional schematic view of an ONO structure 600 formed in accordance with the present invention. Referring to fig. 6, an ONO structure 600 of the present invention is formed on a substrate 602, and includes an ONO stack structure 622, wherein the ONO stack structure 622 is composed of a bottom oxide layer 624, a silicon nitride layer 626 and a top oxide layer 628 sequentially disposed on the substrate 602. Buried diffusion regions (source/drain regions) 632 are formed in the substrate 602 adjacent to the ONO stack structure 622, for example, by ion implantation. The source/drain oxide layer 634 is formed by oxidizing the buried diffusion region 632 in an RTO process with oxygen radicals. And the top oxide layer 628 is also formed during this process concurrently with the source/drain oxide layer 634 as described above with respect to fig. 3 and 4D-4F. And a polysilicon layer 638 overlies the top oxide layer 628 of the ONO stack structure 622 and the source/drain oxide layer 634 adjacent the ONO stack structure 622. In accordance with the present invention, the top oxide layer 628 is formed by oxidation of the exposed surface of the silicon nitride layer 626 after the silicon nitride layer 626 and the bottom oxide layer 624 are patterned. The top oxide layer 628 formed by this method may completely cover the edges and corners of the silicon nitride layer 626, and the top oxide layer 628 surrounds the edges of the silicon nitride layer 626 and contacts the adjacent portions of the source/drain oxide layer 634. Thus, the silicon nitride layer 626 may be completely isolated from a polysilicon layer 638 that is subsequently formed thereon, thereby improving the performance and reliability of the ONO structure 600.

Example one

In this example, a patterned silicon nitride (SiN) and silicon (Si) surface is formed on a wafer substrate, and the wafer is placed in an in-situ steam generation furnace. The wafer is then heated to about 950 degrees celsius in an ISSG chamber and exposed to hydrogen, oxygen, and nitrogen as a carrier gas for about 300 seconds to form an oxide layer on the surface of the silicon and silicon nitride. Wherein the flow rate of hydrogen in the chamber of the ISSG process is 2slm and the flow rate of oxygen is 8 slm. While the oxide layer formed on the silicon surface is approximately 158 angstroms thick and the oxide layer formed on the silicon nitride surface is approximately 128 angstroms thick.

Example two

This example will compare the difference between the actual value of the rate of oxide formation on silicon nitride (SiN) using an ISSG process and the theoretical value derived from the equation.

The theoretical rate can be derived from the following equation:

Si₃N_4-：(28.086×3+14×4g/mole)/(3.1g/cm³)＝45.25cm³/mole

SiO_2-：(28+16×2g/mole)/(2.21g/cm³)＝27.18cm³/mole

(27.18×3)/45.25＝1.8

if the oxide growth thickness in the experimental data of the ISSG process is plotted against the depletion thickness of the silicon nitride layer (SiNGen), the resulting slope is 1.6301. The formation of a nitrogen-combined oxide (oxynitride) in a thin layer at the interface of the top oxide layer and the nitride layer may be used to account for the difference between the theoretical value rate and the measured experimental value rate. And due to the presence of the nitrogen combined with the oxide, the precise location of the oxide-nitride interface, especially the interface of the top oxide film and the nitride layer in the ONO stack structure, is difficult to determine.

Example three

This example compares the rate of oxide formation on silicon nitride compounds (dichlorosilane, DCS) in an ISSG process at three different temperatures. These three temperatures are 850 degrees celsius, 900 degrees celsius, and 950 degrees celsius, respectively. The wafers at each temperature were exposed to hydrogen and oxygen gases at a hydrogen to oxygen flow ratio (H)₂/H₂+O₂) About 33% (H)₂Flow rate of 6slm, and O₂Flow rate 12 slm). And the time intervals for measuring the thickness of the oxide layer are about 30 seconds, 60 seconds, 90 seconds, and 120 seconds.

The growth rate ratio (SiN/Si) of the oxide layer on the silicon nitride and silicon is in a range of approximately 0.68: 1 to 0.75: 1 in a process at a temperature of 850 degrees Celsius. The growth rate ratio (SiN/Si) of the oxide layer on the silicon nitride and silicon is in a range of approximately 0.69: 1 to 0.75: 1 in a 900 degree Celsius process. In a 950 degree celsius process, the growth rate ratio (SiN/Si) of the oxide layer on the silicon nitride and silicon is in a range of approximately 0.72: 1 to 0.78: 1.

The formation of a thin oxide film on a silicon nitride layer is known from the linear growth law (linear growth law). In contrast, the formation of the oxide layer in the ISSG process is apparently achieved by controlling its diffusion. When the square of the thickness of the oxide layer is linearly proportional to the oxidation time, it follows the parabolic generation law (paraolic growth law).

Example four

This example will compare the oxide layer growth rate on silicon nitride (DCS) in an ISSG process for different parameters. Ratio of hydrogen to oxygen (H) in the process₂/H₂+O₂) About 25% and about 33%, respectively, and at temperatures of about 850 degrees celsius, 900 degrees celsius, and 950 degrees celsius, respectively. And the time intervals for measuring the thickness of the oxide layer are about 30 seconds, 60 seconds, 90 seconds, and 120 seconds. And a lamp type (XT) single wafer chamber is used to form the silicon nitride film in advance. Generally, in a higher temperature process, the oxide layer formed in each time interval is thicker. That is, the oxide layer formation rate is faster in the process at higher temperatures because the significant increase in kinetic energy in the oxygen radicals makes it easier to overcome the barrier of active energy. Furthermore, at each process temperature, H₂/H₂+O₂The higher the ratio, the faster the oxide layer is formed. Thus, the higher the hydrogen concentration at a given process temperature, the shorter the process time required for the oxide layer to reach a given thickness. Obviously, high concentrations of hydrogen accelerate the dissociation of oxygen molecules into reactive oxygen radicals, thereby enabling more oxygen radicals to participate in the reaction.

Example five

In this example, the oxide layer is formed on the nitride layer using an ISSG process at 850 degrees celsius and 950 degrees celsius. The nitride layer may be formed in a variety of different ways, including a dichlorosilane (DCS-based) nitride layer (XT lamp type chamber), an alkyl nitride formed using a single wafer chamber (XT lamp type), and an alkyl nitride formed using the SiNGen single wafer chamber system. As expected, the top oxide layer growth rate was faster at higher temperatures. And under the same temperature, the oxide layers on the three different types of films have similar growth rates.

The appropriate values for one or more of the above parameters will vary depending on the value of the other one or more parameters. For example, the time required for the process can be reduced, typically at higher process temperatures. Furthermore, at any given process temperature, the process time will be shorter if the ratio of hydrogen to oxygen in the mixed gas is higher. These examples provide suggested guidelines for determining preferred combinations of parameters, not for expressing a particular implementation, in accordance with the present invention.

Claims

1. A method for forming an ONO structure, comprising:

providing an oxide-nitride film on a surface of a substrate, the oxide-nitride film comprising:

a first oxide layer covering the substrate;

a silicon nitride layer covering the first oxide layer;

patterning the oxide-nitride film to define a bottom oxide and a silicon nitride portion of an ONO stack structure on the substrate, the bottom oxide and the silicon nitride portion having an exposed sidewall and the silicon nitride portion having an exposed surface; and

exposing the exposed sidewalls and the exposed surface to a rapid thermal oxidation in an ambient containing a free radical oxidizing agent to form an oxide layer on the exposed surfaces and the exposed sidewalls of the patterned silicon nitride portion and the patterned oxide portion.

2. The method of claim 1, wherein said free radical oxidizing agent comprises an oxygen radical.

3. The method of claim 1, wherein said free radical oxidizer comprises O^-。

4. The method of claim 1, wherein exposing comprises heating the substrate to a specified temperature and exposing the exposed sidewalls and exposed surface to a gas comprising an oxygen-containing gas and a hydrogen-containing gas in a specified ratio at a specified pressure for a specified time to generate the free radical oxidizing agent in the vicinity of the heated substrate by reaction of the oxygen-containing gas and constituents of the hydrogen-containing gas.

5. The method ofclaim 4, wherein heating the substrate comprises heating the substrate to a temperature in a range of approximately 700 degrees Celsius to approximately 1300 degrees Celsius.

6. The method of claim 4, wherein said heating said substrate comprises heating said substrate to a temperature in a range of approximately 900 degrees Celsius to 1150 degrees Celsius.

7. The method of claim 4, wherein said heating said substrate comprises heating said substrate to a temperature in a range of approximately 850 degrees Celsius to approximately 1000 degrees Celsius.

8. The method of claim 1, wherein said exposing comprises heating said substrate to a specified temperature and exposing said exposed sidewalls and said exposed surface to a specified ratio of O at a specified pressure₂And H₂Mixed gas is passed through O for a specific time₂And H₂By reaction of the constituent elements to produce O in the vicinity of the heated substrate^-。

9. The method of claim 8, wherein said exposing comprises heating said substrate to a temperature in a range of about 700 degrees celsius to about 1300 degrees celsius and exposing said exposed sidewalls and said exposed surface to an O atmosphere at a pressure in a range of about 1 torr to about 20 torr₂And H₂In a ratio of (i) H₂/H₂+O₂In the range of about 0.1% to about 40% of the mixed gas, for a period of about 1 to about 1000 seconds.

10. The method of claim 9 wherein said heating said substrate comprises heating said substrate to a temperature in the range of about 900 to 1150 degrees celsius.

11. The method of claim 9 wherein said step of heating said substrate comprises heating said substrate to a temperature in the range of about 850 ℃ to about 1000 ℃.

12. The method of forming an ONO structure of claim 9 wherein said exposing comprises flowing O over said substrate₂And H₂The ratio of the mixed gas of (1), i.e. H₂/H₂+O₂In the range of about 5% to about 33%.

13. The method of forming an ONO structure of claim 9 wherein said exposing comprises flowing O over said substrate₂And H₂The ratio of the mixed gas of (1), i.e. H₂∶O₂In the range of about 1: 19 to about 1: 2.

14. The method of forming an ONO structure of claim 9 wherein said exposing comprises O₂And H₂The mixed gas is flowed over the substrate for a time period in a range of about 10 seconds to about 500 seconds.

15. The method of claim 9A method of forming an ONO structure, wherein the exposing comprises O₂And H₂The mixed gas is flowed over the substrate for a time period in a range of about 30 seconds to about 300 seconds.

16. The method of claim 1, wherein said exposing comprises heating said substrate in a furnace and introducing a specific proportion of O at a specific pressure₂And H₂The mixed gas is passed through O for a specific time₂And H₂To generate O in the vicinity of the heated substrate^-。

17. The method of forming an ONO structure of claim 16 wherein said introducing O is performed₂And H₂The step of mixing the gas further comprises introducing a carrier gas.

18. The method of forming an ONO structure of claim 17 wherein said introducing O is performed₂And H₂The step of mixing the gas further comprises introducing N₂As a carrier gas.

19. The method of forming an ONO structure of claim 16 wherein said introducing said specified proportion of O₂And H₂The step of mixing the gas of (1), comprising introducing O at a specific flow rate ratio₂And H₂。

20. The method of forming an ONO structure of claim 19 wherein said introducing O is performed₂And H₂The step of mixing the gas further comprises introducing N at a specific flow rate₂As a carrier gas.

21. The method of forming an ONO structure of claim 19 wherein said introducing O is performed₂And H₂Comprises introducing O at an additive flow rate in the range of about 1 to 40slm₂And H₂。

22. The method of forming an ONO structure of claim 20 wherein said introducing O is performed₂And H₂Comprises introducing O at an additive flow rate in the range of about 1 to 40slm₂And H₂And introducing N₂Comprising introducing N at a flow rate of greater than 50slm₂。

23. A method for manufacturing a semiconductor device having an ONO structure includes:

providing an oxide-nitride film on a surface of a substrate, the substrate having first and second regions defined by an insulator, the oxide-nitride film including a first silicon oxide layer overlying the substrate and a silicon nitride layer overlying the first silicon oxide layer;

patterning the oxide-nitride film to expose the surface of the substrate in the second region on the substrate and define a bottom oxide layer and a silicon nitride layer in an ONO stack structure in the first region on the substrate, wherein the bottom oxide layer and the silicon nitride layer both have an exposed sidewall and the silicon nitride layer has an exposed surface;

exposing the exposed sidewalls and the exposed surface to a free radical oxidizing agent while the substrate is at a temperature between about 700 degrees celsius and about 1200 degrees celsius to form a second oxide layer on the exposed sidewalls and the exposed surface of the patterned silicon nitride layer portion and simultaneously form a gate oxide layer on the substrate surface in the second region; and

forming a conductive layer to cover the second oxide layer and the gate oxide layer.

24. The method of claim 23, wherein the radical oxidizing agent comprises an oxygen radical.

25. As claimed in claim 23 the method for fabricating a semiconductor device having an ONO structure, wherein the radical oxidizing agent comprises O^-。

26. The method of claim 23, wherein said exposing comprises heating said substrate to a temperature within said temperature range and exposing said exposed sidewalls and said exposed surface to a mixture of an oxygen-containing gas and a hydrogen-containing gas at a specified pressure and for a specified time to generate said free radical oxidizing agent in the vicinity of said heated substrate by reaction of constituents of said oxygen-containing gas and said hydrogen-containing gas.

27. The method of claim 26, wherein said heating the substrate comprises heating the substrate to a temperature in a range of about 900 degrees celsius to 1150 degrees celsius.

28. The method of claim 26, wherein said heating the substrate comprises heating the substrate to a temperature in a range of about 850 degrees celsius to about 1000 degrees celsius.

29. The method of claim 23, wherein said exposing comprises heating said substrate to a temperature within said temperature range and exposing said exposed sidewalls and exposed surface to a specific ratio of O at a specific pressure₂And H₂Mixed gas is passed through O for a specific time₂And H₂To generate O in the vicinity of the heated substrate^-。

30. The method of claim 29, wherein said exposing comprises heating said substrate to a temperature within said temperature rangeExposing the exposed sidewalls and the exposed surface to an O at a temperature and at a pressure approximately in the range of 1 Torr to 20 Torr₂And H₂In a ratio of (i) H₂/H₂+O₂In the range of about 0.1% to about 40% of the mixed gas, for a period of about 1 to about 1000 seconds.

31. The method of claim 30, wherein said heating the substrate comprises heating the substrate to a temperature in a range of about 900 degrees celsius to 1150 degrees celsius.

32. The method of claim 30, wherein said heating the substrate comprises heating the substrate to a temperature in a range of about 850 degrees celsius to about 1000 degrees celsius.

33. The method of claim 30, wherein said exposing comprises flowing O over said substrate₂And H₂The ratio of the mixed gas of (1), i.e. H₂/H₂+O₂In the range of about 5% to about 33%.

34. The method of claim 30, wherein said exposing comprises flowing O over said substrate₂And H₂The mixture ofWith a gas in a ratio of H₂∶O₂In the range of about 1: 19 to about 1: 2.

35. The method of claim 30, wherein said exposing comprises O₂And H₂The mixed gas is flowed over the substrate for a time period in a range of about 10 seconds to about 500 seconds.

36. The semiconductor device of claim 30 having an ONO structureMethod for manufacturing a component, characterized in that the exposure process comprises O₂And H₂The mixed gas is flowed over the substrate for a time period in a range of about 30 seconds to about 300 seconds.

37. The method of claim 23, wherein said exposing comprises heating said substrate in a furnace and introducing a specific proportion of O at a specific pressure₂And H₂The mixed gas is passed through O for a specific time₂And H₂To generate O in the vicinity of the heated substrate^-。

38. The method of fabricating a semiconductor device having an ONO structure as claimed in claim 37, wherein said introducing O is performed₂And H₂The step of mixing the gas further comprises introducing a carrier gas.

39. The method of claim 38, wherein said introducing O is performed by a single wafer process₂And H₂The step of mixing the gas further comprises introducing N₂As a carrier gas.

40. The method of claim 37, wherein said introducing of said specific O is performed in a single step₂And H₂The step of mixing the gas mixture further comprises introducing O at a specific flow rate ratio₂And H₂。

41. The method of claim 40, wherein the ONO structure comprises a plurality of oxide-nitride-oxide (ONO) structuresMethod characterized in that the introduction of O₂And H₂The step of mixing the gas further comprises introducing N at a specific flow rate₂As a carrier gas.

42. The method according to claim 40, wherein the ONO structure comprises a nitride oxide layer,characterized in that the introduction of O₂And H₂Comprises introducing O at an additive flow rate in the range of about 1 to 40slm₂And H₂。

43. The method of claim 41, wherein said introducing O is performed in a manner similar to that of said ONO structure₂And H₂Comprises introducing O at an additive flow rate in the range of about 1 to 40slm₂And H₂And introducing N₂Comprising introducing N at a flow rate of greater than 50slm₂。

44. The method of claim 23, wherein a thickness ratio of the second oxide layer to the gate oxide layer is in a range from about 0.6: 1 to about 0.8: 1.

45. The method of claim 23, wherein said exposing comprises heating said substrate in a furnace and generating said free radical oxidizing agent in said furnace while maintaining the temperature of said substrate at a temperature within said temperature range for about 10 seconds to about 500 seconds.

46. The method of claim 23, wherein said exposing comprises heating said substrate in a furnace and generating said free radical oxidizing agent in said furnace while maintaining the temperature of said substrate at a temperature within said temperature range for about 30 seconds to about 300 seconds.

47. A method for fabricating a memory device having an ONO structure, comprising:

providing an oxide-nitride film on a surface of a substrate, the substrate having a first region and a second region defined by an insulator, the oxide-nitride film including a first silicon oxide layer overlying the substrate and a silicon nitride layer overlying the first silicon oxide layer;

48. The method of claim 47, wherein said free radical oxidizing agent comprises an oxygen radical.

49. The method of claim 47, wherein said free radical oxidizing agent comprises O^-。

50. The method of claim 47, wherein said exposing comprises heating said substrate to a temperature within said temperature range and exposing said exposed sidewalls and exposed surface to a mixture of an oxygen-containing gas and a hydrogen-containing gas at a specified pressure and for a specified time to generate said free radical oxidizing agent in the vicinity of said heated substrate by reaction of said oxygen-containing gas and constituent elements of said hydrogen-containing gas.

51. The method of claim 50, wherein said heating the substrate comprises heating the substrate to a temperature in a range of about 900 degrees Celsius to 1150 degrees Celsius.

52. The method of claim 50, wherein said heating the substrate comprises heating the substrate to a temperature within a range of about 850 ℃ to about 1000 ℃.

53. The method of claim 47, wherein said exposing comprises heating said substrate to a temperature within said temperature range and exposing said exposed sidewalls and exposed surface to a specific ratio of O at a specific pressure₂And H₂Mixed gas is passed through O for a specific time₂And H₂To generate O in the vicinity of the heated substrate^-。

54. The method of claim 53, wherein said exposing comprises heating said substrate to a temperature within said temperature range and exposing said exposed sidewalls and said exposed surface to an O pressure within a range of about 1 Torr to about 20 Torr₂And H₂In a ratio of (i) H₂/H₂+O₂In the range of about 0.1% to about 40% of the mixed gas, for a period of about 1 to about 1000 seconds.

55. The method of claim 54, wherein said heating the substrate comprises heating the substrate to a temperature in a range of about 900 degrees Celsius to 1150 degrees Celsius.

56. The method of claim 54, wherein said heating the substrate comprises heating the substrate to a temperature within a range of about 850 degrees Celsius to about 1000 degrees Celsius.

57. The method of claim 54, wherein said exposing comprises flowing O over said substrate₂And H₂The ratio of the mixed gas of (1), i.e. H₂/H₂+O₂In the range of about 5% to about 33%.

58. The method of claim 54, wherein said exposing comprises flowing O over said substrate₂And H₂The ratio of the mixed gas of (1), i.e. H₂∶O₂In the range of about 1: 19 to about 1: 2.

59. The method of fabricating a memory device having an ONO structure of claim 54 wherein said exposing comprises O₂And H₂The mixed gas is flowed over the substrate for a time period in a range of about 10 seconds to about 500 seconds.

60. The method of fabricating a memory device having an ONO structure of claim 54 wherein said exposing comprises O₂And H₂The mixed gas is flowed over the substrate for a time period in a range of about 30 seconds to about 300 seconds.

61. The method of claim 47, wherein said exposing comprises heating said substrate in a furnace and introducing O at a specific ratio and pressure₂And H₂The mixed gas is passed through O for a specific time₂And H₂To generate O in the vicinity of the heated substrate^-。

62. Memory having an ONO structure as set forth in claim 61Method for manufacturing a device element, characterized in that the introduction of O₂And H₂The step of mixing the gas further comprises introducing a carrier gas.

63. The method of fabricating a memory device having an ONO structure as in claim 62, wherein said introducing O is performed by a single step₂And H₂The step of mixing the gas further comprises introducing N₂As a carrier gas.

64. The method of claim 61, wherein said introducing of said specific O is performed in a single step₂And H₂The step of mixing the gas mixture further comprises introducing O at a specific flow rate ratio₂And H₂。

65. The method of fabricating a memory device having an ONO structure as in claim 64, wherein said introducing O is performed by a single step₂And H₂The step of mixing the gas further comprises introducing N at a specific flow rate₂As a carrier gas.

66. The method of fabricating a memory device having an ONO structure as in claim 64, wherein said introducing O is performed by a single step₂And H₂Comprises introducing O at an additive flow rate in the range of about 1 to 40slm₂And H₂。

67. The method of fabricating a memory device having an ONO structure as in claim 65, wherein said introducing O is performed by a single step₂And H₂Comprises introducing O at an additive flow rate in the range of about 1 to 40slm₂And H₂And introducing N₂Comprising introducing N at a flow rate of greater than 50slm₂。

68. The method of claim 47, wherein a thickness ratio of the second oxide layer to the gate oxide layer is in a range from about 0.6: 1 to about 0.8: 1.

69. The method of claim 47, wherein said exposing comprises heating said substrate in a furnace and generating said free radical oxidizing agent in said furnace while maintaining the temperature of said substrate at a temperature within said temperature range for about 10 seconds to about 500 seconds.

70. The method of claim 47, wherein said exposing comprises heating said substrate in a furnace and generating said free radical oxidizing agent in said furnace while maintaining the temperature of said substrate at a temperature within said temperature range for about 30 seconds to about 300 seconds.

71. A semiconductor device having a silicon oxide/silicon nitride/silicon oxide structure, comprising:

a first silicon oxide layer covering a substrate;

a silicon nitride layer covering the first silicon oxide layer;

a second silicon oxide layer completely covering the silicon nitride layer and contacting the first silicon oxide layer; and

a gate conductive layer covering the second silicon dioxide layer.

72. A memory cell device having a silicon oxide/silicon nitride/silicon oxide structure, the memory cell device comprising:

an embedded drain and an embedded source disposed in a substrate;

a buried drain oxide layer covering the buried drain, and a buried source oxide layer covering the buried source;

a first silicon oxide layer covering a region between the buried drain and the buried source on the substrate and covering a portion of the buried drain oxide layer and a portion of the buried source oxide layer;

a silicon nitride layer covering part of the first silicon oxide layer;

a gate conductive layer covering the second silicon dioxide layer.

73. A rom having a memory cell element of a silicon oxide/silicon nitride/silicon oxide structure, the rom comprising:

an embedded drain and an embedded source disposed in a substrate;

a silicon nitride layer covering part of the first silicon oxide layer;

a gate conductive layer covering the second silicon dioxide layer.