CN1691502A - Lattice wave digital filter - Google Patents

Abstract

The invention provides a crystal lattice wave digital filter for digital signal processor, comprising a first processing unit or a second processing unit selectively according to the hardware resources. The first processing unit has only a multiplier and the second processing unit has several multipliers. The invention makes use of the special configuration on the circuit to equalize the path length of input signal passing from the first input port to the first output port and from the second input port to the second output port.

Description

The lattice wave digital filter

Technical field

The present invention is about a kind of lattice wave digital filter that is used for digital signal processor.

Background technology

In the field of present Digital Signal Processing (digital signal processing), lattice wave digital filter (lattice wave digital filter) is a very important element, and it is in order to carry out following transfer function:

$H\left(z\right)=\frac{1}{2}(H_1\left(z\right)+H_2\left(z\right))$

By above-mentioned transfer function as can be known, the lattice wave digital filter needs two all-pass filters to realize H ₁(z) and H ₂(z), a multiplier is realized parameter 1/2 and an adder.Figure 1A and Figure 1B are the circuit structure of lattice wave digital filter, and it comprises one first all-pass filter 11, one second all-pass filter 13, an adder 15 and a multiplier 17.

Wherein, shown in Figure 1B, first all-pass filter 11 and second all-pass filter 13 are formed by a plurality of processing units 19.Fig. 2 is the circuit structure of conventional treatment unit 19, and it comprises a first adder 201, a second adder 203, one the 3rd adder 205 and a multiplier 207.Fig. 3 is the state diagram of the processing unit 19 of Fig. 2.As Fig. 2 and shown in Figure 3, conventional treatment unit 19 has two inputs, in order to import one first input signal 200 (state 301) and one second input signal 202 (state 303).First adder 201 is used for receiving and addition first input signal 200 and second input signal 202, to produce one first transient signal 204 (state 305).Multiplier 207 is used for receiving first transient signal 204 and utilizes a predefined parameter value to carry out multiplying, to produce one second transient signal 206 (state 307).Second adder 203 is used for receiving and addition second input signal 202 and second transient signal 206, to produce one second output signal 210 (state 309).The 3rd adder 205 is used for receiving and addition first transient signal 204 and second output signal 210, to produce one first output signal 208 (state 311).First output signal 208 and second output signal 210 can be via the output outputs of processing unit 19, with the input signal as the next stage processing unit.Parameter value that it should be noted that multiplier 207 is decided according to the transfer function that desire realizes.

The circuit structure of conventional treatment unit 19 (three adders and a multiplier) can't be done suitable adjustment according to the configuration of hardware, makes can't reach optimization in the utilization of resource.In addition, as shown in Figure 3, when signal transmitted in conventional treatment unit 19, its beeline was state 303-〉state 309, and the longest distance is state 301 (or 303)-state 305-〉state 307-〉state 309-〉state 311.So big difference in length can cause the difference of signal passing time, and then produces the problem of data dependencies (data dependency).

Summary of the invention

The invention provides a kind of lattice wave digital filter, be applicable in the digital signal processor, can optionally comprise one first processing unit or one second processing unit according to the hardware resource of digital signal processor.First processing unit only has a multiplier, and second processing unit then has a plurality of multipliers.More clearly, when digital signal processor is only supported a multiplier, the lattice wave digital filter then selects first processing unit to realize its transfer function, when digital signal processor can be supported a plurality of multiplier, the lattice wave digital filter can select first processing unit or second processing unit to realize its transfer function, makes the utilization of resource can reach optimization.

In addition, first processing unit and second processing unit comprise a first input end, one second input, one first output and one second output respectively.The present invention utilizes the particular arrangement on the circuit to make input signal be passed to the path of first output via first input end to equate with the path that is passed to second output via second input.So can solve the problem of data dependencies effectively.

Description of drawings

Figure 1A is the calcspar of conventional lattice wave digital filter;

Figure 1B is the schematic diagram of conventional lattice wave digital filter;

Fig. 2 is the circuit diagram of conventional treatment unit;

Fig. 3 is the state diagram of the processing unit of Fig. 2;

Fig. 4 is the schematic diagram of processing unit of the present invention;

Fig. 5 is the circuit diagram of first embodiment of first processing unit;

Fig. 6 is the circuit diagram of second embodiment of first processing unit;

Fig. 7 is the circuit diagram of first embodiment of second processing unit;

Fig. 8 is the circuit diagram of second embodiment of second processing unit; And

Fig. 9 is the schematic diagram of lattice wave digital filter of the present invention.

The figure elements symbol description

11 first all-pass filters, 13 second all-pass filters

15 adders, 17 multipliers

19 processing units

200 first input signals, 201 first adders

202 second input signals, 203 second adders

204 first transient signals 205 the 3rd adder

206 second transient signals, 207 multipliers

208 first output signals, 210 second output signals

301,303,305,307,309,311 states

400 first input signals

402 second input signals, 403 first input ends

404 first output signals, 405 second inputs

406 second output signals, 407 second outputs

409 second outputs, 500 first input signals

501 first adders, 502 second input signals

503 second adders, 504 first transient signals

505 the 3rd adders, 506 second transient signals

507 multipliers, 508 second output signals

510 first output signals, 600 first input signals

601 first adders, 602 second input signals

603 second adders, 604 first transient signals

605 the 3rd adders, 606 second transient signals

607 multipliers, 608 first output signals

610 second output signals, 700 first input signals

701 first multipliers, 702 second input signals

703 second multipliers, 704 first transient signals

705 the 3rd multipliers, 706 second transient signals

707 the 4th multipliers 708 the 3rd transient signal

709 first adders 710 the 4th transient signal

711 second adders, 712 first output signals

714 second output signals, 800 first input signals

801 first multipliers, 802 first transient signals

803 second multipliers, 804 second input signals

805 first adders, 806 second transient signals

807 second adders 808 the 3rd transient signal

809 the 3rd multipliers 810 the 4th transient signal

811 the 4th multipliers, 812 first output signals

814 second output signals

91 first order circuit, 93 second level circuit

95 tertiary circuits, 97 fourth stage circuit

Embodiment

As shown in Figure 4, processing unit of the present invention (i.e. first processing unit and second processing unit) 19 comprises a first input end 403, one second input 405, one first output 407 and one second output 409.Processing unit 19 receives one first input signal 400 and one second input signal 402, produces one first output signal 404 and one second output signal 406 after computing.Wherein, first input signal 400 path (shown in dotted line) that is passed to first output 407 via first input end 403 equates via the path (shown in dotted line) that second input 405 is passed to second output 409 with second input signal 402.

First processing unit of the present invention comprises three adders and a multiplier, and second processing unit of the present invention comprises two adders and four multipliers.Structural difference like this makes the lattice wave digital filter suitably to select first processing unit or second processing unit according to hardware resource.

First processing unit

First embodiment of first processing unit comprises a first adder 501, a second adder 503, one the 3rd adder 505 and a multiplier 507 as shown in Figure 5.First adder 501 is connected to the first input end 403 and second input 405, in order to receive first input signal 500 (being first input signal 400 of Fig. 4) and second input signal 502 (being second input signal 402 of Fig. 4), through after the add operation of first adder 501, produce one first transient signal 504.Multiplier 507 is connected to first adder 501, in order to receive first transient signal 504 and to carry out multiplying according to a parameter value, produces one second transient signal 506.Second adder 503 is connected to first input end 403 and multiplier 507, in order to receive first input signal 500 and second transient signal 506 and to carry out add operation, produces one second output signal 508 (being second output signal 406 of Fig. 4).The 3rd adder 505 is connected to second input 405 and multiplier 507, in order to receive second input signal 502 and second transient signal 506 and to carry out add operation, produces one first output signal 510 (being first output signal 404 of Fig. 4).First output signal 510 is by 407 outputs of first output, and second output signal 508 is by 409 outputs of second output.

Second embodiment of first processing unit comprises a first adder 601, a second adder 603, one the 3rd adder 605 and a multiplier 607 as shown in Figure 6.First adder 601 is connected to the first input end 403 and second input 405, in order to receive first input signal 600 (being first input signal 400 of Fig. 4) and second input signal 602 (being second input signal 402 of Fig. 4) and to carry out add operation, produce one first transient signal 604.Multiplier 607 is connected to first adder 601, in order to receive first transient signal 604 and to carry out multiplying according to a parameter value, produces one second transient signal 606.Second adder 603 is connected to first input end 403 and multiplier 607, in order to receive first input signal 600 and second transient signal 606 and to carry out add operation, produces one first output signal 608 (being first output signal 404 of Fig. 4).The 3rd adder 605 is connected to second input 405 and multiplier 607, in order to receive second input signal 602 and second transient signal 606 and to carry out add operation, produces one second output signal 610 (being second output signal 406 of Fig. 4).First output signal 608 is by 407 outputs of first output, and second output signal 610 is by 409 outputs of second output.

Second processing unit

First embodiment of second processing unit comprises one first multiplier 701, one second multiplier 703, one the 3rd multiplier 705, one the 4th multiplier 707, a first adder 709 and a second adder 711 as shown in Figure 7.First multiplier 701 is connected to first input end 403, in order to receive first input signal 700 (being first input signal 400 of Fig. 4) and to carry out multiplying according to one first parameter value, produces one first transient signal 704.Second multiplier 703 also connects first input end 403, in order to receive first input signal 700 and to carry out multiplying according to one second parameter value, produces one second transient signal 706.The 3rd multiplier 705 is connected to second input 405, in order to import second input signal 702 (being second input signal 402 of Fig. 4) and to carry out multiplying according to one the 3rd parameter value, produces one the 3rd transient signal 708.The 4th multiplier 707 also is connected to second input 405, in order to receive second input signal 702 and to carry out multiplying according to one the 4th parameter value, produces one the 4th transient signal 710.First adder 709 is connected to first multiplier 701 and the 3rd multiplier 705, in order to receive first transient signal 704 and the 3rd transient signal 708 and to carry out add operation, produces one first output signal 712 (being first output signal 404 of Fig. 4).Second adder 711 is connected to second multiplier 703 and the 4th multiplier 707, in order to receive second transient signal 706 and the 4th transient signal 710 and to carry out add operation, produces one second output signal 714 (being second output signal 406 of Fig. 4).First output signal 712 is by 407 outputs of first output, and second output signal 714 is by 409 outputs of second output.

Second embodiment of second processing unit comprises one first multiplier 801, one second multiplier 803, one the 3rd multiplier 809, one the 4th multiplier 811, a first adder 805 and a second adder 807 as shown in Figure 8.First multiplier 801 is connected to first input end 403, in order to receive first input signal 800 (being first input signal 400 of Fig. 4) and to carry out multiplying according to one first parameter value, produces one first transient signal 802.Second multiplier 803 is connected to second input 405, in order to receive second input signal 804 (being second input signal 402 of Fig. 4) and to carry out multiplying according to one second parameter value, produces one second transient signal 806.First adder 805 is connected to first multiplier 801 and second input 405, in order to receive first transient signal 802 and second input signal 804 and to carry out add operation, produces one the 3rd transient signal 808.Second adder 807 is connected to second multiplier 803 and first input end 403, in order to receive second transient signal 806 and first input signal 800 and to carry out add operation, produces one the 4th transient signal 810.The 3rd multiplier 809 is connected to first adder 805, in order to receive the 3rd transient signal 808 and to carry out multiplying according to one the 3rd parameter value, produces one first output signal 812 (being first output signal 404 of Fig. 4).The 4th multiplier 811 is connected to second adder 807, in order to receive the 4th transient signal 810 and to carry out multiplying according to one the 4th parameter value, produces one second output signal 814 (being second output signal 406 of Fig. 4).First output signal 812 is by 407 outputs of first output, and second output signal 814 is by 409 outputs of second output.

Can find out from Fig. 5,6,7,8, the circuit structure of the foregoing description has tangible symmetry, therefore first input signal 400 be passed to the path of first output 407 by first input end 403 can be identical by the path that second input 405 is passed to second output 409 with second input signal 402, so can avoid the problem of data dependencies.

In addition, when lattice wave digital filter of the present invention was selected first processing unit or second processing unit according to hardware resource, first and second all-pass filter in the lattice wave digital filter all utilized first processing unit of identical (selected) or second processing unit to form.Therefore more strengthen the symmetry of first and second all-pass filter, and then more reduce the dependence of data.

Further, if hardware resource is enough, first and second all-pass filter can partly use first processing unit and partly use second processing unit.As shown in Figure 9, first all-pass filter 11 has a first order circuit 91 and a second level circuit 93.Second all-pass filter 13 has a tertiary circuit 95 and a fourth stage circuit 97.Wherein first order circuit 91 promptly has the processing unit of same structure and number corresponding to tertiary circuit 95, just optionally comprises the first identical processing unit or second processing unit.Second level circuit 93 also optionally comprises the first identical processing unit or second processing unit corresponding to fourth stage circuit 97.So first order circuit 91 has symmetry with tertiary circuit 95, second level circuit 93 has symmetry with fourth stage circuit 97, similarly can reduce the dependence of data.It should be noted that, the processing unit of first order circuit 91 and second level circuit 93 (or tertiary circuit 95 and fourth stage circuit 97) does not need identical, and the present invention does not limit the differentiation mode of first order circuit 91, second level circuit 93, tertiary circuit 95 and fourth stage circuit 97.

Above narration only is explanation spirit of the present invention, should be with this as restriction.Those skilled in the art can do suitable variation under the situation of the scope that does not surmount claim and contained.

Claims (20)

1. lattice wave digital filter, be applicable to a digital signal processor, this lattice wave digital filter is according to the hardware resource of this digital signal processor, optionally comprise one first processing unit and one second processing unit one of them, this first processing unit has a multiplier, and this second processing unit has a plurality of multipliers.

2. lattice wave digital filter as claimed in claim 1, wherein this first processing unit comprises:

One first input end;

One second input;

One first output; And

One second output;

Wherein, one first input signal equates via the path of this second input to this second output with one second input signal via the path of this first input end to this first output.

3. lattice wave digital filter as claimed in claim 2, wherein this first processing unit also comprises:

One first adder is connected to this first input end and this second input, in order to this first input signal of addition and this second input signal, and produces one first transient signal;

One multiplier is connected to this first adder, in order to this first transient signal and the parameter value of multiplying each other, and produces one second transient signal;

One second adder is connected to this first input end and this multiplier, in order to this first input signal of addition and this second transient signal, and produces one second output signal; And

One the 3rd adder is connected to this second input and this multiplier, in order to this second input signal of addition and this second transient signal, and produces one first output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

4. lattice wave digital filter as claimed in claim 2, wherein this first processing unit also comprises:

One first adder is connected to this first input end and this second input, in order to this first input signal of addition and this second input signal, and produces one first transient signal;

One multiplier is connected to this first adder, in order to this first transient signal and the parameter value of multiplying each other, and produces one second transient signal;

One second adder is connected to this first input end and this multiplier, in order to this first input signal of addition and this second transient signal, and produces one first output signal; And

One the 3rd adder is connected to this second input and this multiplier, in order to this second input signal of addition and this second transient signal, and produces one second output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

5. lattice wave digital filter as claimed in claim 1, wherein this second processing unit comprises:

One first input end;

One second input;

One first output; And

One second output;

Wherein, one first input signal equates via the path of this second input to this second output with one second input signal via the path of this first input end to this first output.

6. lattice wave digital filter as claimed in claim 5, wherein this second processing unit also comprises:

One first multiplier is connected to this first input end, in order to this first input signal and one first parameter value of multiplying each other, and produces one first transient signal;

One second multiplier is connected to this first input end, in order to this first input signal and one second parameter value of multiplying each other, and produces one second transient signal;

One the 3rd multiplier is connected to this second input, in order to this second input signal and one the 3rd parameter value of multiplying each other, and produces one the 3rd transient signal;

One the 4th multiplier is connected to this second input, in order to this second input signal and one the 4th parameter value of multiplying each other, and produces one the 4th transient signal;

One first adder is connected to this first multiplier and the 3rd multiplier, in order to this first transient signal of addition and the 3rd transient signal, and produces one first output signal; And

One second adder is connected to this second multiplier and the 4th multiplier, in order to this second transient signal of addition and the 4th transient signal, and produces one second output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

7. lattice wave digital filter as claimed in claim 5, wherein this second processing unit also comprises:

One first multiplier is connected to this first input end, in order to this first input signal and one first parameter value of multiplying each other, and produces one first transient signal;

One second multiplier is connected to this second input, in order to this second input signal and one second parameter value of multiplying each other, and produces one second transient signal;

One first adder is connected to this first multiplier and this second input, in order to this first transient signal of addition and this second input signal, and produces one the 3rd transient signal;

One second adder is connected to this second multiplier and this first input end, in order to this second transient signal of addition and this first input signal, and produces one the 4th transient signal;

One the 3rd multiplier is connected to this first adder, in order to the 3rd transient signal and one the 3rd parameter value of multiplying each other, and produces one first output signal; And

One the 4th multiplier is connected to this second adder, in order to the 4th transient signal and one the 4th parameter value of multiplying each other, and produces one second output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

8. lattice wave digital filter as claimed in claim 1 also comprises:

One first all-pass filter has a first order circuit and a second level circuit; And

One second all-pass filter has a tertiary circuit and a fourth stage circuit;

Wherein this first order circuit is corresponding to this tertiary circuit, and optionally comprise simultaneously this first processing unit and this second processing unit one of them, this second level circuit is corresponding to this fourth stage circuit, and optionally comprise simultaneously this first processing unit and this second processing unit one of them.

9. a lattice wave digital filter is applicable to a digital signal processor, and this lattice wave digital filter comprises:

One first all-pass filter has a first order circuit and a second level circuit; And

One second all-pass filter has a tertiary circuit and a fourth stage circuit;

Wherein, this lattice wave digital filter is according to the hardware resource of this digital signal processor, optionally comprise one first processing unit and one second processing unit one of them, this first processing unit has a multiplier, this second processing unit has four multipliers, this first order circuit is corresponding to this tertiary circuit, and optionally comprise simultaneously this first processing unit and this second processing unit one of them, this second level circuit is corresponding to this fourth stage circuit, and optionally comprise simultaneously this first processing unit and this second processing unit one of them.

10. lattice wave digital filter as claimed in claim 9, wherein this first processing unit comprises:

One first input end;

One second input;

One first output; And

One second output;

Wherein, one first input signal equates via the path of this second input to this second output with one second input signal via the path of this first input end to this first output.

11. lattice wave digital filter as claimed in claim 10, wherein this first processing unit also comprises:

One first adder is connected to this first input end and this second input, imports this first input signal and this second input signal in order to addition, and produces one first transient signal;

One multiplier is connected to this first adder, in order to this first transient signal and the parameter value of multiplying each other, and produces one second transient signal;

One second adder is connected to this first input end and this multiplier, in order to this first input signal of addition and this second transient signal, and produces one second output signal; And

One the 3rd adder is connected to this second input and this multiplier, in order to this second input signal of addition and this second transient signal, and produces one first output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

12. lattice wave digital filter as claimed in claim 10, wherein this first processing unit also comprises:

One first adder is connected to this first input end and this second input, imports this first input signal and this second input signal in order to addition, and produces one first transient signal;

One multiplier is connected to this first adder, in order to this first transient signal and the parameter value of multiplying each other, and produces one second transient signal;

One second adder is connected to this first input end and this multiplier, in order to this first input signal of addition and this second transient signal, and produces one first output signal; And

One the 3rd adder is connected to this second input and this multiplier, in order to this second input signal of addition and this second transient signal, and produces one second output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

13. lattice wave digital filter as claimed in claim 9, wherein this second processing unit comprises:

One first input end;

One second input;

One first output; And

One second output;

Wherein, one first input signal equates via the path of this second input to this second output with one second input signal via the path of this first input end to this first output.

14. lattice wave digital filter as claimed in claim 13, wherein this second processing unit also comprises:

One first multiplier is connected to this first input end, in order to this first input signal and one first parameter value of multiplying each other, and produces one first transient signal;

One second multiplier is connected to this first input end, in order to this first input signal and one second parameter value of multiplying each other, and produces one second transient signal;

One the 3rd multiplier is connected to this second input, in order to this second input signal and one the 3rd parameter value of multiplying each other, and produces one the 3rd transient signal;

One the 4th multiplier is connected to this second input, in order to this second input signal and one the 4th parameter value of multiplying each other, and produces one the 4th transient signal;

One first adder is connected to this first multiplier and the 3rd multiplier, in order to this first transient signal of addition and the 3rd transient signal, and produces one first output signal; And

One second adder is connected to this second multiplier and the 4th multiplier, in order to this second transient signal of addition and the 4th transient signal, and produces one second output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

15. lattice wave digital filter as claimed in claim 13, wherein this second processing unit also comprises:

One first multiplier is connected to this first input end, in order to this first input signal and one first parameter value of multiplying each other, and produces one first transient signal;

One second multiplier is connected to this second input, in order to this second input signal and one second parameter value of multiplying each other, and produces one second transient signal;

One first adder is connected to this first multiplier and this second input, in order to this first transient signal of addition and this second input signal, and produces one the 3rd transient signal;

One second adder is connected to this second multiplier and this first input end, in order to this second transient signal of addition and this first input signal, and produces one the 4th transient signal;

One the 3rd multiplier is connected to this first adder, in order to the 3rd transient signal and one the 3rd parameter value of multiplying each other, and produces one first output signal; And

One the 4th multiplier is connected to this second adder, in order to the 4th transient signal and one the 4th parameter value of multiplying each other, and produces one second output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

16. a lattice wave digital filter is applicable to a digital signal processor, this lattice wave digital filter comprises:

One first all-pass filter has a first order circuit and a second level circuit; And

One second all-pass filter has a tertiary circuit and a fourth stage circuit;

Wherein, this lattice wave digital filter is according to the hardware resource of this digital signal processor, optionally comprise one first processing unit and one second processing unit one of them, this first order circuit is corresponding to this tertiary circuit, and optionally comprise simultaneously this first processing unit and this second processing unit one of them, this second level circuit is corresponding to this fourth stage circuit, and optionally comprise simultaneously this first processing unit and this second processing unit one of them;

Wherein, this first processing unit has a multiplier, this second processing unit has four multipliers, this first processing unit and this second processing unit comprise a first input end, one second input, one first output and one second output respectively, and one first input signal equates via the path of this second input to this second output with one second input signal via the path of this first input end to this first output.

17. lattice wave digital filter as claimed in claim 16, wherein this first processing unit also comprises:

One first adder is connected to this first input end and this second input, imports this first input signal and this second input signal in order to addition, and produces one first transient signal;

One multiplier is connected to this first adder, in order to this first transient signal and the parameter value of multiplying each other, and produces one second transient signal;

One second adder is connected to this first input end and this multiplier, in order to this first input signal of addition and this second transient signal, and produces one second output signal; And

One the 3rd adder is connected to this second input and this multiplier, in order to this second input signal of addition and this second transient signal, and produces one first output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

18. lattice wave digital filter as claimed in claim 16, wherein this first processing unit also comprises:

One first adder is connected to this first input end and this second input, imports this first input signal and this second input signal in order to addition, and produces one first transient signal;

One multiplier is connected to this first adder, in order to this first transient signal and the parameter value of multiplying each other, and produces one second transient signal;

One second adder is connected to this first input end and this multiplier, in order to this first input signal of addition and this second transient signal, and produces one first output signal; And

One the 3rd adder is connected to this second input and this multiplier, in order to this second input signal of addition and this second transient signal, and produces one second output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

19. lattice wave digital filter as claimed in claim 16, wherein this second processing unit also comprises:

One first multiplier is connected to this first input end, in order to this first input signal and one first parameter value of multiplying each other, and produces one first transient signal;

One second multiplier is connected to this first input end, in order to this first input signal and one second parameter value of multiplying each other, and produces one second transient signal;

One the 3rd multiplier is connected to this second input, in order to this second input signal and one the 3rd parameter value of multiplying each other, and produces one the 3rd transient signal;

One the 4th multiplier is connected to this second input, in order to this second input signal and one the 4th parameter value of multiplying each other, and produces one the 4th transient signal;

One first adder is connected to this first multiplier and the 3rd multiplier, in order to this first transient signal of addition and the 3rd transient signal, and produces one first output signal; And

One second adder is connected to this second multiplier and the 4th multiplier, in order to this second transient signal of addition and the 4th transient signal, and produces one second output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

20. lattice wave digital filter as claimed in claim 16, wherein this second processing unit also comprises:

One first multiplier is connected to this first input end, in order to this first input signal and one first parameter value of multiplying each other, and produces one first transient signal;

One second multiplier is connected to this second input, in order to this second input signal and one second parameter value of multiplying each other, and produces one second transient signal;

One first adder is connected to this first multiplier and this second input, in order to this first transient signal of addition and this second input signal, and produces one the 3rd transient signal;

One second adder is connected to this second multiplier and this first input end, in order to this second transient signal of addition and this first input signal, and produces one the 4th transient signal;

One the 3rd multiplier is connected to this first adder, in order to the 3rd transient signal and one the 3rd parameter value of multiplying each other, and produces one first output signal; And

One the 4th multiplier is connected to this second adder, in order to the 4th transient signal and one the 4th parameter value of multiplying each other, and produces one second output signal;

Wherein, this first output signal is by this first output output, and this second output signal is by this second output output.

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