CN1689117A - Memory - Google Patents
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- CN1689117A CN1689117A CN03824185.4A CN03824185A CN1689117A CN 1689117 A CN1689117 A CN 1689117A CN 03824185 A CN03824185 A CN 03824185A CN 1689117 A CN1689117 A CN 1689117A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Abstract
A memory having a plurality of banks (BNKA, BNKB, BNKC, BNKD) each having a plurality of memory cells for storing data, and a plurality of bit lines for reading out data from the plurality of memory cells. The plurality of banks have bit lines of equal length.
Description
Technical field
The present invention relates to memory storage, particularly relate to memory storage with a plurality of memory set.
Background technology
Flash memories has Nonvolatile storage unit, and is that unit carries out data deletion and data write with the section with a plurality of storage unit.The operator scheme of flash memories comprises: read mode, read the data of selected one or more storage unit; Puncturing pattern, all storage unit in selected section write data " 1 "; Programming (writing) pattern writes data " 0 " to selected one or more storage unit.
In addition, in above-mentioned programming mode and puncturing pattern, the stress that oriented storage unit with floating boom applies constant noble potential applies step and after this checks the checking procedure of the variations in threshold voltage of storage unit, and till repeating to proceed to desirable data and being written into.Promptly, in programming mode, apply positive high voltage to control gate, thereby inject electronics to floating boom, till reaching certain threshold voltage more than the value, in puncturing pattern, apply as back-biased positive high voltage to substrate-side, thereby draw electronics from floating boom, till reaching certain threshold voltage below the value.Therefore, in flash memories, when the section in a certain memory set is in programming or the deletion action, even the storage unit of other sections in this memory set is also forbidden read operation.
In addition, because comparing with read operation, programming and deletion action need for a long time, so to a certain memory set starting program or deletion action the time, the storage area that can read tails off, and the restriction of read operation takes place thus.
In order to reduce these restrictions, need the flash memories of multi-memory group structure.That is,, can reduce owing to just programming or delete and the capacity of the storer that can't visit by increasing the quantity of memory set.
And, as another characteristics, even flash memories is also to keep storing the non-volatility memorizer of data under the state of power cutoff, so it is more to be used as the situation of the semiconductor memory that is used to be recorded in the boot of visiting at first when starting power supply.Thereupon, flash memories usually is made of memory set with guiding segments accessed when starting power supply and the memory set with common section in addition.
At this moment, according to size of boot etc., need with user's purposes corresponding memory group structure, the capacity that for example has the memory set of guiding segments is compared flash memories of little flash memories or equal capacity etc. with the capacity of other memory set.
As the method that satisfies these two kinds of demands simultaneously, propose to have the combination that changes a plurality of real storage groups by kind to constitute the combination of a plurality of virtual memory groups, thereby satisfy the method for multiple needs by flash memories.
Like this, in flash memories in order to reduce owing to programming or deleting and the capacity of the storer that can't visit, generally mostly be structure based on the multi-memory group, and, for corresponding to multiple use, carried the function that can change combination, with the ratio of the capacity of the capacity that allows to freely to design memory set and other memory set with guiding segments by kind.
Here, can carry out freely designing and be meant for example in four real storage groups (volume ratio 1: 3: 3: under the situation 1), realize two groups virtual memory group (volume ratio 1: 7,2: 6,4: 4) or four groups virtual memory group (volume ratio 1: 3: 3: the combination of multiple virtual memory group 1).Yet, with regard to the structure example of virtual memory group, the shape difference of each memory set, and deviation often takes place in bit line length.
In general flash memories, little current conversion in the memory cell transistor is become current potential, and read by comparing with reference potential, when yet bit line is long, stray capacitance at selecteed bit line is also bigger, thereby current potential conversion is slack-off, and therefore just acquisition is enough to the poor current potential that compares with reference potential, spended time.That is, this means that the data read in the longest virtual memory group combination of bit line length becomes the poorest visit.
Summary of the invention
The purpose of this invention is to provide the memory storage that a kind of structure that can be not limited to the virtual memory group realizes best reading speed.
According to a design of the present invention, can provide a kind of memory storage with a plurality of memory set.Each memory set has and is used to store a plurality of storage unit of data and is used for a plurality of bit lines from a plurality of storage unit reading of data.The bit line of all memory set of a plurality of memory set is isometric.
Because the bit line of all memory set is isometric, so can accelerate the access speed of memory storage integral body.In addition, because the form that can be not limited to as the virtual memory group of the combination of real storage group makes the bit line of all virtual memory groups isometric, so can carry out reading at a high speed.
Description of drawings
Fig. 1 is the figure that illustrates according to the structure example of the real storage group of the flash memories of embodiment of the present invention;
Fig. 2 is the figure that illustrates according to the hierarchical block structure example in the real storage group of present embodiment;
Fig. 3 A～Fig. 3 D is the figure that the structure example of four kinds of flash memories is shown;
Fig. 4 A and Fig. 4 B are the figure that real storage group structure example is shown;
Fig. 5 A～Fig. 5 D is the figure that the structure example of four kinds of flash memories in the present embodiment is shown;
Fig. 6 A and Fig. 6 B are the figure that the real storage group structure example in the present embodiment is shown.
Embodiment
Below, the example of embodiment of the present invention is described with reference to accompanying drawing.Protection scope of the present invention is not limited to following embodiment, and the invention that covers claims record is equal to invention with it.
Fig. 1 is the figure that illustrates according to the structure example of the real storage group of the flash memory device of embodiment of the present invention.The real storage group comprises a plurality of storage unit m00, m01, m10, the m11 with floating boom.Storage unit m00～m11 is configured in the crossover location of each word line WL0, WL1 and bit line BL0, BL1 respectively, and the storage data.
Memory cell transistor m00, its control gate are connected on the word line WL0, and drain electrode is connected on the bit line BL0, and source electrode is connected on the earthing potential.Memory cell transistor m01, its control gate are connected on the word line WL0, and drain electrode is connected on the bit line BL1, and source electrode is connected on the earthing potential.Memory cell transistor m10, its control gate are connected on the word line WL1, and drain electrode is connected on the bit line BL0, and source electrode is connected on the earthing potential.Memory cell transistor m11, its control gate are connected on the word line WL1, and drain electrode is connected on the bit line BL1, and source electrode is connected on the earthing potential.
Drive word line WL0, WL1 by word driver 101 according to the address.Bit line BL0, BL1 are connected with data bus DB via column gate 103.Column gate 103 is according to the address, and the one or more bit lines that will select from a plurality of bit lines etc. are connected on one or more data bus DB.Selection by word line WL0, WL1 and bit line BL0, BL1 comes among select storage unit m00～m11.The data that read from selected storage unit m00 etc. are output on the data bus DB via bit line BL0 or BL1.The data that 102 pairs of one or more sensor amplifiers read on one or more data bus DB are amplified.
Under the deletion state, memory cell transistor m00 etc. is in the low state of threshold value (data " 1 ").Under programming state,, in floating boom, inject negative charge, thereby threshold voltage settings is got high by word line WL0 or WL1 and bit line BL0 or BL1 are controlled on the positive noble potential.This state is data " 0 ".In addition, when deleting,, word line WL0 or WL1 are controlled on the earthing potential, and back bias is controlled on the positive noble potential, draw the negative charge in the floating boom by with bit line BL0 or BL1 open (OPEN), thus must be low with threshold voltage settings.This state is data " 1 ".When reading, on word line WL0 or WL1, apply the medium voltage of two kinds of threshold voltages, thereby read the storage data by the size of the electric current that on bit line BL0 or BL1, flows corresponding to threshold status.
Fig. 2 is the figure that illustrates according to the hierarchical block structure example in the real storage group of present embodiment.Major word driver 201 is controlled the voltage of main word line MWL (the 3rd metal level) according to the address, and this main word line MWL is connected with a plurality of vertical block BLK.202 pairs of data that read on the data bus DB of sensor amplifier block are amplified.In the zone 203, a plurality of vertical block BLK along continuous straight runs are arranged.Each vertical block BLK has vertically arranged a plurality of section SEC in zone 204.Center section at section SEC has disposed vertical word driver 221 and sub-driver 222.In the right side and the left side of section, disposed 1/2 and selected circuit 211,213 and cell array 212.
Read method then is described.Select circuit 231 to describe with regard to 1/4.Four gate line g3 are connected with the grid of four n channel MOS transistor m3.According to the address, one among four gate line g3 becomes high level, thereby has only corresponding therewith transistor m3 conducting.Common data bus DB is connected on bit line (second metal level) BL2 thus.That is among four gate line g3 of selection.Bit line BL2 can be connected with storage unit mc1, mc2, mc3, mc4.Select by this, select four storage unit mc1, mc2, mc3, mc4 in a plurality of storage unit.
1/2 selects circuit 211 to have n channel MOS transistor m1.Transistor m1, its grid is connected with gate line g1, and drain electrode is connected with bit line BL2, and source electrode is connected with the drain electrode of memory cell transistor mc2 and mc4.The source electrode of memory cell transistor mc1～mc4 is connected on the earthing potential.1/2 selects circuit 213 to have n channel MOS transistor m2.Transistor m2, its grid is connected with gate line g2, and drain electrode is connected with bit line BL2, and source electrode is connected with the drain electrode of memory cell transistor mc1 and mc3.
According to the address, a certain among above-mentioned gate line g1 and the g2 becomes high level.For example gate line g1 becomes high level, thus transistor m1 conducting, and transistor m2 ends.Thus, bit line BL2 is connected on memory cell transistor mc2 and the mc4.Carrying out 1/2 thus selects.Select combine and can carry out 1/8 selection with above-mentioned 1/4.
In addition, as mentioned above, owing to selected sub-word line SWL, so as a result of storage unit mc4 is selected.On bit line BL2 and common data bus DB, have with the corresponding electric current of the threshold voltage of storage unit mc4 and flow.Sensor amplifier block 202 becomes voltage to amplify the current conversion of this data bus DB, and it is exported to the outside as reading of data.
Promptly, on as the memory cell transistor mc4 on the crossover location that is disposed at sub-word line SWL and bit line BL2 of above-mentioned selection, if threshold voltage becomes low state (data " 1 "), then have bigger electric current and flow through bit line BL2, if threshold voltage becomes high state (data " 0 "), then on bit line BL2, almost there is not electric current to flow through.Bit line BL2 is connected with data bus DB via column gate (1/2 selects circuit 211,213 and 1/4 to select the general name of circuit 231), and then is connected with sensor amplifier block 202.The electric current that flows through bit line BL2 is exaggerated at this sensor amplifier block 202, thereby stores reading of data.
Main word line MWL is total by a plurality of vertical block BLK, and in each vertical block BLK via sub-driver 222 after, driven element word line SWL in vertical block BLK.Therefore, the stray capacitance among the main word line MWL comprises junction capacity in each sub-driver 222 corresponding with the progression of vertical block BLK and the wiring capacitance corresponding with length of arrangement wire.In addition, only otherwise change the number of the storage unit mc3 that connected by grid etc. in vertical block BLK, the stray capacitance among the sub-word line SWL is just constant.
Similarly, bit line BL2 is total by a plurality of section SEC, and selects after the circuit 211,213 via 1/2 in each section SEC, and is total by the storage unit mc1 in the section SEC etc.Therefore, the stray capacitance among the bit line BL2 comprises that corresponding each of progression with section SEC 1/2 select junction capacity in circuit 211,213 and the wiring capacitance corresponding with length of arrangement wire.In addition, only otherwise change the number of the storage unit mc1 that in section SEC, connected etc., just constant via the stray capacitance in 1/2 bit line of selecting behind the circuit 211,213 by knot.
In general, MWL compares with main word line (the 3rd metal line), and the wiring capacitance of bit line BL2 (second metal line) is big.When reading, because the Weak current of storage unit mc1 etc. must flow through bit line BL2, thus if this bit line BL2 has superfluous stray capacitance, then be difficult to find movement of electric charges, unsatisfactory from this point.Therefore, the progression of the section SEC of the length of decision bit line BL2 should not got a lot.
Fig. 3 A～Fig. 3 D is the figure that the structure example of four kinds of flash memories is shown.Four kinds of flash memories constitute by four real storage group BNKA, BNKB, BNKC, BNKD.Real storage group BNKA and BNKD are 1/8 memory capacity of whole memory area.Real storage group BNKB and BNKC are 3/8 memory capacity of whole memory area.That is, real storage group BNKB and BNKC have 3 times of memory capacity to real storage group BNKA and BNKD.The memory capacity ratio of four real storage group BNKA～BNKD is 1: 4: 4: 1.
The flash memories of Fig. 3 A has two virtual memory group VBNK1 and VBNK2.Virtual memory group VBNK1 is made of a real storage group BNKA.Virtual memory group VBNK2 is made of three real storage group BNKB, BNKC, BNKD.The memory capacity ratio of virtual memory group VBNK1 and virtual memory group VBNK2 is 1: 7.
The flash memories of Fig. 3 B has two virtual memory group VBNK1 and VBNK2.Virtual memory group VBNK1 is made of two real storage group BNKA, BNKD.Virtual memory group VBNK2 is made of two real storage group BNKB, BNKC.The memory capacity ratio of virtual memory group VBNK1 and virtual memory group VBNK2 is 2: 6.
The flash memories of Fig. 3 C has two virtual memory group VBNK1 and VBNK2.Virtual memory group VBNK1 is made of two real storage group BNKA, BNKB.Virtual memory group VBNK2 is made of two real storage group BNKC, BNKD.The memory capacity ratio of virtual memory group VBNK1 and virtual memory group VBNK2 is 4: 4.
The flash memories of Fig. 3 D has four virtual memory group BNKA～BNKD.That is, the real storage group is identical with the virtual memory group.
The flash memories of Fig. 3 A～Fig. 3 C is two groups the storer that is made of two virtual memory groups.The flash memories of Fig. 3 D is four groups the storer that is made of four virtual memory groups.
Here, the real storage group is meant the actual set that is formed on a plurality of storage unit on the memory area, it comprises word driver 101, row gate 103 and memory cell array m00～m11 at least, and select by the selection signal of real storage group, this selection signal gets by selecting the address to decipher to memory set.That is, a plurality of real storage groups are merely able to from a real storage group reading of data of selecting.
In addition, the virtual memory group is the memory set that is formed by one or more real storage groups.It is virtual memory set from system's one side that storer is installed.In general, with this virtual memory group be unit programme or deletion action in read the control of forbidding.That is, in the same period, can on a virtual memory group, carry out programming operation on one side, on other virtual memory groups carry out read operation on one side.
Fig. 4 A is the figure that the structure example of real storage group BNKA among Fig. 3 A～Fig. 3 D and BNKD is shown.Under real storage group BNKA and the BNKD situation below sensor amplifier block 401 is arranged at, has section array 402 in the above.Section array 402 has been arranged two section SEC along the direction (vertical direction) that bit line extends, and has arranged four section SEC along the direction (horizontal direction) that word line extends, thereby has had 8 section SEC0～SEC7.
Fig. 4 B is the figure that the structure example of real storage group BNKB among Fig. 3 A～Fig. 3 D and BNKC is shown.Under real storage group BNKB and the BNKC situation below sensor amplifier block 411 is arranged at, has section array 412 in the above.Section array 412 has been arranged six section SEC along the direction that bit line extends, and has arranged four section SEC along the direction that word line extends, thereby has had 24 section SEC0～SEC23.
These sections SEC is the programming and the least unit of deletion action, can be to each section SEC or simultaneously a plurality of sections are programmed or delete.The bit line length 403 of the section array 402 of Fig. 4 A is two section length.The bit line length 413 of the section array 412 of Fig. 4 B is six section length.That is, the ratio of the stray capacitance in the bit line of section array 402 and section array 412 has 1: 3 poor.In the case, as the access speed of flash memories, the data reading speed in the memory set structure of Fig. 4 B that bit line length is the longest becomes the poorest visit, and Zheng Ti access speed is slack-off thus.
Fig. 5 A～Fig. 5 D is the figure that the structure example of four kinds of flash memories in the present embodiment is shown.The flash memories of Fig. 5 A～Fig. 5 D is respectively the isometric storer of bit line length that makes the flash memories of Fig. 3 A～Fig. 3 D, and with regard to the relation of real storage group and virtual memory group, both are identical.That is, in Fig. 3 A～Fig. 3 D, the length of real storage group BNKA, BNKD on the bit line bearing of trend (vertical direction) is different with the length of real storage group BNKB, BNKC.In Fig. 5 A～Fig. 5 D, the length of the real storage group on the bit line bearing of trend (vertical direction) is all identical with regard to all real storage group BNKA～BNKD.
Among Fig. 5 A, the ratio of the memory capacity of two virtual memory group VBNK1 and VBNK2 is 1: 7.Among Fig. 5 B, the ratio of the memory capacity of two virtual memory group VBNK1 and VBNK2 is 2: 6.Among Fig. 5 C, the ratio of the memory capacity of two virtual memory group VBNK1 and VBNK2 is 4: 4.Among Fig. 5 D, the ratio of the memory capacity of four virtual memory group BNKA～BNKD is 1: 4: 4: 1.
Fig. 6 A is the figure that the structure example of the real storage group BNKA of Fig. 5 A～Fig. 5 D and BNKD is shown.Under real storage group BNKA and the BNKD situation below sensor amplifier block 601 is arranged on, has section array 602 in the above.Section array 602 has been arranged four section SEC along the direction (vertical direction) that bit line extends, and has arranged two section SEC along the direction (horizontal direction) that word line extends, thereby has had 8 section SEC0～SEC7.
Fig. 6 B is the figure that the structure example of the real storage group BNKB of Fig. 5 A～Fig. 5 D and BNKC is shown.Under real storage group BNKB and the BNKC situation below sensor amplifier block 611 is arranged on, has section array 612 in the above.Section array 612 has been arranged four section SEC along the direction that bit line extends, and has arranged six section SEC along the direction that word line extends, thereby has had 24 section SEC0～SEC23.
The bit line length 603 of the section array 602 of Fig. 6 A is four section length.The bit line length 613 of the section array 612 of Fig. 6 B is four section length.That is, the ratio of the stray capacitance in the bit line of section array 602 and section array 612 is identical.Therefore, the access speed of the real storage group of the access speed of the real storage group of Fig. 6 A and Fig. 6 B is identical.Thus, the access speed of flash memories integral body accelerates.
In the flash memories of the real storage group with Fig. 4 A and Fig. 4 B, the poorest access speed is the access speed suitable with the bit line length 413 of six section length of Fig. 4 B.Relative therewith, in the flash memories of the real storage group with Fig. 6 A and Fig. 6 B, the poorest access speed is the access speed suitable with the bit line length 603,613 of four section length of Fig. 6 A and Fig. 6 B, thereby has accelerated.
In addition, the word line length of the real storage group of Fig. 6 A is two section length, and the word line length of the real storage group of Fig. 6 B is six section length, so the ratio of the stray capacitance in each word line is 1: 3.
As mentioned above, according to present embodiment, memory storage has a plurality of memory set, and the bit line of all memory set of a plurality of memory set is isometric.Here, when the bit line of all real storage groups was isometric, the bit line of all virtual memory groups was also isometric.In all memory set of a plurality of memory set, on bit line, connected the storage unit of similar number, and arranged the section of similar number along the direction that bit line extends.Section has a plurality of storage unit, is data deletion unit.For example, as the real storage group BNKB and BNKC of the real storage group BNKA of Fig. 6 A and BNKD and Fig. 6 B, flash memories has the real storage group of two or more different memory sizes at least.
According to present embodiment, because the bit line of all memory set is isometric, so can accelerate the access speed of memory storage integral body.In addition, shown in Fig. 5 A～Fig. 5 D, because the form that can be not limited to as the virtual memory group of the combination of real storage group makes the bit line of all virtual memory groups isometric, so can carry out reading at a high speed.
In addition, being illustrated as an example with flash memories in the above, but being not limited thereto, also can be other storer.Storage unit both can be a Nonvolatile storage unit, also can be volatile memory cell, but preferred Nonvolatile storage unit.
Above-mentioned embodiment only shows and is suitable for implementing object lesson of the present invention, can not explain technical scope of the present invention according to these with limiting.That is, the present invention can implement with various forms in the scope that does not break away from its technical conceive or its principal character.
Industrial applicibility
Because the bit line of all memory set is isometric, so can accelerate the access speed of storage device integral body Degree. In addition, owing to can be not limited to form as the virtual memory group of the combination of real storage group Make the bit line of all virtual memory groups isometric, so can carry out reading of high speed.
Claims (24)
1. a memory storage has a plurality of memory set, wherein
Described each memory set has a plurality of storage unit and a plurality of bit lines that are used for from described a plurality of storage unit reading of data that are used to store data,
The bit line of all memory set of described a plurality of memory set is isometric.
2. memory storage as claimed in claim 1, wherein said a plurality of memory set are merely able to reading of data from a selecteed memory set.
3. memory storage as claimed in claim 1, wherein said memory set are the real storage groups.
4. memory storage as claimed in claim 1, wherein said memory set are the virtual memory groups.
5. memory storage as claimed in claim 3, wherein said each real storage group also has the word line that is used to select described each storage unit.
6. memory storage as claimed in claim 5, wherein said each real storage group also has the word driver that is used for applying to described word line voltage.
7. memory storage as claimed in claim 6, wherein said each real storage group also has the selection circuit, and one or more bit lines that this selection circuit is used for selecting from described a plurality of bit lines are connected to one or more data buss.
8. memory storage as claimed in claim 7, wherein said each real storage group also has one or more sensor amplifiers, and described one or more sensor amplifiers are used to amplify the data that read on described one or more data bus.
9. memory storage as claimed in claim 1 wherein in all memory set of described a plurality of memory set, has connected the storage unit of similar number on described bit line.
10. memory storage as claimed in claim 9 wherein in all memory set of described a plurality of memory set, has been arranged the section of similar number along the direction of described bit line extension.
11. memory storage as claimed in claim 10, wherein said section has a plurality of storage unit, and is data deletion unit.
12. memory storage as claimed in claim 11, wherein said a plurality of memory set are merely able to reading of data from a selecteed memory set.
13. memory storage as claimed in claim 12, wherein said memory set are the real storage groups.
14. memory storage as claimed in claim 13, wherein said each real storage group also has the word line that is used to select described each storage unit.
15. memory storage as claimed in claim 14, wherein said each real storage group also has the word driver that is used for applying to described word line voltage.
16. memory storage as claimed in claim 15, wherein said each real storage group also has the selection circuit, and one or more bit lines that this selection circuit is used for selecting from described a plurality of bit lines are connected to one or more data buss.
17. memory storage as claimed in claim 16, wherein said each real storage group also has one or more sensor amplifiers, and described one or more sensor amplifiers are used to amplify the data that read on described one or more data bus.
18. memory storage as claimed in claim 1, wherein said storage unit is a Nonvolatile storage unit.
19. memory storage as claimed in claim 3, wherein said a plurality of memory set are two or more memory set with different memory sizes at least.
20. memory storage as claimed in claim 19, wherein said real storage group are four real storage groups.
21. memory storage as claimed in claim 20, the memory capacity ratio of wherein said four real storage groups is 1: 3: 3: 1.
22. a memory storage has a plurality of memory set, wherein
Described each memory set has a plurality of storage unit and a plurality of bit lines that are used for from described a plurality of storage unit reading of data that are used to store data,
In all memory set of described a plurality of memory set, connected the storage unit of similar number along described bit line bearing of trend.
23. memory storage as claimed in claim 22 wherein in all memory set of described a plurality of memory set, has been arranged the section of similar number along described bit line bearing of trend, described each section has a plurality of storage unit, and is data deletion unit.
24. memory storage as claimed in claim 22, the bit line of all memory set of wherein said a plurality of memory set is isometric.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2003/002832 WO2004081946A1 (en) | 2003-03-11 | 2003-03-11 | Memory |
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| Publication Number | Publication Date |
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| CN1689117A true CN1689117A (en) | 2005-10-26 |
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| CN03824185.4A Granted CN1689117A (en) | 2003-03-11 | 2003-03-11 | Memory |
| CN03824185.4A Expired - Fee Related CN1689117B (en) | 2003-03-11 | 2003-03-11 | Memory storage |
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| Application Number | Title | Priority Date | Filing Date |
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| CN03824185.4A Expired - Fee Related CN1689117B (en) | 2003-03-11 | 2003-03-11 | Memory storage |
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| JP (1) | JPWO2004081946A1 (en) |
| CN (2) | CN1689117A (en) |
| WO (1) | WO2004081946A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2625277B2 (en) * | 1991-05-20 | 1997-07-02 | 富士通株式会社 | Memory access device |
| JP3487690B2 (en) * | 1995-06-20 | 2004-01-19 | シャープ株式会社 | Nonvolatile semiconductor memory device |
| US6591327B1 (en) * | 1999-06-22 | 2003-07-08 | Silicon Storage Technology, Inc. | Flash memory with alterable erase sector size |
| JP2001084777A (en) * | 1999-09-09 | 2001-03-30 | Hitachi Ltd | Semiconductor memory |
| JP2002329396A (en) * | 2001-04-26 | 2002-11-15 | Fujitsu Ltd | Flash memory whose bank constitution can be modified |
-
2003
- 2003-03-11 CN CN03824185.4A patent/CN1689117A/en active Granted
- 2003-03-11 WO PCT/JP2003/002832 patent/WO2004081946A1/en active Application Filing
- 2003-03-11 CN CN03824185.4A patent/CN1689117B/en not_active Expired - Fee Related
- 2003-03-11 JP JP2004569330A patent/JPWO2004081946A1/en active Pending
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| Publication number | Publication date |
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| WO2004081946A1 (en) | 2004-09-23 |
| JPWO2004081946A1 (en) | 2006-06-15 |
| CN1689117B (en) | 2015-08-12 |
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