CN1776822A - Method and apparatus for programming nonvolatile memory - Google Patents
Method and apparatus for programming nonvolatile memory Download PDFInfo
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- CN1776822A CN1776822A CN 200510071981 CN200510071981A CN1776822A CN 1776822 A CN1776822 A CN 1776822A CN 200510071981 CN200510071981 CN 200510071981 CN 200510071981 A CN200510071981 A CN 200510071981A CN 1776822 A CN1776822 A CN 1776822A
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Abstract
Programming nonvolatile memory cells is affected by the program disturb effect which causes data accuracy issues with nonvolatile memory. Rather than masking the voltage conditions that cause the program disturb effect, voltages are applied to neighboring nonvolatile memory cells, which takes advantage of the program disturb effect to program multiple cells quickly.
Description
Technical field
The invention relates to a kind of nonvolatile storage unit, and particularly relevant for a kind of nonvolatile storage unit that is subjected to programming interference (program disturb).
Background technology
Programming interference effect (program disturb effect) makes the programming operation (program operation) of nonvolatile storage unit complicated.Programming operation is that electric charge is added in the selected storage element in the memory array, perhaps remove electric charge in the selected storage element from memory array, and erase operation for use (erase operation) is that the whole section (sector) of storage element is reset to identical charge storage state.The present invention comprises two kinds of products and method.In first method, programming refers to and makes the net charge that is stored in the charge-trapping structure have current potential more negative or corrigendum.In the second approach, erase refer to make the net charge that is stored in the charge-trapping structure have more negative or the corrigendum current potential.In the programming interference effect, will cause the selected storage element adjacent to selected storage element is produced unwanted programming to the programming of a selected storage element.Especially, the programming interference effect has caused the unwanted programming of following storage element: 1) be positioned at the adjacent column of the row of selected storage element, and 2) storage element (line is the word line that gate voltage (gate voltage) is provided for the storage element of selecting) that is connected with selected line.These problems have had a strong impact on the integrality (integrity) of memory array.
The primary method that interference effect is read in solution is the unwanted program conditions that reduces not selected storage element.Because across the storage element that the unwanted voltage difference on the bit line will cause programming and select, wherein this bit line links to each other with the selected storage element of the adjacent column that is positioned at selected storage element.For example, if the voltage on the bit line is brought up in the time of can programming to the storage element that is positioned at bit line one side, the interference effect of programming this moment trend is to being positioned at the adjacent storage units programming of bit line opposite side.Can stop the unwanted programming to not selected storage element to produce by reducing across the undesired voltage difference on the bit line, wherein the bit line be to link to each other with the not selected storage element of the adjacent column that is positioned at selected storage element.For instance, for being used to the programming process of access adjacent to two bit lines of the row that comprise the storage element of choosing, one of them that puts on this two bits line when a program voltage is with to selected storage
During the deposit receipt metaprogramming, then change voltage on another bit line to reduce unwanted voltage difference.
This kind stops machine-processed potential (underlying) trend of only having covered for program disturb effect, do not stop the potential trend that causes program disturb effect veritably.Because program disturb effect is the intrinsic effect that a kind of a lot of programming mechanism all has, it is useful utilizing program disturb effect to a certain extent, rather than causes the voltage status of program disturb effect and voltage is put on other the bit line just to counteracting.
Summary of the invention
Various embodiment of the present invention is the method about a kind of nonvolatile memory and this memory body of programming.Various embodiments has utilized program disturb effect to being the nonvolatile memory programming of unit with at least two storage elements, rather than just to offsetting program disturb effect voltage is arranged on the bit line.
A kind of construction method of nonvolatile memory array commonly used is that a plurality of storage elements are arranged by row and column.Each storage element comprises a main body, two current terminals that are arranged in main body, and a bottom insulator, one has the charge-trapping structure (each parts has a charge storage state) of the parts that correspond to each current terminal, and a top insulator.
The access of the row of many word line control nonvolatile memory arrays.Each word line provides a gate voltage to the top insulator of the storage element of the particular row that is positioned at a plurality of storage elements.The row of many bit lines these storage elements of access by the current terminal of these storage elements.
According to the storage element of at least two row that are arranged in memory array, but dispose at least three specific bit lines of access storage element, as described below.The first bit line access is positioned at first current terminal of the storage element of first row and secondary series.The second bit line access is positioned at second current terminal of the storage element of first row.The 3rd bit line access is positioned at second current terminal of the storage element of secondary series.In this arrangement mode, the access of same bit line is positioned at first current terminal of the adjacent storage units of adjacent column, and different bit line accesses is positioned at second current terminal of the adjacent storage units of adjacent column.
In one embodiment, programming instruction with electric charge be added to first row in a storage element and the storage element in secondary series.One voltage is applied on the bit line, and this bit line provides gate voltage for being arranged in first storage element that is listed as and the storage element of secondary series at least.This gate voltage enough moves on to charge-trapping structure by bottom insulator with energetic charges from the main body of storage element.For instance, if energetic charges with electric current mechanism (for example, CHISEL, CHE, the Fowler-Nordheim channelling effect, when band-band hot hole channelling effect (band-to-band hothole tunneling)) attracteding in the main body of storage element, gate voltage is enough to be used for removing this energetic charges so.Voltage puts on the first bit line, and this bit line access and programming are arranged in the storage element of at least the first row and secondary series.This voltage with energetic charges (for example is enough to be used for, by CHISEL, CHE, the Fowler-Nordheim channelling effect, band-band hot hole channelling effect (band-to-band hot hole tunneling)) be introduced in the main body of the storage element that has enough at least voltage differences between the current terminal.At last, a voltage is set in the second bit line and the 3rd bit line, these bit lines are remaining bit lines, but access and programming are arranged in the storage element of at least the first row and secondary series.This voltage setting can cause: with for simplicity, identical voltage is applied on the second bit line and the 3rd bit line, perhaps with elasticity flexibly for the purpose of, different voltage is applied on the second bit line and the 3rd bit line.This voltage is provided with at least one enough voltage differences between the current terminal of storage element that will cause at least the first row and secondary series, with the energetic charges of the main body of the storage element that attracts to be arranged in storage element (for example, by CHISEL, CHE, the Fowler-Nordheim channelling effect, band-band hot hole channelling effect (band-to-band hot hole tunneling)).Because this enough voltage difference and can successfully energetic charges being introduced in the storage element main body makes this gate voltage and the voltage that puts on the first bit line electric charge can be added in the storage element.
In another embodiment, programming instruction is on the storage element that electric charge is not added in first row and on the storage element in secondary series.This voltage setting can not cause the enough voltage differences between the current terminal of storage element in first row and secondary series, so that can not attract the energetic charges in the main body of storage element; Rather than voltage is arranged in the second bit line and the 3rd bit line, with the enough voltage differences between the current terminal that causes the storage element in first row and secondary series, and attract energetic charges in the main body of storage element.Because this not enough voltage difference can not attract energetic charges in the main body of storage element, this gate voltage and the voltage that puts on the first bit line will can not increase electric charge in storage element.
In another embodiment,, and set the voltage on the second bit line and the 3rd bit line, comprising according to programming instruction as follows:
A) if programming instruction is when electric charge is joined the charge-trapping structure of the storage element that is arranged in first row and secondary series, then set the voltage on the second and the 3rd bit line, to cause the enough at least voltage differences between the current terminal of storage element, first of storage element is listed as and the energetic charges of the main body of secondary series so that attract to be arranged in;
B) if when programming instruction does not join electric charge the charge-trapping structure that is arranged in first row and the storage element of secondary series, then set the voltage on the second and the 3rd bit line, and can not cause enough voltage differences between current terminal, so that can not attract to be arranged in the energetic charges of the main body of first row of storage element and secondary series;
C) if programming instruction is the charge-trapping structure that electric charge is joined at least one storage element that is arranged in first row, rather than when electric charge joined the charge-trapping structure of at least one storage element that is arranged in secondary series, voltage then is set in causing on the second and the 3rd bit line: 1) the enough at least voltage differences between the current terminal in first row of storage element, with the energetic charges of the main body of first row that attract to be arranged in storage element; And 2) voltage difference of the deficiency between current terminal in the secondary series of storage element, and can not attract to be arranged in the energetic charges of main body of the secondary series of storage element; And
D) if programming instruction is the charge-trapping structure that electric charge is not joined at least one storage element that is arranged in first row, and electric charge can be joined the charge-trapping structure of at least one storage element that is arranged in secondary series the time, voltage then is set in causing on the second and the 3rd bit line: the 1) voltage difference of deficiency between the current terminal in first row of storage element, and can not attract to be arranged in the energetic charges of main body of first row of storage element; And 2) the enough at least voltage differences between the current terminal in the secondary series of storage element are with the energetic charges of the main body of the secondary series that attracts to be arranged in storage element.
Various embodiment have been contained the programmed method and the integrated circuit relevant with the nonvolatile memory array of storage element.
The present invention not only comprises simultaneously two storage elements is programmed, and more comprises three or more storage elements are programmed.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 illustrates the synoptic diagram into a kind of part of nonvolatile storage cellular array, and it has shown on adjacent storage element increases electric charge.
Fig. 2 illustrates the synoptic diagram into a kind of part of nonvolatile storage cellular array, and it is not shown on the adjacent storage element increases electric charge.
Fig. 3 illustrates the synoptic diagram into a kind of part of nonvolatile storage cellular array, and it carries out a decoding programming instruction, to increase or not increase electric charge in adjacent storage element.
Fig. 4 illustrates the more detailed synoptic diagram into a kind of adjacent nonvolatile storage unit, and it has shown on adjacent storage element increases electric charge.
Fig. 5 illustrates the more detailed synoptic diagram into a kind of adjacent nonvolatile storage unit, and it is not presented on the adjacent storage element increases electric charge.
Fig. 6 illustrates the calcspar into a kind of according to an embodiment of the invention nonvolatile memory array, its a plurality of storage elements able to programme.
110: word line WL
N-1
112: word line WL
N
114: word line WL
N+1
120,121,122,123,124,125 and 126: the nonvolatile storage unit
130: bit line BL
M-1
131: bit line BL
M
132: bit line BL
M+1
410: gate
420,421: the top insulation system
430,431: the charge-trapping structure
435,436: electric hole
440,441: the bottom insulation structure
450,460,470:n type doping current terminal
490,491:P type doping basal area
600: charge-trapping storage element array
601: line decoder
602: word line
603: column decoder
604: the bit line
606: induction amplifier and data input structure
607: data bus
608: bias voltage measure supply voltage
609: bias voltage measure stater
610: DOL Data Output Line
611: Data In-Line
660: integrated circuit
670: bus
Embodiment
Fig. 1 is the synoptic diagram of the partial array of a nonvolatile storage unit.Word line WL
N-1110 row to nonvolatile storage unit 120 and 121 provide the critical voltage of 0V.Word line WL
N112 row to nonvolatile storage unit 122 and 123 provide-critical voltage of 5V.Word line WL
N+1114 row to nonvolatile storage unit 124 and 125 provide the critical voltage of 0V.Bit line BL
M131 provide 5V voltage to first current terminal of first row of storage element 120,122 and 124 and first current terminal of the secondary series of storage element 121,123 and 125.Bit line BL
M+1132 first second current terminals (currentterminal) that are listed as to storage element 120,122 and 124 provide 0V voltage.Bit line BL
M-1130 second current terminals to the secondary series of storage element 121,123 and 125 provide 0V voltage.The charge storage state of nonvolatile storage unit 122 and 123 charge storing structure is a programmingization.Nonvolatile storage unit 120,121, the charge storage state of 124 and 126 charge storing structure is not programmed, and this is because inadequate 1 critical voltage can't be moved into the energetic charges that is across in the main body of nonvolatile storage unit of bottom insulator in the charge-trapping structure.Each nonvolatile storage unit 120,121,122,123,124 has and the corresponding parts of different current terminals with 125 charge-trapping structure.In nonvolatile storage unit 122,123, electric charge is added in the charge-trapping structure via band-band hot hole (band-to-band hot holes).More particularly, by bit line BL
M131 join electric charge in the charge-trapping structure.This programming has simultaneously to nonvolatile storage unit 122 and 123 speed advantages of programming.
Fig. 2 is the synoptic diagram of the partial array of a nonvolatile storage unit.In Fig. 2, bit line BL
M+1132 first second current terminals that are listed as to storage element 120,122 and 124 provide 3V voltage.Bit line BL
M-1130 second current terminals to the secondary series of storage element 121,123 and 125 provide 3V voltage.Although critical voltage is not enough to move the energetic charges be arranged in across the main body of the nonvolatile storage unit 122 of bottom insulator and 123 to the charge-trapping structure, nonvolatile storage unit 122 and 123 is not programmed. Nonvolatile storage unit 122 and 123 is not programmed former because: be positioned at bit line BL
M+1132 and bit line BL
MVoltage difference between 131 is too little for the row of nonvolatile storage unit 120,122 and 124; Be positioned at bit line BL
M-1130 and bit line BL
MVoltage difference between 131 is too little for the row of nonvolatile storage unit 121,123 and 125.Voltage difference between a pair of bit line is not enough to attract energetic charges on the main body of storage element.The advantage of this programming is: if the bit line of another one storage element is grounded, this programming can remain in bit line BL
MBias voltage on 131, it can sufficiently attract the energetic charges in the main body of nonvolatile storage unit, but neither to 122 programmings of nonvolatile storage unit, also to 123 programmings of nonvolatile storage unit.
Fig. 3 is the synoptic diagram of the partial array of a nonvolatile storage unit.Word line WL
N-1110 row to nonvolatile storage unit 120 and 121 provide V
N-1Critical voltage.Word line WL
N112 row to nonvolatile storage unit 122 and 123 provide V
NCritical voltage.Word line WL
N+1114 row to nonvolatile storage unit 124 and 125 provide V
N+1Critical voltage.Bit line BL
M131 provide V to first current terminal of first row of storage element 120,122 and 124 and first current terminal of the secondary series of storage element 121,123 and 125
MVoltage.Bit line BL
M+1132 first second current terminals that are listed as to storage element 120,122 and 124 provide V
M+1Voltage.Bit line BL
M-1130 second current terminals to the secondary series of storage element 121,123 and 125 provide V
M-1Voltage.
The nonvolatile memory array of Fig. 3 is to voltage V
N-1, V
N, V
N+1, V
M+1, V
M, V
M-1Adopt following voltage and voltage setting.
| By bit line BL
MCharge-trapping structural detail to |
By other bit line BL
M+1/BL
M-1Charge-trapping structural detail to |
V M+1 | V M | V M-1 | V N-1 | V N | V N+1 | |
| Be | Be | |
5V | 0V | 0V | -5V | 0V | |
| Be | Not | | 5V | 3V | 0V | -5V | 0V | |
| Not | Be | |
5V | 0V | 0V | -5V | 0V | |
| Not | Not | | 5V | 3V | 0V | -5V | 0V | |
| 0V | 0V | 0V | 0V | -5V | 0V |
Fig. 4 is the synoptic diagram of the charge-trapping storage element of 2 shared word lines and a bit line, and it has shown that one is carried out programming operation by shared bit line on the charge-trapping structure of each non-volatile cell of part.P type doping basal area 490 or 491 comprises n type doping current terminal 450,460 and 470.N type doping current terminal 460 is first current terminals of two storage elements.The remainder of first storage element comprises one and is positioned at suprabasil bottom insulation structure 440, a charge-trapping structure 430 that is positioned on the bottom insulation structure 440 (bottom oxide), a top insulation system 420 (top oxide) that is positioned on the charge-trapping structure 430, and a gate 410 that is positioned on the oxide structure 420.The remainder of second storage element comprises one and is positioned at suprabasil insulation system 441, a charge-trapping structure 431 that is positioned on the bottom insulation structure 441 (bottom oxide), a top insulation system 421 (top oxide) that is positioned on the charge-trapping structure 431, and a gate 410 that is positioned on the oxide structure 421.Gate 410 is actually the word line that an oxide structure 420 to the oxide structure 420 of first storage element and second storage element provides gate voltage.Representative top insulator comprises silicon dioxide and has how rice (nanometers) thick silicon oxynitride (silicon oxynitride) of 5-10, or other similar high dielectric constant materials alundum (Al for example.Representative bottom insulator comprises silicon dioxide and has the how thick silicon oxynitride of rice of 3-10, or other similar high dielectric constant materials.Representative charge-trapping structure comprises that thickness is the how silicon nitride of rice of 3-9, or other similar high dielectric constant materials comprises metal oxide such as alundum (Al, hafnium oxide and other material.The charge-trapping structure can be a cover discrete capsule (pocket) or have the particle of charge-trapping material, perhaps continuous layer as shown in the figure.
For example, PHINES type storage element has the how bottom oxide of rice of a thickness 2-10, and a thickness 2-10 is the electric charge capture layer of rice how, and the thickness 2-15 top oxide of rice how.
In certain embodiments, gate comprises the material of a working function (work function) greater than the intrinsic working function of n type silicon, or bigger than about 4.1eV, is preferably greatlyyer than about 4.25eV, and it comprises for example big than about 5eV.Representational gate material has P type polysilicon (poly), titanium nitride, and platinum, and other has the metal and the material of high workload function.Other material that the high workload function is arranged that is suitable for the embodiment of present technique comprises metal, metal alloy and metal nitride, wherein metal is including but not limited to ruthenium, iridium, nickel, cobalt, and metal alloy includes, but are not limited to ruthenium/titanium alloy and nickel/titanium alloys, and metal oxide includes, but are not limited to ruthenic oxide.Compared to general n type polycrystalline silicon gate pole, the gate material of high workload function will produce higher injection barrier (injection barrier) to electron channel.With the injection barrier about 3.15eV of silicon dioxide as the material of the n type polycrystalline silicon gate pole of top insulator.Therefore, in the embodiment of present technique, the material that is used as gate and top insulator has the injection barrier that is higher than about 3.15eV, and it for example is higher than about 3.4eV, wherein is preferably than about 4eV height.Concerning with silicon dioxide as the P type polycrystalline silicon gate pole of top insulator, it injects the about 4.25eV of barrier, and the critical value as a result of its convergence unit (convergedcell) (resulting threshold) is with respect to having reduced about 2 volts with silicon dioxide as the n type polycrystalline silicon gate pole of top insulator.
In Fig. 4, the charge-trapping structure division of current terminal 460 each unit of programming of each storage element, it for example injects (band-band hothole injection) in charge-trapping structure 430 and 431 via electric hole 435 and 436 band-band hot holes.Other programming and the technology of erasing can be used to as United States Patent (USP) the 6th, 690, described in No. 601, also can adopt other storage element and other operation rule in the operation rule that PHINES type storage element adopted.
Fig. 5 is the synoptic diagram of the charge-trapping storage element of two common word line and bit line.Even change the setting of voltage, without any being programmed of storage element.Even be applied to bias voltage on the bit line 460 because of the time enough greatly with the energetic charges in the main body 490 and 491 of the nonvolatile storage unit that attracts on another bit line, to have relevant voltage, and other bit line 450 and 470 in bit line centering because of having inadequate voltage difference, so can't attract to be arranged in the main body 490 of nonvolatile storage unit and 491 energetic charges.
Fig. 6 is the simplification calcspar of a kind of integrated circuit of one embodiment of the invention.Integrated circuit 660 comprises a memory array 600, and this memory array 600 uses carries out its operation at the suprabasil charge-trapping storage element of semiconductor.One line decoder 601 be coupling in a plurality of word lines 602, wherein these word lines 602 are to arrange along the row in memory array 600.One column decoder 603 be coupling in a plurality of bit lines 604, wherein these bit lines 604 are to arrange along the row in memory array 600.Address offers column decoder 603 and line decoder 601 by bus 670.Induction amplifier in square 606 and data input structure by data bus 607 and coupling in column decoder 603.Data are by the I/O end of Data In-Line 611 from the integrated circuit 660, or are input to integrated circuit 660 and the data input structure square 606 from other inside or outside data source.Data output to I/O end on the integrated circuit 660 by the induction amplifier of DOL Data Output Line 610 from square 606, or inside or outside data destination to other integrated circuit 660.The application of bias voltage measure stater 609 control bias voltage measure supply voltages 608, verification of for example erasing (erase verify) and programming calibration voltage reach the programming of a plurality of selected unit, the measure of reading and erasing of storage element.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (42)
1, a kind of programmed method of storage element, it is characterized in that its be suitable for programming one first storage element and one second storage element, and this first storage element and this second storage element have a main body separately, one first current terminal in this main body and one second current terminal, one gate terminal, one top insulator, the charge-trapping structure and the bottom insulator that have the parts that correspond to this first current terminal and this second current terminal, wherein the gate of this first storage element and this second storage element is coupled to an identical word line, and those first current terminals of this first storage element and this second storage element are coupled to an identical bit line, and those second current terminals of this first storage element and this second storage element are coupled to different bit lines, and the programmed method of this storage element comprises:
Respond a programming instruction, and add electric charge to this charge-trapping structure of this first storage element and this second storage element at least, comprising:
Apply one first voltage to this identical word line, enough energetic charges is moved in this charge-trapping structure by this bottom insulator from this main body of those storage elements;
Apply one second voltage to this identical bit line, and allow energetic charges in the main body of those storage elements have at least one enough voltage differences between this first current terminal and this second current terminal; And
One voltage is set on different bit lines,, is arranged in the energetic charges of those main bodys of this first storage element and this second storage element with attraction to cause this enough voltage difference at least between this first current terminal and this second current terminal.
2, the programmed method of storage element according to claim 1 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the secondary charges that passage brings out.
3, the programmed method of storage element according to claim 1 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the passage hot charge.
4, the programmed method of storage element according to claim 1 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by the Fowler-Nordheim channelling effect.
5, the programmed method of storage element according to claim 1 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by band-tape channel effect.
6, the programmed method of storage element according to claim 1 is characterized in that wherein said voltage setting is that different bit lines is applied an identical voltage.
7, the programmed method of storage element according to claim 1 is characterized in that wherein said voltage setting is that different bit lines is applied different voltage.
8, a kind of programmed method of storage element, it is characterized in that its be suitable for programming one first storage element and one second storage element, and this first storage element and this second storage element have a main body separately, one first current terminal in this main body and one second current terminal, one gate terminal, one top insulator, the charge-trapping structure and the bottom insulator that have the parts that correspond to this first current terminal and this second current terminal, wherein the gate of this first storage element and this second storage element is coupled to an identical word line, and those first current terminals of this first storage element and this second storage element are coupled to an identical bit line, and those second current terminals of this first storage element and this second storage element are coupled to different bit lines, and the programmed method of this storage element comprises:
Respond a programming instruction, and electric charge do not added to this charge-trapping structure of this first storage element and this second storage element at least, comprising:
Apply one first voltage to this identical word line, enough energetic charges is moved in this charge-trapping structure by this bottom insulator from this main body of those storage elements;
Apply one second voltage to this identical bit line, and allow energetic charges in the main body of those storage elements have at least one enough voltage differences between this first current terminal and this second current terminal; And
One voltage is set on different bit lines, makes voltage difference between this first current terminal and this second current terminal be not enough to attract be arranged in the energetic charges of those main bodys of this first storage element and this second storage element.
9, the programmed method of storage element according to claim 8 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the secondary charges that passage brings out.
10, the programmed method of storage element according to claim 8 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the passage hot charge.
11, the programmed method of storage element according to claim 8 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by the Fowler-Nordheim channelling effect.
12, the programmed method of storage element according to claim 8 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by band-tape channel effect.
13, the programmed method of storage element according to claim 8 is characterized in that wherein said voltage setting is that different bit lines is applied an identical voltage.
14, the programmed method of storage element according to claim 8 is characterized in that wherein this voltage setting is that different bit lines is applied different voltage.
15, a kind of programmed method of storage element, it is characterized in that its be suitable for programming one first storage element and one second storage element, and this first storage element and this second storage element have a main body separately, one first current terminal in this main body and one second current terminal, one gate terminal, one top insulator, the charge-trapping structure and the bottom insulator that have the parts that correspond to this first current terminal and this second current terminal, wherein the gate of this first storage element and this second storage element is coupled to an identical word line, and those first current terminals of this first storage element and this second storage element are coupled to an identical bit line, and those second current terminals of this first storage element and this second storage element are coupled to different bit lines, and the programmed method of this storage element comprises:
Respond a programming instruction, comprising:
Apply one first voltage to this identical word line, enough energetic charges is moved in this charge-trapping structure by this bottom insulator from this main body of those storage elements;
Apply one second voltage to this identical bit line, and allow energetic charges in the main body of those storage elements have at least one enough voltage differences between this first current terminal and this second current terminal; And
According to this programming instruction as follows, and a voltage is set on different bit lines, comprises:
If this programming instruction is when electric charge is joined this charge-trapping structure of those storage elements that are arranged in one first row and a secondary series, voltage then is set on one second bit line and one the 3rd bit line, causing this enough voltage difference at least between this first current terminal and this second current terminal, so that attract to be arranged in the energetic charges of the main body of this first row of those storage elements and this secondary series;
When if this programming instruction does not join electric charge this charge-trapping structure of those storage elements that are arranged in these first row and this secondary series, voltage then is set on this second bit line and the 3rd bit line, the enough voltage differences between this first current terminal and this second current terminal can not be caused, and the energetic charges of the main body of this first row of those storage elements and this secondary series can not be attracted to be arranged in;
If this programming instruction is this charge-trapping structure that electric charge is joined at least one storage element that is arranged in these first row, rather than when electric charge being joined this charge-trapping structure of at least one storage element that is arranged in this secondary series, voltage then is set in causing on this second bit line and the 3rd bit line: 1) this enough voltage difference at least between this first current terminal in this first storage element and this second current terminal, be arranged in the energetic charges of this first main body that is listed as of those storage elements with attraction, and 2) voltage difference of this first current terminal in this second storage element and the deficiency between this second current terminal, and can not attract to be arranged in the energetic charges of main body of this secondary series of those storage elements; And
If this programming instruction is this charge-trapping structure that electric charge can not be joined at least one storage element that is arranged in these first row, and electric charge can be joined this charge-trapping structure of at least one storage element that is arranged in this secondary series the time, voltage then is set in causing on this second bit line and the 3rd bit line: the 1) voltage difference of this first current terminal in this first storage element and the deficiency between this second current terminal, and can not attract to be arranged in the energetic charges of main body of these first row of those storage elements, and 2) this first current terminal in this second storage element and the enough at least voltage differences between this second current terminal are with the energetic charges of the main body of this secondary series of attracting to be arranged in those storage elements.
16, the programmed method of storage element according to claim 15 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the secondary charges that passage brings out.
17, the programmed method of storage element according to claim 15 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the passage hot charge.
18, the programmed method of storage element according to claim 15 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by the Fowler-Nordheim channelling effect.
19, the programmed method of storage element according to claim 15 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by band-tape channel effect.
20, the programmed method of storage element according to claim 15 is characterized in that wherein this voltage setting is that different bit lines is applied an identical voltage.
21, the programmed method of storage element according to claim 15 is characterized in that wherein this voltage setting is that different bit lines is applied different voltage.
22, a kind of nonvolatile memory is characterized in that it comprises:
One storage element array is by rows, comprises at least one first row and most row, and wherein those row comprise at least one first row and secondary series, and each storage element comprises:
One main body;
One first current terminal is arranged in this main body;
One second current terminal is arranged in this main body;
One bottom insulator, idol is connected to this main body;
One charge-trapping structure, idol is connected to this bottom insulator, and this charge-trapping structure has most parts that correspond to this source first current terminal and this second current terminal, and each those parts has a charge storage state; And
One top insulator, idol is connected to this charge-trapping structure;
Most bar word lines, be coupled to those top insulator in those storage elements, and those word lines comprise at least one first word line, and wherein most storage elements in first row of this in this storage element array obtain coming from a gate voltage of this first word line;
Most bar bit lines be coupled to this first current terminal and this second current terminal in this storage element array, and those bit lines comprise:
One first bit line is coupled to this first current terminal of those storage elements in these first row and this secondary series;
One second bit line is coupled to this second current terminal of those storage elements in these first row; And
One the 3rd bit line is coupled to this second current terminals of those storage elements in this secondary series; And
One logic, idol is connected to those storage elements, by a following majority step, makes this logic respond a programming instruction, and electric charge is joined this charge-trapping structure that is arranged in these first row and those storage elements at least of this secondary series, and those steps comprise:
Apply one first voltage to this first word line, enough energetic charges is moved in this charge-trapping structure by this bottom insulator from this main body of those storage elements;
Apply one second voltage to this first bit line, and allow energetic charges in the main body of those storage elements have at least one enough voltage differences between this first current terminal and this second current terminal; And
One voltage is set on this second bit line and the 3rd bit line, causing this enough voltage difference at least between this first current terminal and this second current terminal, with the energetic charges of those main bodys of those first row of attracting to be arranged in those storage elements and those secondary series.
23, nonvolatile memory according to claim 22 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the secondary charges that passage brings out.
24, nonvolatile memory according to claim 22 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the passage hot charge.
25, nonvolatile memory according to claim 22 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by the Fowler-Nordheim channelling effect.
26, nonvolatile memory according to claim 22 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by band-tape channel effect.
27, nonvolatile memory according to claim 22 is characterized in that wherein said voltage setting is that different bit lines is applied an identical voltage.
28, nonvolatile memory according to claim 22 is characterized in that wherein said voltage setting is that different bit lines is applied different voltage.
29, a kind of nonvolatile memory is characterized in that it comprises:
One storage element array is by rows, comprises at least one first row and most row, and wherein those row comprise at least one first row and secondary series, and each storage element comprises:
One main body;
One first current terminal is arranged in this main body;
One second current terminal is arranged in this main body;
One bottom insulator, idol is connected to this main body;
One charge-trapping structure, idol is connected to this bottom insulator, and this charge-trapping structure has most parts that correspond to this source first current terminal and this second current terminal, and each those parts has a charge storage state; And
One top insulator, idol is connected to this charge-trapping structure;
Most bar word lines, be coupled to those top insulator in those storage elements, and those word lines comprise at least one first word line, and wherein most storage elements in first row of this in this storage element array obtain coming from a gate voltage of this first word line;
Most bar bit lines be coupled to this first current terminal and this second current terminal in this storage element array, and those bit lines comprise:
One first bit line is coupled to this first current terminal of those storage elements in these first row and this secondary series;
One second bit line is coupled to this second current terminal of those storage elements in these first row; And
One the 3rd bit line is coupled to this second current terminals of those storage elements in this secondary series; And
One logic, idol is connected to those storage elements, by a following majority step, makes this logic respond a programming instruction, and electric charge is not joined this charge-trapping structure that is arranged in these first row and those storage elements at least of this secondary series, and those steps comprise:
Apply one first voltage to identical word line, be moved into this charge-trapping structure by this bottom insulator with the energetic charges of this main body that enough will be arranged in those storage elements;
Apply one second voltage to this first bit line, and allow energetic charges in the main body of those storage elements have at least one enough voltage differences between this first current terminal and this second current terminal; And
One voltage is set on this second bit line and the 3rd bit line, makes voltage difference between this first current terminal and this second current terminal be not enough to attract be arranged in the energetic charges of those main bodys of this first storage element and this second storage element.
30, nonvolatile memory according to claim 29 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the secondary charges that passage brings out.
31, nonvolatile memory according to claim 29 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the passage hot charge.
32, nonvolatile memory according to claim 29 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by the Fowler-Nordheim channelling effect.
33, nonvolatile memory according to claim 29 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by band-tape channel effect.
34, nonvolatile memory according to claim 29 is characterized in that wherein said voltage setting is that different bit lines is applied an identical voltage.
35, nonvolatile memory according to claim 29 is characterized in that wherein said voltage setting is that different bit lines is applied different voltage.
36, a kind of nonvolatile memory is characterized in that it comprises:
One storage element array is by rows, comprises at least one first row and most row, and wherein those row comprise at least one first row and secondary series, and each storage element comprises:
One main body;
One first current terminal is arranged in this main body;
One second current terminal is arranged in this main body;
One bottom insulator, idol is connected to this main body;
One charge-trapping structure, idol is connected to this bottom insulator, and this charge-trapping structure has most parts that correspond to this source first current terminal and this second current terminal, and each those parts has a charge storage state; And
One top insulator, idol is connected to this charge-trapping structure;
Most bar word lines, be coupled to those top insulator in those storage elements, and those word lines comprise at least one first word line, and wherein most storage elements in first row of this in this storage element array obtain coming from a gate voltage of this first word line;
Most bar bit lines be coupled to this first current terminal and this second current terminal in this storage element array, and those bit lines comprise:
One first bit line is coupled to this first current terminal of those storage elements in these first row and this secondary series;
One second bit line is coupled to this second current terminal of those storage elements in these first row; And
One the 3rd bit line is coupled to this second current terminals of those storage elements in this secondary series; And
One logic, idol is connected to those storage elements, by a following majority step, make this logic respond a programming instruction, and those steps comprises:
Apply one first voltage to this first word line, enough energetic charges is moved in this charge-trapping structure by this bottom insulator from this main body of those storage elements;
Apply one second voltage to this first bit line, and allow energetic charges in the main body of those storage elements have at least one enough voltage differences between this first current terminal and this second current terminal; And
According to this programming instruction as follows, and a voltage is set on different bit lines, comprises:
If this programming instruction is when joining electric charge in this charge-trapping structure of one first storage element and one second storage element, then applying voltage is arranged on the different bit lines, to cause this enough voltage difference at least between this first current terminal and this second current terminal, so that attraction is arranged in the energetic charges of those main bodys of this first storage element and this second storage element;
When if this programming instruction does not join electric charge in this charge-trapping structure of this first storage element and this second storage element, then applying voltage is arranged on the different bit lines, the enough voltage differences between this first current terminal and this second current terminal can not be caused, and the energetic charges of those main bodys of this first storage element and this second storage element can not be attracted to be arranged in;
If this programming instruction is that electric charge is joined in this charge-trapping structure of this first storage element, rather than when electric charge being joined in this charge-trapping structure of this second storage element, voltage then is set in causing on the different bit lines: 1) this enough voltage difference at least between this first current terminal in this first storage element and this second current terminal, be arranged in the energetic charges of this main body of this first storage element with attraction, and 2) voltage difference of this first current terminal in this second storage element and the deficiency between this second current terminal, and can not attract to be arranged in the energetic charges of this main body of this second storage element; And
If this programming instruction is electric charge can not be joined in this charge-trapping structure of this first storage element, and electric charge can be joined in this charge-trapping structure of this second storage element the time, voltage then is set in causing on the different bit lines: the 1) voltage difference of this first current terminal in this first storage element and the deficiency between this second current terminal, and can not attract to be arranged in the energetic charges of this main body of this first storage element, and 2) this first current terminal in this second storage element and the enough at least voltage differences between this second current terminal are with the energetic charges of this main body of attracting to be arranged in this second storage element.
37, nonvolatile memory according to claim 36 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the secondary charges that passage brings out.
38, nonvolatile memory according to claim 36 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is the passage hot charge.
39, nonvolatile memory according to claim 36 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by the Fowler-Nordheim channelling effect.
40, nonvolatile memory according to claim 36 is characterized in that wherein being caused by this enough voltage and the energetic charges that is moved in this charge-trapping structure is brought out by band-tape channel effect.
41, nonvolatile memory according to claim 36 is characterized in that wherein said voltage setting is that different bit lines is applied an identical voltage.
42, nonvolatile memory according to claim 36 is characterized in that wherein said voltage setting is that different bit lines is applied different voltage.
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| Application Number | Priority Date | Filing Date | Title |
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| US62973504P | 2004-11-19 | 2004-11-19 | |
| US60/629,735 | 2004-11-19 | ||
| US11/064,316 | 2005-02-23 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256836B (en) * | 2007-02-28 | 2012-11-07 | 三星电子株式会社 | Method of operating nonvolatile memory device |
| CN101573763B (en) * | 2006-11-07 | 2014-03-12 | 桑迪士克Il有限公司 | Programming NAND flash memory with reduced program disturb |
| CN106057239A (en) * | 2016-05-27 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | Programming operation method for flash memory array |
| CN106531216A (en) * | 2015-09-11 | 2017-03-22 | 株式会社东芝 | Memory system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003346489A (en) * | 2002-05-24 | 2003-12-05 | Mitsubishi Electric Corp | Semiconductor storage device |
| JP2004079602A (en) * | 2002-08-12 | 2004-03-11 | Fujitsu Ltd | Nonvolatile memory having trap layer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101573763B (en) * | 2006-11-07 | 2014-03-12 | 桑迪士克Il有限公司 | Programming NAND flash memory with reduced program disturb |
| CN101256836B (en) * | 2007-02-28 | 2012-11-07 | 三星电子株式会社 | Method of operating nonvolatile memory device |
| CN106531216A (en) * | 2015-09-11 | 2017-03-22 | 株式会社东芝 | Memory system |
| CN106057239A (en) * | 2016-05-27 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | Programming operation method for flash memory array |
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| CN100449646C (en) | 2009-01-07 |
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