CN1689117B - Memory storage - Google Patents
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- CN1689117B CN1689117B CN03824185.4A CN200380241854A CN1689117B CN 1689117 B CN1689117 B CN 1689117B CN 200380241854 A CN200380241854 A CN 200380241854A CN 1689117 B CN1689117 B CN 1689117B
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- 230000005055 memory storage Effects 0.000 title claims abstract description 19
- 230000015654 memory Effects 0.000 claims abstract description 153
- 238000012217 deletion Methods 0.000 claims description 10
- 230000037430 deletion Effects 0.000 claims description 10
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 101100420730 Mus musculus Sec23a gene Proteins 0.000 description 2
- 101150080918 SEC23 gene Proteins 0.000 description 2
- 101100365194 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SEC7 gene Proteins 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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Abstract
Memory storage has multiple memory set (BNKA, BNKB, BNKC, BNKD), and each memory set has the multiple storage unit for storing data and the multiple bit lines for reading data from described multiple storage unit.The bit line of all memory set of multiple memory set is isometric.
Description
Technical field
The present invention relates to memory storage, particularly relate to the memory storage with multiple memory set.
Background technology
Flash memories has non-volatile memory cells, and in units of the section with multiple storage unit, carry out data deletion and data write.The operator scheme of flash memories comprises: read mode, the data of the one or more storage unit selected by reading; Puncturing pattern, to all storage unit write data " 1 " in selected section; Programming (write) pattern, to selected one or more storage unit write data " 0 ".
In addition, in above-mentioned programming mode and puncturing pattern, the stress that the oriented storage unit with floating boom applies constant noble potential applies step, and after this checks the checking procedure of change of threshold voltage of storage unit, and repeats to proceed to till desired data are written into.Namely, in programming mode, positive high voltage is applied to control gate, thus inject electronics to floating boom, until reach the threshold voltage of more than certain value, in puncturing pattern, apply as back-biased positive high voltage to substrate-side, thus draw electronics, until reach the threshold voltage of below certain value from floating boom.Therefore, in flash memories, when the section in a certain memory set is in programming or deletion action, even the storage unit of other sections in this memory set also forbids read operation.
In addition, because programming and deletion action need for a long time compared with read operation, so when starting programming or deletion action to a certain memory set, the storage area that can read tails off, and the restriction of read operation occurs thus.
In order to reduce these restrictions, need the flash memories of multi-memory group structure.That is, by increasing the quantity of memory set, the capacity owing to just carrying out the storer programmed or delete and cannot access can be reduced.
And, as another feature, even if flash memories is the nonvolatile memory that also can keep storing data under the state of power cutoff, so the situation of the semiconductor memory of the boot of accessing at first when being used as being recorded in and starting power supply is more.Thereupon, flash memories is usually made up of the memory set of the memory set with the guiding segments accessed when starting power supply with the common section had in addition.
Now, according to the size etc. of boot, need the memory set structure corresponding to the purposes of user, such as, there is the flash memories etc. of the capacity of the memory set of guiding segments flash memories little compared with the capacity of other memory set or equal capacity.
As the method meeting these two kinds of demands simultaneously, propose have the combination by changing multiple real storage group by the kind of flash memories to form the combination of multiple virtual memory group, thus meet the method for multiple needs.
Like this, in order to reduce the capacity owing to carrying out the storer programmed or delete and cannot access in flash memories, generally mostly be the structure based on multi-memory group, and, in order to correspond to multiple use, carry the function that can change combination by kind, to allow to the ratio freely designing the capacity of the memory set with guiding segments and the capacity of other memory set.
Here, can carry out freely designing and refer to such as when four real storage groups (volume ratio 1: 3: 3: 1), realize the combination of the multiple virtual memory group of the virtual memory group (volume ratio 1: 7,2: 6,4: 4) of two groups or the virtual memory group (volume ratio 1: 3: 3: 1) of four groups.But with regard to the structure example of virtual memory group, the shape of each memory set is different, and bitline length often deviation occurs.
In general flash memories, convert the small area analysis in memory cell transistor to current potential, and read by comparing with reference potential, but bit line long time, for also larger by the stray capacitance of bit line selected, thus current potential conversion is slack-off, therefore with regard to obtaining the poor current potential being enough to compare with reference potential, spended time.That is, this means that the digital independent in the virtual memory group combination that bitline length is the longest becomes the poorest access.
Summary of the invention
The object of this invention is to provide a kind of structure that can be not limited to virtual memory group to realize the memory storage of best reading speed.
According to a design of the present invention, a kind of memory storage with multiple memory set can be provided.Each memory set has the multiple storage unit for storing data, and for reading multiple bit lines of data from multiple storage unit.The bit line of all memory set of multiple memory set is isometric, and wherein said memory set is virtual memory group, carries out programming or control that reading in deletion action is forbidden in units of this virtual memory group.
According to another technical scheme of the present invention, provide a kind of memory storage with multiple memory set, wherein each memory set has the multiple storage unit for storing data and the multiple bit lines for reading data from described multiple storage unit, in all memory set, the storage unit of identical number is connected to along bit line bearing of trend, wherein said memory set is virtual memory group, carries out programming or control that reading in deletion action is forbidden in units of this virtual memory group.
Because the bit line of all memory set is isometric, so the access speed of memory storage entirety can be accelerated.In addition, due to the form of the virtual memory group of the combination as real storage group can be not limited to make the bit line of all virtual memory groups isometric, so reading at a high speed can be carried out.
Accompanying drawing explanation
Fig. 1 is the figure of the structure example of the real storage group of the flash memories illustrated according to embodiment of the present invention;
Fig. 2 is the figure of the hierarchical block structure example illustrated in real storage group according to the present embodiment;
Fig. 3 A ~ Fig. 3 D is the figure of the structure example that four kinds of flash memories are shown;
Fig. 4 A and Fig. 4 B is the figure that real storage group structure example is shown;
Fig. 5 A ~ Fig. 5 D is the figure of the structure example of the four kinds of flash memories illustrated in present embodiment;
Fig. 6 A and Fig. 6 B is the figure of the real storage group structure example illustrated in present embodiment.
Embodiment
Below, the example of embodiment of the present invention is described with reference to accompanying drawing.Protection scope of the present invention is not limited to embodiment below, covers invention and its equivalent invention of claims record.
Fig. 1 is the figure of the structure example of the real storage group of the flash memory device illustrated according to embodiment of the present invention.Real storage group comprise there is floating boom multiple storage unit m00, m01, m10, m11.Storage unit m00 ~ m11 is configured in the crossover location of each wordline WL0, WL1 and bit line BL0, BL1 respectively, and stores data.
Memory cell transistor m00, its control gate is connected on wordline WL0, and drain electrode is connected on bit line BL0, and source electrode is connected on earthing potential.Memory cell transistor m01, its control gate is connected on wordline WL0, and drain electrode is connected on bit line BL1, and source electrode is connected on earthing potential.Memory cell transistor m10, its control gate is connected on wordline WL1, and drain electrode is connected on bit line BL0, and source electrode is connected on earthing potential.Memory cell transistor m11, its control gate is connected on wordline WL1, and drain electrode is connected on bit line BL1, and source electrode is connected on earthing potential.
Wordline WL0, WL1 is driven according to address by word driver 101.Bit line BL0, BL1 are connected with data bus DB via column gate 103.Column gate 103, according to address, is connected to from middle one or more bit lines selected such as multiple bit lines on one or more data bus DB.One in select storage unit m00 ~ m11 is carried out by the selection of wordline WL0, WL1 and bit line BL0, BL1.The data read from selected storage unit m00 etc. are output on data bus DB via bit line BL0 or BL1.One or more sensor amplifier 102 amplifies the data read on one or more data bus DB.
Under deletion state, memory cell transistor m00 etc. is in the low state of threshold value (data " 1 ").Under programming state, by wordline WL0 or WL1 and bit line BL0 or BL1 is controlled, on positive noble potential, to inject negative charge in floating boom, thus threshold voltage settings is obtained high.This state is data " 0 ".In addition, when deleting, by bit line BL0 or BL1 is opened (OPEN), wordline WL0 or WL1 is controlled on earthing potential, and back bias is controlled on positive noble potential, draw the negative charge in floating boom, thus must be low by threshold voltage settings.This state is data " 1 ".When reading, the medium voltage of applying two kinds of threshold voltages on wordline WL0 or WL1, thus the size of the electric current flowed on bit line BL0 or BL1 by corresponding to threshold status reads storage data.
Fig. 2 is the figure of the hierarchical block structure example illustrated in real storage group according to the present embodiment.Main word driver 201 controls the voltage of main word line MWL (the 3rd metal level) according to address, and this main word line MWL is connected with multiple vertical block BLK.Sensor amplifier block 202 amplifies the data read on data bus DB.In region 203, multiple vertical block BLK arranges in the horizontal direction.Each vertical block BLK is vertically arranged multiple section SEC in region 204.Vertical word driver 221 and sub-driver 222 is configured with at the center section of section SEC.In right side and the left side of section, be configured with 1/2 selection circuit 211,213 and cell array 212.
Then read method is described.Be described with regard to 1/4 selection circuit 231.Four gate line g3 are connected with the grid of four n channel MOS transistor m3.According to address, one in four gate line g3 becomes high level, thus only has transistor m3 conducting correspondingly.Common data bus DB is connected on bit line (the second metal level) BL2 thus.That is, in four gate line g3 is selected.Bit line BL2 can be connected with storage unit mc1, mc2, mc3, mc4.By this selection, select four storage unit mc1 in multiple storage unit, mc2, mc3, mc4.
1/2 selection circuit 211 has n channel MOS transistor m1.Transistor m1, its grid is connected with gate line g1, and drain electrode is connected with bit line BL2, and source electrode is connected with the drain electrode of memory cell transistor mc2 and mc4.The source electrode of memory cell transistor mc1 ~ mc4 is connected on earthing potential.1/2 selection circuit 213 has n channel MOS transistor m2.Transistor m2, its grid is connected with gate line g2, and drain electrode is connected with bit line BL2, and source electrode is connected with the drain electrode of memory cell transistor mc1 and mc3.
According to address, a certain in above-mentioned gate line g1 and g2 becomes high level.Such as gate line g1 becomes high level, thus transistor m1 conducting, transistor m2 ends.Thus, bit line BL2 is connected on memory cell transistor mc2 and mc4.Carry out 1/2 selection thus.Combination is selected to carry out 1/8 selection with above-mentioned 1/4.
In addition, as mentioned above, owing to have selected sub-wordline SWL, so storage unit mc4 is selected as a result.Bit line BL2 and common data bus DB there is the current flowing corresponding to the threshold voltage of storage unit mc4.The electric current of this data bus DB is converted to voltage to amplify by sensor amplifier block 202, and it can be used as reading data externally to export.
Namely, on memory cell transistor mc4 on the crossover location being configured at sub-wordline SWL and bit line BL2 of such as above-mentioned selection, if threshold voltage becomes low state (data " 1 "), then have larger electric current and flow through bit line BL2, if threshold voltage becomes high state (data " 0 "), then on bit line BL2, electric current is not almost had to flow through.Bit line BL2 is connected with data bus DB via column gate (general name of 1/2 selection circuit 211,213 and 1/4 selection circuit 231), and then is connected with sensor amplifier block 202.The electric current flowing through bit line BL2 is exaggerated at this sensor amplifier block 202, thus carries out the reading storing data.
Main word line MWL is had by multiple vertical block BLK, and in each vertical block BLK via sub-driver 222 after, driven element wordline SWL in vertical block BLK.Therefore, the stray capacitance in main word line MWL comprises junction capacity in each sub-driver 222 corresponding with the progression of vertical block BLK and the wiring capacitance corresponding with length of arrangement wire.In addition, only otherwise change the number of the storage unit mc3 connected by grid in vertical block BLK etc., the stray capacitance in sub-wordline SWL is just constant.
Similarly, bit line BL2 is had by multiple section SEC, and via after 1/2 selection circuit 211,213 in each section SEC, is had by the storage unit mc1 in section SEC etc.Therefore, the stray capacitance in bit line BL2 comprises junction capacity in each 1/2 selection circuit 211,213 corresponding with the progression of section SEC and the wiring capacitance corresponding with length of arrangement wire.In addition, only otherwise change the number of the storage unit mc1 connected by knot in section SEC etc., just constant via the stray capacitance in the bit line after 1/2 selection circuit 211,213.
In general, compared with main word line (the 3rd metal line) MWL, the wiring capacitance of bit line BL2 (the second metal line) is large.When reading, because the Weak current of storage unit mc1 etc. must flow through bit line BL2, if so this bit line BL2 has superfluous stray capacitance, be then difficult to the movement finding electric charge, from unsatisfactory this point.Therefore, determine that the progression of the section SEC of the length of bit line BL2 should not got a lot.
Fig. 3 A ~ Fig. 3 D is the figure of the structure example that four kinds of flash memories are shown.Four kinds of flash memories are formed by four real storage group BNKA, BNKB, BNKC, BNKD.Real storage group BNKA and BNKD is the memory capacity of 1/8 of whole memory area.Real storage group BNKB and BNKC is the memory capacity of 3/8 of whole memory area.That is, real storage group BNKB and BNKC has 3 times to the memory capacity of real storage group BNKA and BNKD.The memory capacity ratio of four real storage group BNKA ~ BNKD is 1: 4: 4: 1.
The flash memories of Fig. 3 A has two virtual memory group VBNK1 and VBNK2.Virtual memory group VBNK1 is made up of a real storage group BNKA.Virtual memory group VBNK2 is made up of three real storage group BNKB, BNKC, BNKD.The memory capacity ratio of virtual memory group VBNK1 and virtual memory group VBNK2 is 1: 7.
The flash memories of Fig. 3 B has two virtual memory group VBNK1 and VBNK2.Virtual memory group VBNK1 is made up of two real storage group BNKA, BNKD.Virtual memory group VBNK2 is made up of two real storage group BNKB, BNKC.The memory capacity ratio of virtual memory group VBNK1 and virtual memory group VBNK2 is 2: 6.
The flash memories of Fig. 3 C has two virtual memory group VBNK1 and VBNK2.Virtual memory group VBNK1 is made up of two real storage group BNKA, BNKB.Virtual memory group VBNK2 is made up of two real storage group BNKC, BNKD.The memory capacity ratio of virtual memory group VBNK1 and virtual memory group VBNK2 is 4: 4.
The flash memories of Fig. 3 D has four virtual memory group BNKA ~ BNKD.That is, real storage group is identical with virtual memory group.
The flash memories of Fig. 3 A ~ Fig. 3 C is the storer of two groups be made up of two virtual memory groups.The flash memories of Fig. 3 D is the storer of four groups be made up of four virtual memory groups.
Here, real storage group refers to the set of the actual multiple storage unit be formed on memory area, it at least comprises word driver 101, row gate 103 and memory cell array m00 ~ m11, and selected by the selection signal of real storage group, this selection signal obtains by selecting address to carry out decoding to memory set.That is, the real storage group that multiple real storage group is merely able to from selecting reads data.
In addition, virtual memory group is the memory set formed by one or more real storage group.It is the virtual memory set from the system side of installing storer.In general, carry out programming in units of this virtual memory group or control that reading in deletion action is forbidden.That is, in the same period, programming operation can be carried out in a virtual memory group, while carry out read operation in other virtual memory groups.
Fig. 4 A is the figure of the structure example that real storage group BNKA in Fig. 3 A ~ Fig. 3 D and BNKD is shown.Real storage group BNKA and BNKD when below being arranged at by sensor amplifier block 401, has segment array 402 in the above.Segment array 402 is arranged two section SEC along the direction (vertical direction) that bit line extends, and the direction (horizontal direction) extended along wordline is arranged four section SEC, thus has 8 section SEC0 ~ SEC7.
Fig. 4 B is the figure of the structure example that real storage group BNKB in Fig. 3 A ~ Fig. 3 D and BNKC is shown.Real storage group BNKB and BNKC when below being arranged at by sensor amplifier block 411, has segment array 412 in the above.Segment array 412 is arranged six section SEC along the direction that bit line extends, and the direction extended along wordline is arranged four section SEC, thus has 24 section SEC0 ~ SEC23.
These sections SEC is the least unit of programming and deletion action, or can programme to multiple section simultaneously or delete each section SEC.The bitline length 403 of the segment array 402 of Fig. 4 A is two section length.The bitline length 413 of the segment array 412 of Fig. 4 B is six section length.That is, the ratio of the stray capacitance in the bit line of segment array 402 and segment array 412 has the difference of 1: 3.In the case, as the access speed of flash memories, the data reading speed in the memory set structure of Fig. 4 B that bitline length is the longest becomes the poorest access, and access speed overall is thus slack-off.
Fig. 5 A ~ Fig. 5 D is the figure of the structure example of the four kinds of flash memories illustrated in present embodiment.The flash memories of Fig. 5 A ~ Fig. 5 D is the storer making the bitline length of the flash memories of Fig. 3 A ~ Fig. 3 D isometric respectively, and with regard to the relation of real storage group and virtual memory group, both are identical.That is, in Fig. 3 A ~ Fig. 3 D, the real storage group BNKA on bit line bearing of trend (vertical direction), the length of BNKD are different with the length of real storage group BNKB, BNKC.In Fig. 5 A ~ Fig. 5 D, the length of the real storage group on bit line bearing of trend (vertical direction) is all identical with regard to all real storage group BNKA ~ BNKD.
In Fig. 5 A, the ratio of the memory capacity of two virtual memory group VBNK1 and VBNK2 is 1: 7.In Fig. 5 B, the ratio of the memory capacity of two virtual memory group VBNK1 and VBNK2 is 2: 6.In Fig. 5 C, the ratio of the memory capacity of two virtual memory group VBNK1 and VBNK2 is 4: 4.In Fig. 5 D, the ratio of the memory capacity of four virtual memory group BNKA ~ BNKD is 1: 4: 4: 1.
Fig. 6 A is the figure that the real storage group BNKA of Fig. 5 A ~ Fig. 5 D and the structure example of BNKD are shown.Real storage group BNKA and BNKD when below being arranged on by sensor amplifier block 601, has segment array 602 in the above.Segment array 602 is arranged four section SEC along the direction (vertical direction) that bit line extends, and the direction (horizontal direction) extended along wordline is arranged two section SEC, thus has 8 section SEC0 ~ SEC7.
Fig. 6 B is the figure that the real storage group BNKB of Fig. 5 A ~ Fig. 5 D and the structure example of BNKC are shown.Real storage group BNKB and BNKC when below being arranged on by sensor amplifier block 611, has segment array 612 in the above.Segment array 612 is arranged four section SEC along the direction that bit line extends, and the direction extended along wordline is arranged six section SEC, thus has 24 section SEC0 ~ SEC23.
The bitline length 603 of the segment array 602 of Fig. 6 A is four section length.The bitline length 613 of the segment array 612 of Fig. 6 B is four section length.That is, the ratio of the stray capacitance in the bit line of segment array 602 and segment array 612 is identical.Therefore, the access speed of the real storage group of Fig. 6 A is identical with the access speed of the real storage group of Fig. 6 B.Thus, the access speed of flash memories entirety accelerates.
In the flash memories of real storage group with Fig. 4 A and Fig. 4 B, the poorest access speed is the access speed suitable with the bitline length 413 of six of Fig. 4 B section length.On the other hand, in the flash memories of real storage group with Fig. 6 A and Fig. 6 B, the poorest access speed is and the bitline length 603 of four section length of Fig. 6 A and Fig. 6 B, 613 suitable access speeds, thus has accelerated.
In addition, the wordline length of the real storage group of Fig. 6 A is two section length, and the wordline length of the real storage group of Fig. 6 B is six section length, and the ratio of the stray capacitance therefore in each wordline is 1: 3.
As mentioned above, according to the present embodiment, memory storage has multiple memory set, and the bit line of all memory set of multiple memory set is isometric.Here, while the bit line of all real storage groups is isometric, the bit line of all virtual memory groups is also isometric.In all memory set of multiple memory set, bit line is connected to the storage unit of identical number, and is arranged the section of identical number along the direction that bit line extends.Section has multiple storage unit, is that data delete unit.Such as, as the real storage group BNKA of Fig. 6 A and the real storage group BNKB of BNKD and Fig. 6 B and BNKC, flash memories at least has the real storage group of two or more different memory sizes.
According to the present embodiment, because the bit line of all memory set is isometric, so the access speed of memory storage entirety can be accelerated.In addition, as shown in Fig. 5 A ~ Fig. 5 D, due to the form of the virtual memory group of the combination as real storage group can be not limited to make the bit line of all virtual memory groups isometric, so reading at a high speed can be carried out.
In addition, being illustrated as an example above with flash memories, but being not limited thereto, also can be other storer.Storage unit both can be non-volatile memory cells, also can be volatile memory cell, but preferred non-volatile memory cells.
Above-mentioned embodiment illustrate only and is suitable for implementing object lesson of the present invention, can not explain technical scope of the present invention with limiting according to these.That is, the present invention can implement in a variety of manners in the scope not departing from its technical conceive or its principal character.
Industrial applicibility
Because the bit line of all memory set is isometric, so the access speed of memory storage entirety can be accelerated.In addition, due to the form of the virtual memory group of the combination as real storage group can be not limited to make the bit line of all virtual memory groups isometric, so reading at a high speed can be carried out.
Claims (7)
1. a memory storage, comprises multiple real storage group and multiple virtual memory group, wherein:
Each of described multiple real storage group has the multiple storage unit for storing data and the multiple bit lines for reading data from described multiple storage unit, each in described multiple bit lines is by being connected respectively with for each data line read in the sensor amplifier block of data from described multiple storage unit with data bus for the column gate according to address selection bit line
Described multiple real storage group at least has the real storage group of two or more different memory sizes, and the bit line of all real storage groups is isometric, and
Carry out programming in units of this virtual memory group or control that reading in deletion action is forbidden, each virtual memory group is formed by one or more real storage group, and the bit line of all virtual memory groups is isometric and distance apart from described sensor amplifier block is equal.
2. memory storage as claimed in claim 1, wherein said multiple real storage group is merely able to read data from by a real storage group selecting.
3. memory storage as claimed in claim 1, wherein in all real storage groups of described multiple real storage group, described bit line is connected to the storage unit of identical number.
4. memory storage as claimed in claim 3, wherein in all real storage groups of described multiple real storage group, is arranged the section of identical number along the direction that described bit line extends.
5. memory storage as claimed in claim 4, wherein said section has multiple storage unit, and is that data delete unit.
6. memory storage as claimed in claim 5, wherein said multiple real storage group is merely able to read data from by a real storage group selecting.
7. memory storage as claimed in claim 1, wherein said storage unit is non-volatile memory cells.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2003/002832 WO2004081946A1 (en) | 2003-03-11 | 2003-03-11 | Memory |
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| CN1689117B true CN1689117B (en) | 2015-08-12 |
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| CN03824185.4A Granted CN1689117A (en) | 2003-03-11 | 2003-03-11 | Memory |
| CN03824185.4A Expired - Fee Related CN1689117B (en) | 2003-03-11 | 2003-03-11 | Memory storage |
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| CN03824185.4A Granted CN1689117A (en) | 2003-03-11 | 2003-03-11 | Memory |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5673222A (en) * | 1995-06-20 | 1997-09-30 | Sharp Kabushiki Kaisha | Nonvolatile semiconductor memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2625277B2 (en) * | 1991-05-20 | 1997-07-02 | 富士通株式会社 | Memory access device |
| US6591327B1 (en) * | 1999-06-22 | 2003-07-08 | Silicon Storage Technology, Inc. | Flash memory with alterable erase sector size |
| JP2001084777A (en) * | 1999-09-09 | 2001-03-30 | Hitachi Ltd | Semiconductor memory |
| JP2002329396A (en) * | 2001-04-26 | 2002-11-15 | Fujitsu Ltd | Flash memory whose bank constitution can be modified |
-
2003
- 2003-03-11 WO PCT/JP2003/002832 patent/WO2004081946A1/en active Application Filing
- 2003-03-11 CN CN03824185.4A patent/CN1689117A/en active Granted
- 2003-03-11 CN CN03824185.4A patent/CN1689117B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5673222A (en) * | 1995-06-20 | 1997-09-30 | Sharp Kabushiki Kaisha | Nonvolatile semiconductor memory device |
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| JPWO2004081946A1 (en) | 2006-06-15 |
| WO2004081946A1 (en) | 2004-09-23 |
| CN1689117A (en) | 2005-10-26 |
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