CN1688135A - Flow receiving taking and statistic circuit assembly for 10G network performance tester - Google Patents
Flow receiving taking and statistic circuit assembly for 10G network performance tester Download PDFInfo
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Abstract
This invention relates to a flow receiving, gripping and calculating circuit component for a 10G network performance test instrument characterizing in separating the data into two parts with a branch circuit after receiving the frame data from a frame controller by the PL4 IP core receiver, one part passing through the protocol sending circuit and a related storage is fetched by CPU via the CPU interface circuit to be sent to an upper level applied program, the other part passes through the data analysis pre-process circuit to carry out the flow and ping packet statistics to be sent to CPU via related interface circuit and to the data packet gripping circuit, which decides datum that should be written into the outboard SRAM based on the plan and generates a written, request signal to be sent to the arbitration circuit to arbitrate and select from the read-write instructions.
Description
Technical field
The invention belongs to applied in network performance test technical field in express network and the network device performance test thereof.
Background technology
Applied in network performance test is meant the performance of the test network system and the network equipment, and the performance of the network system and the network equipment is estimated.The specific performance index of measurand is paid close attention in performance test, as throughput, delay, Loss Rate etc., is a kind of important means of estimating the performance of under the heterogeneous networks load tested network or the network equipment exactly.Test macro is finished the test function to tested network or equipment under test, is made up of equipment under test (DUT:Device Under Test), test executing device (being also referred to as " tester ") and this three part of test monitoring device (being also referred to as " monitoring equipment ").Tester is realized test port, finishes the basic function of test, comprises the generation of measurement, route message of the generation of test traffic and reception, test statistics and message intercepting etc.In the express network performance test, generally use PC as the test monitoring device, the test monitoring device is also referred to as " monitoring equipment ", and User Interface is provided, and comprises the analysis of setting, test result of test parameter and demonstration etc.;
In applied in network performance test, adopt initiatively method of measurement, tester generates and sends test traffic on one's own initiative, and transmit through equipment under test and get back to tester, tester analytical test flow, thus draw the performance index of the network or the network equipment.Flow reception, extracting and statistical circuit assembly are the important component parts of tester, finish reception, extracting and the statistical function of test traffic, realize the test of dependence test object performance index.
At home and abroad, test traffic reception, the realization of grasping and adding up have two kinds of methods of hardware and software.Realize that with software test traffic receives, grasps and statistics merely, speed is lower and real-time is too poor, can't satisfy the performance test demand of the express network or the network equipment, under the 10G network condition, have the performance test requirement of adopting hardware approach to realize just reaching rfc1242, rfc2544 regulation only.And hardware approach is realized also adopting application-specific integrated circuit (ASIC) (ASIC) device to realize, just in a single day the ASIC device designs moulding, and internal logic and function just can't change, and upgradability and extensibility are relatively poor.Therefore, we adopt the FPGA technology to realize reception, extracting and the statistics of test traffic.Yet there are no any report in these all kinds of at present documents at home and abroad.
Summary of the invention
But the object of the present invention is to provide a real time high-speed ground to realize test traffic reception, extracting and statistics and upgradability and extensibility 10G network performance tester flow reception preferably, extracting and statistical circuit assembly.
The invention is characterized in: it is made up of following each circuit part:
A:PL4 IPCore receiver is called for short the IPCore circuit, and its data input pin and the frame controller of outside are that the corresponding output end of Framer links to each other;
B: the data shunt circuit, its data input pin that is converted to the FPGA sequential links to each other with the corresponding output end of above-mentioned IP Core circuit;
C: protocol frame is submitted circuit, and its packet input links to each other with the corresponding output of above-mentioned data shunt circuit;
D: the data analysis pre-process circuit, its packet input links to each other with the corresponding output end of above-mentioned data shunt circuit, so that the packet that is received is made pretreatment operation;
E: packet grasps circuit, and its packet input links to each other with the corresponding output end of above-mentioned data analysis pre-process circuit, so that packet is grasped; Its SRAM FPDP and external SRAM corresponding port interconnection simultaneously;
F: internet information search packet protocol package is the statistical circuit of ping bag, its packet input links to each other with the corresponding output end of above-mentioned data analysis pre-process circuit, so that finish the statistical work of ping bag, comprising the statistics of overall budget number, total delay and current delay;
G: the stream statistical circuit, its data flow input links to each other with the corresponding output end of above-mentioned data analysis pre-process circuit, so that realize the statistics to the performance condition of data flow;
H: the protocol frame memory, its protocol frame input links to each other with the corresponding output end that above-mentioned protocol frame is submitted circuit;
I: totally 5 of stream statistics memories, their FPDP respectively with the corresponding port interconnection of above-mentioned stream statistical circuit;
J:CPU interface circuit, its each output grasp circuit, data analysis pre-process circuit, protocol frame with above-mentioned packet respectively and submit the corresponding output end of circuit, stream statistical circuit and link to each other; Each input of cpu interface circuit links to each other with the corresponding output end that above-mentioned packet grasps circuit, ping bag statistical circuit, stream statistical circuit, each stream statistics memory, protocol frame memory; Simultaneously, to also have a PORTX be communication interface transmitting-receiving and port external interconnect to above-mentioned cpu interface circuit;
Wherein, data shunt circuit B comprises:
B1: input register, its packet input links to each other with the corresponding output end of above-mentioned IP Core circuit;
B2: first, second output register, promptly output register 1,2, and their packet input links to each other with the corresponding output end of above-mentioned input register respectively;
Wherein protocol frame is submitted circuit C and is comprised:
C1: protocol frame screening circuit comprises:
C1a: frame type is differentiated logical circuit, and its packet input links to each other with the corresponding output end of the 2nd output register in the above-mentioned data shunt circuit;
C1b: data latches, its enable signal input, frame data input link to each other with the corresponding output end of above-mentioned frame type differentiation logical circuit respectively;
C2: valid data detect logical circuit, and its frame data input links to each other with the corresponding output end that above-mentioned protocol frame screens the data latches in the circuit;
C3: data register, its data input pin links to each other with the output that above-mentioned valid data detect logical circuit;
C4: the count enable signal that memory space counter, above-mentioned valid data detect logical circuit output is useful signal is sent to above-mentioned memory space counter after adding 1 counter a respective input, and the value that adds after 1 is sent to above-mentioned 1 counter that adds;
C5: the spatial threshold value register, its Configuration Values input links to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J;
C6: the time threshold register, its Configuration Values input links to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J;
C7: the internal clocking counter, each clock cycle counter adds 1;
C8: first comparator, its two inputs link to each other with the corresponding output end of above-mentioned spatial threshold value register, memory space counter respectively;
C9: second comparator, its two inputs link to each other with two outputs of above-mentioned time threshold register, internal clocking counter respectively;
C10: interrupt clear register, its interrupt clear signal input part links to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J; Its two reset signal outputs link to each other with the respective input of above-mentioned memory space counter, internal clocking counter respectively;
C11: the interrupt control logic circuit, its two interruptions generate signal input part and link to each other with the corresponding output end of above-mentioned first, second comparator respectively, and its interrupt clear signal input part links to each other with the corresponding output end of above-mentioned interrupt clear register;
Each circuit of above-mentioned C2～C12 is formed interrupt circuit jointly, the protocol frame of sending here from above-mentioned protocol frame screening circuit C1 is stored in above-mentioned protocol frame memory H by above-mentioned data register C3, submits to upper layer software (applications) by the interrupt requests mode of above-mentioned interrupt control logic circuit by the PORTX output of the above-mentioned cpu interface circuit of representing with J then and handle; Wherein, above-mentioned data analysis pre-process circuit D comprises:
D1: the port count circuit is finished port statistics and forwarding of data operation, and it comprises:
D1a: frame number and byte number counting logical circuit, an input links to each other with the corresponding output end of the 1st output register in the above-mentioned data shunt circuit;
D1b: frame number counter, above-mentioned frame number links to each other with the input of this frame number counter behind one adder with the frame number value output of byte number counting logical circuit, add 1 back frame number count value and send above-mentioned frame number and byte number counting logical circuit again back to, be sent to the above-mentioned cpu interface circuit of representing with J simultaneously again;
D1c: byte number counter, the byte number output of above-mentioned frame number and byte number counting logical circuit link to each other with the input of this byte number counter after through one+α adder, and the byte number the behind+α is sent to above-mentioned frame number again and byte number is counted logical circuit; Simultaneously, be sent to the above-mentioned cpu interface circuit of representing with J again; The α value is a set point;
D2: the protocol frame filtering circuit, it filters out all protocol frames in the frame that receives, and it comprises:
D2a: frame type is differentiated logical circuit, and its input links to each other with the corresponding output end of byte number counting logical circuit with frame number in the above-mentioned port count circuit;
D2b: data latches, its data input pin links to each other with the corresponding output end of above-mentioned frame type differentiation logical circuit D2a respectively with the enable signal input;
D3: the frame head stripper circuit, it removes the PPP information frame of higher level's circuit output or mac frame frame head, comprising:
D3a: data buffer one, its input connect the output of data latches in the above-mentioned protocol frame filtering circuit;
D3b: data buffer two, its input connects the output of above-mentioned data buffer one;
D3c: data word splicing control state machine, its two inputs connect the corresponding output end of above-mentioned data buffer one, two respectively;
D4: stream and ping data markers circuit, it checks whether each packet has stream label, makes respective markers again on side information, and promptly flow label signal str and ping wrap marking signal png, and it comprises:
D4a: stream and ping discriminating data logical circuit, its input connect the corresponding output end of data word splicing control state machine in the above-mentioned frame head stripper circuit;
D4b:4 claps delay time register, and its input connects the output of above-mentioned stream and ping discriminating data logical circuit;
D5: background flows through the filter circuit, and the background stream with the option field mark in its convection tags filters, and comprising:
D5a: background stream is differentiated logical circuit, and its input links to each other with 4 outputs of clapping delay time register in the ping data markers circuit with above-mentioned stream; Simultaneously, also have two inputs and above-mentioned stream to link to each other with flow label signal str, ping bag marking signal png in the ping discriminating data logical circuit;
D5b: data latches, its data input pin, str signal input part, png signal input part link to each other with the corresponding output end that enable signal input and above-mentioned background stream are differentiated logical circuit;
D6: erroneous packets marking circuit, it carries out a verification and calculating to each IPv4 bag that receives and according to verification and whether wrong, add respective markers at this packet side information place, be verification and mark chk, correctly be 0, mistake is 1, and carries out the statistics of the bag number of bad checksum, and it comprises:
D6a: verification and inspection logical circuit, its data, str signal, png signal input part flow through the corresponding output end of filtering data latches in the circuit with above-mentioned background respectively and link to each other;
D6b: erroneous packets counter, above-mentioned verification links to each other with the input of this erroneous packets counter behind an one adder with the output of checking logical circuit, the erroneous packets number that adds after 1 is sent verification back to and is checked logical circuit, is sent to the above-mentioned cpu interface circuit of representing with J simultaneously;
D7: the routing error counting circuit, it is differentiated each packet that receives whether routing error takes place, and adds that corresponding side information is routing error mark mis, the counting of walking along the street by erroneous packets of going forward side by side; Divide data three the road to transmit simultaneously, the data that added side information are sent to next packet respectively grasp circuit, stream statistical circuit and ping bag statistical circuit; Described routing error statistical circuit comprises:
D7a: destination interface is checked logical circuit, its data input pin, str signal input part, png signal input part and chk signal input part respectively with above-mentioned erroneous packets counting circuit D6 in verification and check that the corresponding output end of logical circuit links to each other, and the local port number input of packet links to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J;
D7b: the wrong counter of route, an output of above-mentioned purpose port test logical circuit link to each other with the respective input of this erroneous packets counter after through an one adder, again the routing error bag number that adds after 1 are returned above-mentioned purpose port test logical circuit;
D7c:4 claps delay time register, and its data input pin, str signal input part, png signal input part, chk signal input part link to each other with the corresponding output end of above-mentioned purpose port test logical circuit respectively;
D7d: output latch one, its packet input, enable signal str signal input part link to each other with above-mentioned 4 corresponding output end of clapping delay time register respectively; The output of this latch one links to each other with the respective input of above-mentioned stream statistical circuit G;
D7e: output latch two, its data input pin, enable signal png signal link to each other with above-mentioned 4 corresponding output end of clapping delay time register respectively; The output of this latch two links to each other with the input of above-mentioned ping bag statistical circuit;
Wherein, above-mentioned packet grasps the data execution packet grasping manipulation that circuit is sent here the data analysis pre-process circuit, and it comprises:
The E1:IP address matcher circuit, it carries out the matching inspection of source, destination address to the input packet, and is transmitted to subordinate's circuit adding on the side information after respective markers is source address matches signal sip, matching destination address signal dip, and it comprises:
E1a:IP matching addresses logical circuit, its data input pin, verification and mark chk input link to each other with 4 corresponding output end of clapping delay time register D7c among the above-mentioned routing error counting circuit D7 respectively, and its routing error mark mis signal input part links to each other with the corresponding output end of above-mentioned purpose port test logical circuit D7a; The purpose IP address of this IP matching addresses logical circuit and matched rule, source IP address and matched rule input link to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J respectively;
E1b:3 claps delay time register, and its data input pin, chk signal input part, mis signal input part link to each other with the corresponding output end of above-mentioned IP matching addresses logical circuit respectively;
E2: packet header agreement and length field match circuit, it carries out the matching inspection of protocol number, length to the packet that receives, and be transmitted to the next stage circuit adding on the side information of packet after respective markers is protocol number matched signal pro, length 1 matched signal len1, length 2 matched signal len2, it comprises:
E2a: packet header agreement and length field match logic circuitry, its data input pin, verification and mark chk input, routing error mark mis input link to each other with 3 corresponding output end of clapping delay time register E1b among the above-mentioned IP address matcher circuit E1 respectively, and its source address matches signal sip input, matching destination address signal dip input link to each other with the corresponding output end of above-mentioned IP matching addresses logical circuit E1a respectively; Its length 1 and matched rule, length 2 and matched rule, protocol number and matched rule input link to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J respectively; So-called protocol number is meant the protocol fields of IPv4 and IPv6 heading; So-called length 1, length 2 are given message length values;
E2b:1 claps delay time register, and its data input pin, chk signal input part, mis signal input part, sip signal input part, dip signal input part link to each other with the corresponding output end of length field match logic circuitry with above-mentioned packet header agreement respectively;
E3: trigger match circuit, it is the trigger coupling that the partial content that it is chosen the packet that receives from higher level's circuit carries out trigger message, and be transmitted to the next stage circuit adding on the side information of packet after respective markers is trigger match signal trig1, trig2, trig3, trig4, it comprises:
E3a: trigger match logical circuit, its data input pin, verification and mark chk input, routing error mark mis input, source address matches mark sip input, matching destination address mark dip input link to each other with 1 corresponding output end of clapping delay time register E2b in above-mentioned packet header agreement and the length field match circuit respectively, and its other 3 side information pro, len1, len2 input link to each other with the corresponding output end of above-mentioned packet header agreement with length field match logic circuitry E2a respectively; Its 4 trigger messages be trigger1,2,3,4 and 4 inputs of corresponding matched rule link to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J; Wherein, described len1, len2 are the side informations of expression length field, and pro is meant the side information of the next header field of the protocol field of IPv4 or IPv6, i.e. protocol number matched signal; Trig1～trig4 is 4 match information that are used for the trigger rule of expression, and wherein any trigger is one group of matched rule, finishes the inspection of particular value in an IP Bao one zone is compared;
E3b:5 claps delay time register, and its data input pin, each side information chk, mis, sip, dip, pro, len1, len2 input link to each other with the corresponding output end of above-mentioned trigger match logical circuit E3a respectively;
E4: data grasp control circuit, and whether it determines a packet should write in the external SRAM according to each the sideband mark in the extracting scheme contrasting data bag of configuration and remove generation SRAM written request signal; It comprises:
E4a: grasp control logic circuit, 5 clap delay time register E3b and link to each other in its each side information chk, mis, sip, dip, pro, len1, len2 input and the above-mentioned trigger match circuit, and other 4 side information trig1～trig4 link to each other with trigger match logical circuit E3a in the above-mentioned trigger match circuit;
E4b: data latches, its data input pin, enable signal link to each other with above-mentioned 5 corresponding output end of clapping delay time register E3b, extracting control logic circuit E4a respectively;
The E5:SRAM arbitration circuit, receive the read request of the cpu interface circuit of representing from the write request of above-mentioned extracting control circuit and the J that use by oneself simultaneously, generate and meet the sheet read-write control signal of SRAM sequential outward, wherein, read request from above-mentioned cpu interface circuit has higher priority, and it comprises:
E5a: the read-write arbitraling logic circuit, it and above-mentioned cpu interface circuit interconnect, and its another input links to each other with the corresponding output end of above-mentioned data latches E4b, this read-write arbitraling logic circuit interconnects with the outer SRAM of sheet again;
Wherein, the statistics of the delay of overall budget number, total delay and last bag of the statistical circuit realization ping packet of ping bag, it comprises:
F1: packet detects logical circuit;
F2: postpone the extraction logic circuit;
The input of these two circuit of F1, F2 respectively with above-mentioned data analysis pre-process circuit in the routing error counting circuit two outputs of output register two link to each other;
F3:ping bag number register, its input links to each other with the output that above-mentioned packet detects logical circuit;
F4: total delay register, the result of its storage total delay statistics;
F5: adder, its two inputs connect the corresponding output end that postpones extraction logic circuit and total delay register respectively, and the output of this adder links to each other with the input of total delay register;
F6: current delay time register, its input links to each other with the output of above-mentioned delay extraction logic circuit;
Wherein, the stream statistical circuit, it comprises:
G1: every flow delay statistical circuit, it adds up and gives record to the every stream packets transmission delay that comprises maximum delay, minimum delay and total delay, reads for the cpu interface circuit of representing with J, and it comprises:
G1a: in the stream numbering extraction logic circuit, its data input pin and above-mentioned data analysis pre-process circuit in the routing error counting circuit output of output register one link to each other;
G1b: postpone the extraction logic circuit, the input of its input and above-mentioned stream numbering extraction logic circuit is and connects;
G1c: total delay register;
G1d: adder, its two inputs link to each other with the output of above-mentioned delay extraction logic circuit and total delay register respectively;
G1e: maximum delay register;
G1f: comparator one, its two inputs link to each other with each output that postpones the extraction logic circuit with above-mentioned maximum delay register respectively;
G1g: minimum delay register;
G1h: comparator two, its two inputs link to each other with each output that postpones the extraction logic circuit with above-mentioned minimum delay register respectively;
G1i:2 circuit-switched data selector one, its two inputs link to each other with each output that postpones the extraction logic circuit with above-mentioned maximum delay register respectively;
G1j:2 circuit-switched data selector two, its two inputs link to each other with each output that postpones the extraction logic circuit with above-mentioned minimum delay register respectively;
G1k: write data register, its three inputs link to each other with the output of above-mentioned adder with two data selectors one, two respectively;
G1l: read data register, its data-out port links to each other with the input of above-mentioned total delay register, maximum delay register, minimum delay register;
G1m: the read/write address register, its data input pin links to each other with the output of above-mentioned stream numbering extraction logic circuit;
G2: the out of order statistical circuit of every stream, it adds up the number of dropped packets of every stream, out of order and retransmission count information, and the storage statistics, reads for the cpu interface circuit of representing with J, and it comprises:
G2a: in the stream numbering extraction logic circuit, its data input pin and above-mentioned data analysis pre-process circuit in the routing error counting circuit output of output register one link to each other;
G2b: bag sequence number extraction logic circuit, the input of its data input pin and above-mentioned stream numbering extraction logic circuit G2a also connects;
G2c: lost package number register;
G2d: retransmission packet number register;
G2e: out of order bag number register;
G2f:RFC1242 windowing mechanism controller, its 4 inputs link to each other with the output of above-mentioned bag sequence number extraction logic circuit G2b and lost package, retransmission packet, each number register of out of order bag respectively;
G2g: write data register, its input links to each other with the output of above-mentioned RFC1242 windowing mechanism controller;
G2h: read data register, its data output end links to each other with the input of above-mentioned lost package, retransmission packet, each number register of out of order bag;
G2i: the read/write address register, its data input pin links to each other with the output of above-mentioned stream numbering extraction logic circuit G2a;
G3: the real time delay statistical circuit, it decides according to option territory in the stream label which bar stream is carried out the real time delay statistics, and stores corresponding statistics, reads for the cpu interface circuit of representing with J, and it comprises:
G3a: postpone the extraction logic circuit, in its data input pin and the above-mentioned data analysis pre-process circuit in the routing error counting circuit output of output register one link to each other;
G3b: delay time register, its input links to each other with the output of above-mentioned delay extraction logic circuit;
G3c: write data register, its input links to each other with the output of above-mentioned delay time register;
G3d: next address register;
G3e: writing address register, its input links to each other with the output of above-mentioned next address register, and its output links to each other with the input of above-mentioned next address register after through an one adder, the value that adds after 1 is returned this writing address register:
G4: postpone the distribution statistics circuit, it does the delay distribution statistics according to option territory decision in the stream label to which bar stream, and statistics storage and the cpu interface circuit that supplies to represent with J read, and it comprises:
G4a: postpone the extraction logic circuit, in its data input pin and the above-mentioned data analysis pre-process circuit in the routing error counting circuit output of output register one link to each other;
G4b: 15 outputs that postpone the interval endpoint registers of the cpu interface circuit that data comparison circuit, its two inputs are represented with above-mentioned delay extraction logic circuit G4a, with J respectively link to each other;
G4c: the read/write address register, its input links to each other with the output of above-mentioned data comparison circuit G4b;
G4d: postpone a number register in interval;
G4e: read data register, its data output end links to each other with the input of a delay number register in the above-mentioned interval;
G4f: write data register, its data input pin links to each other with the output of a delay number register in the above-mentioned interval;
G5: every stream statistical circuit, the data that comprise every stream byte number, overall budget number that its statistics receives, and store for the cpu interface circuit of representing with J and read, it comprises:
G5a: stream numbering extraction logic circuit, its data go in end and the above-mentioned data analysis pre-process circuit that the output of output register one links to each other in the routing error counting circuit;
G5b: byte number register;
G5c: bag number register;
G5d: read data register, its two data outputs link to each other with the input of above-mentioned byte number register, bag number register respectively;
G5e: write data register, the output valve of above-mentioned bag number register adds the input that is sent to this write data register after 1, and the output valve of above-mentioned byte number register adds the input that is sent to this write data register behind the α;
G5f: the read/write address register, its input links to each other with the output of above-mentioned stream numbering extraction logic circuit G5a;
Wherein, 5 stream statistics memory I, its divide in addition with above-mentioned every flow delay statistical circuit in, in the out of order statistical circuit of every stream, postpone in the distribution statistics circuit and in every stream statistical circuit the input of read data register link to each other, and link to each other with their write data register, each output of read/write address register; The input of these 5 stream statistics memories also links to each other with each output of write data register, writing address register in the above-mentioned real time delay statistical circuit;
Wherein, cpu interface circuit represents that with J it instructs according to outer CPU and finishes the configuration of each configuration register and the submission of each statistics, and it comprises:
The J1:CPU address register;
J2:CPU control signal register;
The ternary scheduling logic circuit of J3:CPU data/address bus, its input links to each other with the output of above-mentioned CPU control signal register;
Foregoing circuit J1～J3 links to each other with the outer CPU corresponding output end respectively;
J4: address decoder, its input links to each other with the output of above-mentioned cpu address register;
J5: status register group, its input links to each other with frame number counter D1b, byte counter D1c, erroneous packets counter D6b, each output of the wrong counter D7b of route in the above-mentioned data analysis pre-process circuit respectively, and its input also links to each other with ping each output of wrapping number register F3, total delay register F4, current delay time register F6 in the above-mentioned ping bag statistical circuit;
J6: groups of configuration registers, its each output are connected respectively to above-mentioned packet and grasp each continuous input that circuit, data analysis pre-process circuit, protocol frame are submitted circuit, stream statistical circuit;
◆ J7: the external SRAM data register, its input links to each other with the SRAM arbitration circuit that packet grasps circuit;
◆ J8: stream statistics memory data register group, its each input link to each other with each output of above-mentioned 5 stream statistics memories respectively;
◆ J9: the protocol frame memory data register, its each input links to each other with the output of above-mentioned protocol frame memory;
Each output of above-mentioned address decoder J4 links to each other with the input of above-mentioned each circuit of J5～J9 respectively; Each input of the ternary scheduling logic circuit of above-mentioned cpu data bus links to each other with each output of above-mentioned status register group, external SRAM data register and protocol frame memory data register respectively; Simultaneously, interconnect with above-mentioned stream statistics memory data register group again; Its output then links to each other with the input of above-mentioned groups of configuration registers.
This high speed test flow performance analytical equipment is supported two kinds of patterns: the pattern of 10G POS and 10G Ethernet LAN/WAN.It has realized carrying out real-time statistics and extracting from an OC192 or 10G Ethernet interface acceptance test packet, thus obtain various performance index and will grasp after data deposit the outer SRAM confession of sheet CPU in and read.This equipment is supported the performance test of IPv4 and IPv6 simultaneously, can realize that the linear velocity of minimum 20 byte data bags is handled, and support that CPU reads various performance index in real time.
Description of drawings
Fig. 1 stream label structure chart;
Fig. 2 test macro totally constitutes;
Fig. 3 tester backboard, mainboard are connected situation with master control borad;
Fig. 4 tester mainboard structure block diagram;
Fig. 5 tester mainboard receives the FPGA cut-away view;
Fig. 6 data shunt circuit;
Fig. 7 protocol frame is submitted circuit;
Fig. 8 data analysis pre-process circuit;
Fig. 9 packet grasps circuit;
Figure 10 ping wraps statistical circuit;
Figure 11 flows statistical circuit;
Figure 12 cpu interface circuit.
Embodiment
This high speed test flow performance analytical equipment realizes for being sent by this tester transmit port and through equipment under test (DeviceUnder Test, DUT) the high speed test flow of Zhuan Faing receives and analyzes, thereby from test traffic, add up (Stat.) various performance index, and various satisfactory packets are grasped (Capture) according to customer requirements.This device interior employing 128bit data wire adds the form of some side informations, so the internal work clock adopts 100MHz can satisfy the requirement of the 10Gbps data being carried out real-time analysis.This equipment can comprise by the performance index that statistics obtains: port count, bag error count, routing error counting, every flow accounting, delay distribution statistics, real time delay statistics, every flow delay counting, packet loss counting, out of order bag counting, retransmission packet are counted, these performance index of utilizing this hardware circuit to obtain, upper layer software (applications) can further obtain throughput, Loss Rate, performance index such as characteristic back-to-back through handling; In addition, this equipment also can mate packet and grasps according to following user's request: IP source address and destination address, packet header protocol fields, packet length, partial data bag content.
In this equipment, for the test data fluidity can index statistics and be based on for the extracting of packet that stream label carries out.Stream label (signature) is the mark of being inserted by tester transmit leg circuit relevant with various performance index that is positioned at IP grouped data part.Its structure as shown in Figure 1.
The mentality of designing of the most of circuit module of this equipment is such: when receiving a data grouping, find respective field in stream label or the IP header according to the operation purpose, obtain some performance index in view of the above or further operate.
Whole tester system is made up of three parts: monitoring equipment (monitor), tester (tester) and equipment under test (DUT), the connection situation as shown in Figure 2.Tester is finished the basic function of test, comprises the generation of measurement, route message of the generation of test traffic and reception, test statistics and message intercepting etc.Monitoring equipment is finished control to tester by message mechanism, and be responsible for the user alternately, comprise the analysis of setting, test result of test parameter and demonstration etc.In test macro, each test interface of tester directly links to each other with each interface of test router, links to each other by the 100M Ethernet between tester and the monitoring equipment.When many testers participated in test, each tester simultaneous monitoring equipment used 100M Hub to connect, and finished co-ordination between each tester by monitoring equipment.
Tester (tester) has comprised the hardware circuit design in the whole test system, and its each integrated circuit board connection layout as shown in Figure 3.Mainboard is used to realize the generation and the analysis of test traffic; Master control borad be used to realize between each mainboard synchronously and the cascade between the tester; Backboard is responsible for the mutual of control information between each tester mainboard and the master control borad.
The tester mainboard is a most important parts in the tester, and its external interface and internal circuit configuration are as shown in Figure 4.It comprises the CPU control module, cascade circuit module, ethernet communication module (not drawing among the figure), FPGA flow generate and statistics receiver module and 10G optical interface module synchronously.
The present invention has obtained realization on the FPGA device of the Stratix of altera corp GX EP1SGX40DF1020C6 model.Be distributed in around this device and mainly be frame controller Framer chip and static memory sram chip with its peripheral chip that directly links to each other, its operational environment as shown in Figure 4.During real work, FPGA passes through the SPI4.2 interface from Framer acceptance test data traffic; Then, the test data flow in FPGA inside through analyzing step by step, thereby obtain various performance index and be stored in inner register or the inner RAM that hews out in, meet the user simultaneously and mate a part of data of requirement and be stored among the SRAM of FPGA outside after crawled.The data width of FPGA inside adopts 128bit, and the inter-process clock adopts the 100MHz clock.
Introduce data flow of the present invention in detail below in conjunction with accompanying drawing.
At first, as shown in Figure 5, the 16bit differential data of the 622MHz that meets the SPI4.2 interface specification that comes from the framer chip is received by PL4 IPCore receiver.Through the processing of PL4 IPCore receiver, the differential data of these 16bit is converted to the single-ended data-signal of 128bit, and to meet the signal form output of Atlantic interface specification.
The data shunt circuit receives data by the Atlantic interface from PL4 IPCore receiver, it is copied into two-way with data then, and one the tunnel is sent to the data analysis pre-process circuit, is used for adding up and grasping, another road is sent to protocol frame and is submitted circuit, is used for mutual between the upper-layer protocol software.The formation of this two paths of data all comprises protocol frame and Frame at first, and wherein the Frame of the existing band stream label of Frame also has the Frame of not being with stream label, and what have some encapsulation in the frame of stream label is the ping bag.
For a circuit-switched data that is sent to the data analysis pre-process circuit, as shown in Figure 8, successively the circuit structure and the corresponding process operations of process are as described below successively for these data.
Port count circuit: carry out the frame number counting and receive the byte number counting.The end mark that frame number and byte number counting logic whenever detect a frame just adds 1 with the frame number counter; Simultaneously when it whenever detects an active data word, if this data word is not the end of a frame, then byte counter is added 16 (128bit=16 bytes), otherwise byte counter is added effective word joint number in this data word.Simultaneously, data are input to the next stage circuit without change.
The protocol frame filtering circuit: this circuit-switched data is used for adding up and grasping, and therefore here protocol frame is filtered out.Frame type is differentiated the value of the protocol fields of logical foundation frame head and is judged that the frame of handling is IP Frame or protocol frame, if the IP Frame is then opened data latches and made it pass through, otherwise will not pass through.Will an only remaining IP Frame through the data after this filtering circuit processing.
Frame head stripper circuit:, the frame head of IP Frame is peeled off for further facilitating the processing of data.Two data words that will receive in succession earlier are stored in two buffers, are responsible for respectively getting two partial datas in the buffer by data word splicing control state machine then and are spliced into a new 128bit word, deliver to the next stage circuit.Form by the IP bag fully through the data after the processing of frame head stripper circuit.
Stream and Ping data markers circuit: just arrived the existing IP bag that has stream label of IP bag here, the IP bag that does not have stream label is also arranged, wherein some is the ping bag, does not have diacritics each other.Because subsequent conditioning circuit is wanted stream data (the IP bag that promptly has stream label) and the special processing of ping bag, therefore with side information they is distinguished here.Stream passes through to detect stream label and IP packet header protocol field (or next header field) with Ping discriminating data logic, screens out flow data and ping bag, and comes mark with side information str and png respectively.
Background flows through the filter circuit: background stream is differentiated logic by checking the Option field in the stream label judges whether the current IP bag belongs to background stream, if background stream then will not pass through.
The erroneous packets counting circuit: recomputate the stream label verification and with the verification of IPv4 packet header and, check whether wrong generation, if find mistake, then the erroneous packets counter adds 1; Whether simultaneously add 1bit side information chk again, being used for writing down the current IP bag is wrong bag.
The wrong counting circuit of route: the value and the local port number in DstPort territory in the stream label are compared, if do not wait, then the wrong counter of route adds 1; Add simultaneously 1bit side information mis again and export to packet extracting circuit synchronously, be used for writing down the current IP bag whether routing error takes place with the data that postpone 4 timeticks.In addition, the wrong counting circuit of this route also flows to stream statistical circuit and Ping bag statistical circuit respectively with flow data and ping bag, and the identification of flow data and ping bag decides according to the value of side information str and png respectively.
IP bag is divided into three the tunnel: the one tunnel after the wrong counting circuit output of route and is sent to packet and grasps circuit, is used for grasping according to user's request; One the tunnel is sent to the stream statistical circuit, is used for obtaining the various performance index relevant with stream; Ping bag statistical circuit is sent on another road, is used for the bag number of ping bag and delay etc. are added up.
The following introduction earlier is sent to the situation that packet grasps the IP bag of circuit, as shown in Figure 9.
At first, data are passed the IP address matcher circuit, carry out the coupling of IP address field.According to source IP address and matched rule, purpose IP address and matched rule by the CPU configuration, check source IP address and purpose IP address field in the IP packet header, on side information sip and dip, stamp respective markers respectively for the IP bag that meets matched rule.Then, data are passed packet header agreement and length field match circuit again, this circuit is checked protocol field (IPv4) or the next header field (IPv6) and the length field in IP packet header according to the matched rule of CPU configuration, wherein the length coupling is supported the coupling of two rules, therefore this process common property is given birth to 3bit side information (pro, len1 and len2).Next, data are finished the coupling of 4 user trigger rules when passing the trigger match circuit, produce 4bit side information (trig1, trig2, trig3 and trig4).A trigger is one group of matched rule, can finish the inspection of certain bits in an IP Bao one zone is compared.
Next step, data and side information thereof are input to data and grasp control circuit, and whether extracting control logic wherein grasps according to the value determination data of each side information, if decision is grasped, then allows data pass through this circuit, sends into the SRAM arbitration circuit.At last, the read request of writing SRAM request and cpu interface circuit of SRAM arbitration circuit deal with data extracting simultaneously control circuit produces correct SRAM read-write control signal.
Next introduce a circuit-switched data that is sent to the stream statistical circuit from the wrong counting circuit of route more in detail, as shown in figure 11.
In the stream statistical circuit, all IP bags all are flow datas, and these flow datas are inputed to the real time delay statistical circuit simultaneously concurrently, postpone distribution statistics circuit, every stream statistical circuit, every flow delay statistical circuit and the out of order statistical circuit of every stream.
In the real time delay statistical circuit, the timestamp in the stream label of each IP bag is extracted, and deducts timestamp with the value of local clock counter then and just obtains delay.In this circuit, whenever obtain a delay and just it is written in the 1st the stream statistics memory.
In postponing the distribution statistics circuit, the still similar foregoing length of delay that obtains, 15 that then this length of delay and CPU are configured postpone interval endpoints and compare, and draw it and belong to 0---and 15 which interval, this interval number is address, corresponding statistics memory location.This memory location from the 2nd stream statistics memory is read this interval and is postponed number then, writes back this address again after adding 1.
In every stream statistical circuit, the DstNo territory in the stream label of each IP bag is extracted, as address, corresponding statistics memory location.According to this address, IP bag number and byte number, the original position of restoring after the renewal are read in this memory location from the 3rd stream statistics memory.
In every flow delay statistical circuit, the similar foregoing length of delay that obtains, and the DstNo territory in the stream label of IP bag as address, statistics memory location accordingly.According to this address, minimum delay, maximum delay and total delay are read, the original position of restoring after the renewal in this memory location from the 4th stream statistics memory.Concrete more new approach is the minimum value of getting initial value and new length of delay the minimum delay, and maximum delay is got the maximum of initial value and new length of delay, total delay get initial value and new length of delay and.
In the out of order statistical circuit of every stream, be used as address, corresponding statistics memory location under still the DstNo territory in the stream label of IP bag being extracted, also need to extract the bag sequence number sequence territory in the stream label simultaneously.Use the windowing mechanism described in the RFC 1242,, constantly revise the 5th lost package number, retransmission packet number and the out of order bag number in the stream statistics memory in conjunction with the bag sequence number that receives bag and the window value of maintenance.
In addition, one road IP data of exporting from the wrong counting circuit of route that also have have been sent to Ping bag statistical circuit, and bag number, total delay and current delay that the ping that receives wraps are added up.
At last, at first crotch of data flow, promptly data shunt circuit place also has a circuit-switched data to be sent to protocol frame and submits circuit.As shown in Figure 7, submit circuit inside at protocol frame, data filter out the IP Frame only remaining protocol frame through protocol frame screening circuit earlier.Then, protocol frame arrives interrupt circuit, is at first deposited in the protocol frame memory, produces according to certain condition and interrupts, and request CPU handles the protocol frame of all buffer memorys.The condition that generation is interrupted is in the protocol frame memory data are arranged, and the space hold of protocol frame memory to have surpassed space threshold value or the free time since a last interrupt requests above a time threshold, just once interruption of generation.
Claims (1)
1.10G the reception of network performance tester flow, extracting and statistical circuit device is characterized in that, it is to be the extensive programmable digital integrated circuit (IC)-components that FPGA realizes with field programmable gate array, and it is made up of following each circuit part:
A:PL4 IPCore receiver is called for short the IPCore circuit, and its data input pin and the frame controller of outside are that the corresponding output end of Framer links to each other;
B: the data shunt circuit, its data input pin that is converted to the FPGA sequential links to each other with the corresponding output end of above-mentioned IP Core circuit;
C: protocol frame is submitted circuit, and its packet input links to each other with the corresponding output of above-mentioned data shunt circuit;
D: the data analysis pre-process circuit, its packet input links to each other with the corresponding output end of above-mentioned data shunt circuit, so that the packet that is received is made pretreatment operation;
E: packet grasps circuit, and its packet input links to each other with the corresponding output end of above-mentioned data analysis pre-process circuit, so that packet is grasped; Its SRAM FPDP and external SRAM corresponding port interconnection simultaneously;
F: internet information search packet protocol package is the statistical circuit of ping bag, its packet input links to each other with the corresponding output end of above-mentioned data analysis pre-process circuit, so that finish the statistical work of ping bag, comprising the statistics of overall budget number, total delay and current delay;
G: the stream statistical circuit, its data flow input links to each other with the corresponding output end of above-mentioned data analysis pre-process circuit, so that realize the statistics to the performance condition of data flow;
H: the protocol frame memory, its protocol frame input links to each other with the corresponding output end that above-mentioned protocol frame is submitted circuit;
I: totally 5 of stream statistics memories, their FPDP respectively with the corresponding port interconnection of above-mentioned stream statistical circuit;
J:CPU interface circuit, its each output grasp circuit, data analysis pre-process circuit, protocol frame with above-mentioned packet respectively and submit the corresponding output end of circuit, stream statistical circuit and link to each other; Each input of cpu interface circuit links to each other with the corresponding output end that above-mentioned packet grasps circuit, ping bag statistical circuit, stream statistical circuit, each stream statistics memory, protocol frame memory; Simultaneously, to also have a PORTX be communication interface transmitting-receiving and port external interconnect to above-mentioned cpu interface circuit;
Wherein, data shunt circuit B comprises:
B1: input register, its packet input links to each other with the corresponding output end of above-mentioned IP Core circuit;
B2: first, second output register, promptly output register 1,2, and their packet input links to each other with the corresponding output end of above-mentioned input register respectively;
Wherein protocol frame is submitted circuit C and is comprised:
C1: protocol frame screening circuit comprises:
C1a: frame type is differentiated logical circuit, and its packet input links to each other with the corresponding output end of the 2nd output register in the above-mentioned data shunt circuit;
C1b: data latches, its enable signal input, frame data input link to each other with the corresponding output end of above-mentioned frame type differentiation logical circuit respectively;
C2: valid data detect logical circuit, and its frame data input links to each other with the corresponding output end that above-mentioned protocol frame screens the data latches in the circuit;
C3: data register, its data input pin links to each other with the output that above-mentioned valid data detect logical circuit;
C4: the count enable signal that memory space counter, above-mentioned valid data detect logical circuit output is useful signal is sent to above-mentioned memory space counter after adding 1 counter a respective input, and the value that adds after 1 is sent to above-mentioned 1 counter that adds;
C5: the spatial threshold value register, its Configuration Values input links to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J;
C6: the time threshold register, its Configuration Values input links to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J;
C7: the internal clocking counter, each clock cycle counter adds 1;
C8: first comparator, its two inputs link to each other with the corresponding output end of above-mentioned spatial threshold value register, memory space counter respectively;
C9: second comparator, its two inputs link to each other with two outputs of above-mentioned time threshold register, internal clocking counter respectively;
C10: interrupt clear register, its interrupt clear signal input part links to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J; Its two reset signal outputs link to each other with the respective input of above-mentioned memory space counter, internal clocking counter respectively;
C11: the interrupt control logic circuit, its two interruptions generate signal input part and link to each other with the corresponding output end of above-mentioned first, second comparator respectively, and its interrupt clear signal input part links to each other with the corresponding output end of above-mentioned interrupt clear register;
Each circuit of above-mentioned C2～C12 is formed interrupt circuit jointly, the protocol frame of sending here from above-mentioned protocol frame screening circuit C1 is stored in above-mentioned protocol frame memory H by above-mentioned data register C3, submits to upper layer software (applications) by the interrupt requests mode of above-mentioned interrupt control logic circuit by the PORTX output of the above-mentioned cpu interface circuit of representing with J then and handle;
Wherein, above-mentioned data analysis pre-process circuit D comprises:
D1: the port count circuit is finished port statistics and forwarding of data operation, and it comprises:
D1a: frame number and byte number counting logical circuit, an input links to each other with the corresponding output end of the 1st output register in the above-mentioned data shunt circuit;
D1b: frame number counter, above-mentioned frame number links to each other with the input of this frame number counter behind one adder with the frame number value output of byte number counting logical circuit, add 1 back frame number count value and send above-mentioned frame number and byte number counting logical circuit again back to, be sent to the above-mentioned cpu interface circuit of representing with J simultaneously again;
D1c: byte number counter, the byte number output of above-mentioned frame number and byte number counting logical circuit link to each other with the input of this byte number counter after through one+α adder, and the byte number the behind+α is sent to above-mentioned frame number again and byte number is counted logical circuit; Simultaneously, be sent to the above-mentioned cpu interface circuit of representing with J again; The α value is a set point;
D2: the protocol frame filtering circuit, it filters out all protocol frames in the frame that receives, and it comprises:
D2a: frame type is differentiated logical circuit, and its input links to each other with the corresponding output end of byte number counting logical circuit with frame number in the above-mentioned port count circuit;
D2b: data latches, its data input pin links to each other with the corresponding output end of above-mentioned frame type differentiation logical circuit D2a respectively with the enable signal input;
D3: the frame head stripper circuit, it removes the PPP information frame of higher level's circuit output or mac frame frame head, comprising:
D3a: data buffer one, its input connect the output of data latches in the above-mentioned protocol frame filtering circuit;
D3b: data buffer two, its input connects the output of above-mentioned data buffer one;
D3c: data word splicing control state machine, its two inputs connect the corresponding output end of above-mentioned data buffer one, two respectively;
D4: stream and ping data markers circuit, it checks whether each packet has stream label, makes respective markers again on side information, and promptly flow label signal str and ping wrap marking signal png, and it comprises:
D4a: stream and ping discriminating data logical circuit, its input connect the corresponding output end of data word splicing control state machine in the above-mentioned frame head stripper circuit;
D4b:4 claps delay time register, and its input connects the output of above-mentioned stream and ping discriminating data logical circuit;
D5: background flows through the filter circuit, and the background stream with the option field mark in its convection tags filters, and comprising:
D5a: background stream is differentiated logical circuit, and its input links to each other with 4 outputs of clapping delay time register in the ping data markers circuit with above-mentioned stream; Simultaneously, also have two inputs and above-mentioned stream to link to each other with flow label signal str, ping bag marking signal png in the ping discriminating data logical circuit;
D5b: data latches, its data input pin, str signal input part, png signal input part link to each other with the corresponding output end that enable signal input and above-mentioned background stream are differentiated logical circuit;
D6: erroneous packets marking circuit, it carries out a verification and calculating to each IPv4 bag that receives and according to verification and whether wrong, add respective markers at this packet side information place, be verification and mark chk, correctly be 0, mistake is 1, and carries out the statistics of the bag number of bad checksum, and it comprises:
D6a: verification and inspection logical circuit, its data, str signal, png signal input part flow through the corresponding output end of filtering data latches in the circuit with above-mentioned background respectively and link to each other;
D6b: erroneous packets counter, above-mentioned verification links to each other with the input of this erroneous packets counter behind an one adder with the output of checking logical circuit, the erroneous packets number that adds after 1 is sent verification back to and is checked logical circuit, is sent to the above-mentioned cpu interface circuit of representing with J simultaneously;
D7: the routing error counting circuit, it is differentiated each packet that receives whether routing error takes place, and adds that corresponding side information is routing error mark mis, the counting of walking along the street by erroneous packets of going forward side by side; Divide data three the road to transmit simultaneously, the data that added side information are sent to next packet respectively grasp circuit, stream statistical circuit and ping bag statistical circuit; Described routing error statistical circuit comprises:
D7a: destination interface is checked logical circuit, its data input pin, str signal input part, png signal input part and chk signal input part respectively with above-mentioned erroneous packets counting circuit D6 in verification and check that the corresponding output end of logical circuit links to each other, and the local port number input of packet links to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J;
D7b: the wrong counter of route, an output of above-mentioned purpose port test logical circuit link to each other with the respective input of this erroneous packets counter after through an one adder, again the routing error bag number that adds after 1 are returned above-mentioned purpose port test logical circuit;
D7c:4 claps delay time register, and its data input pin, str signal input part, png signal input part, chk signal input part link to each other with the corresponding output end of above-mentioned purpose port test logical circuit respectively;
D7d: output latch one, its packet input, enable signal str signal input part link to each other with above-mentioned 4 corresponding output end of clapping delay time register respectively; The output of this latch one links to each other with the respective input of above-mentioned stream statistical circuit G;
D7e: output latch two, its data input pin, enable signal png signal link to each other with above-mentioned 4 corresponding output end of clapping delay time register respectively; The output of this latch two links to each other with the input of above-mentioned ping bag statistical circuit;
Wherein, above-mentioned packet grasps the data execution packet grasping manipulation that circuit is sent here the data analysis pre-process circuit, and it comprises:
The E1:IP address matcher circuit, it carries out the matching inspection of source, destination address to the input packet, and is transmitted to subordinate's circuit adding on the side information after respective markers is source address matches signal sip, matching destination address signal dip, and it comprises:
E1a:IP matching addresses logical circuit, its data input pin, verification and mark chk input link to each other with 4 corresponding output end of clapping delay time register D7c among the above-mentioned routing error counting circuit D7 respectively, and its routing error mark mis signal input part links to each other with the corresponding output end of above-mentioned purpose port test logical circuit D7a; The purpose IP address of this IP matching addresses logical circuit and matched rule, source IP address and matched rule input link to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J respectively;
E1b:3 claps delay time register, and its data input pin, chk signal input part, mis signal input part link to each other with the corresponding output end of above-mentioned IP matching addresses logical circuit respectively;
E2: packet header agreement and length field match circuit, it carries out the matching inspection of protocol number, length to the packet that receives, and be transmitted to the next stage circuit adding on the side information of packet after respective markers is protocol number matched signal pro, length 1 matched signal len1, length 2 matched signal len2, it comprises:
E2a: packet header agreement and length field match logic circuitry, its data input pin, verification and mark chk input, routing error mark mis input link to each other with 3 corresponding output end of clapping delay time register E1b among the above-mentioned IP address matcher circuit E1 respectively, and its source address matches signal sip input, matching destination address signal dip input link to each other with the corresponding output end of above-mentioned IP matching addresses logical circuit E1a respectively; Its length 1 and matched rule, length 2 and matched rule, protocol number and matched rule input link to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J respectively; So-called protocol number is meant the protocol fields of IPv4 and IPv6 heading; So-called length 1, length 2 are given message length values;
E2b:1 claps delay time register, and its data input pin, chk signal input part, mis signal input part, sip signal input part, dip signal input part link to each other with the corresponding output end of length field match logic circuitry with above-mentioned packet header agreement respectively;
E3: trigger match circuit, it is the trigger coupling that the partial content that it is chosen the packet that receives from higher level's circuit carries out trigger message, and be transmitted to the next stage circuit adding on the side information of packet after respective markers is trigger match signal trig1, trig2, trig3, trig4, it comprises:
E3a: trigger match logical circuit, its data input pin, verification and mark chk input, routing error mark mis input, source address matches mark sip input, matching destination address mark dip input link to each other with 1 corresponding output end of clapping delay time register E2b in above-mentioned packet header agreement and the length field match circuit respectively, and its other 3 side information pro, len1, len2 input link to each other with the corresponding output end of above-mentioned packet header agreement with length field match logic circuitry E2a respectively; Its 4 trigger messages be trigger1,2,3,4 and 4 inputs of corresponding matched rule link to each other with the corresponding output end of the above-mentioned cpu interface circuit of representing with J; Wherein, described len1, len2 are the side informations of expression length field, and pro is meant the side information of the next header field of the protocol field of IPv4 or IPv6, i.e. protocol number matched signal; Trig1～trig4 is 4 match information that are used for the trigger rule of expression, and wherein any trigger is one group of matched rule, finishes the inspection of particular value in an IP Bao one zone is compared;
E3b:5 claps delay time register, and its data input pin, each side information chk, mis, sip, dip, pro, len1, len2 input link to each other with the corresponding output end of above-mentioned trigger match logical circuit E3a respectively;
E4: data grasp control circuit, and whether it determines a packet should write in the external SRAM according to each the sideband mark in the extracting scheme contrasting data bag of configuration and remove generation SRAM written request signal; It comprises:
E4a: grasp control logic circuit, 5 clap delay time register E3b and link to each other in its each side information chk, mis, sip, dip, pro, len1, len2 input and the above-mentioned trigger match circuit, and other 4 side information trig1～trig4 link to each other with trigger match logical circuit E3a in the above-mentioned trigger match circuit;
E4b: data latches, its data input pin, enable signal link to each other with above-mentioned 5 corresponding output end of clapping delay time register E3b, extracting control logic circuit E4a respectively;
The E5:SRAM arbitration circuit, receive the read request of the cpu interface circuit of representing from the write request of above-mentioned extracting control circuit and the J that use by oneself simultaneously, generate and meet the sheet read-write control signal of SRAM sequential outward, wherein, read request from above-mentioned cpu interface circuit has higher priority, and it comprises:
E5a: the read-write arbitraling logic circuit, it and above-mentioned cpu interface circuit interconnect, and its another input links to each other with the corresponding output end of above-mentioned data latches E4b, this read-write arbitraling logic circuit interconnects with the outer SRAM of sheet again;
Wherein, the statistics of the delay of overall budget number, total delay and last bag of the statistical circuit realization ping packet of ping bag, it comprises:
F1: packet detects logical circuit;
F2: postpone the extraction logic circuit;
The input of these two circuit of F1, F2 respectively with above-mentioned data analysis pre-process circuit in the routing error counting circuit two outputs of output register two link to each other;
F3:ping bag number register, its input links to each other with the output that above-mentioned packet detects logical circuit;
F4: total delay register, the result of its storage total delay statistics;
F5: adder, its two inputs connect the corresponding output end that postpones extraction logic circuit and total delay register respectively, and the output of this adder links to each other with the input of total delay register;
F6: current delay time register, its input links to each other with the output of above-mentioned delay extraction logic circuit;
Wherein, the stream statistical circuit, it comprises:
G1: every flow delay statistical circuit, it adds up and gives record to the every stream packets transmission delay that comprises maximum delay, minimum delay and total delay, reads for the cpu interface circuit of representing with J, and it comprises:
G1a: in the stream numbering extraction logic circuit, its data input pin and above-mentioned data analysis pre-process circuit in the routing error counting circuit output of output register one link to each other;
G1b: postpone the extraction logic circuit, the input of its input and above-mentioned stream numbering extraction logic circuit is and connects;
G1c: total delay register;
G1d: adder, its two inputs link to each other with the output of above-mentioned delay extraction logic circuit and total delay register respectively;
G1e: maximum delay register;
G1f: comparator one, its two inputs link to each other with each output that postpones the extraction logic circuit with above-mentioned maximum delay register respectively;
G1g: minimum delay register;
G1h: comparator two, its two inputs link to each other with each output that postpones the extraction logic circuit with above-mentioned minimum delay register respectively;
G1i:2 circuit-switched data selector one, its two inputs link to each other with each output that postpones the extraction logic circuit with above-mentioned maximum delay register respectively;
G1j:2 circuit-switched data selector two, its two inputs link to each other with each output that postpones the extraction logic circuit with above-mentioned minimum delay register respectively;
G1k: write data register, its three inputs link to each other with the output of above-mentioned adder with two data selectors one, two respectively;
G1l: read data register, its data-out port links to each other with the input of above-mentioned total delay register, maximum delay register, minimum delay register;
G1m: the read/write address register, its data input pin links to each other with the output of above-mentioned stream numbering extraction logic circuit;
G2: the out of order statistical circuit of every stream, it adds up the number of dropped packets of every stream, out of order and retransmission count information, and the storage statistics, reads for the cpu interface circuit of representing with J, and it comprises:
G2a: in the stream numbering extraction logic circuit, its data input pin and above-mentioned data analysis pre-process circuit in the routing error counting circuit output of output register one link to each other;
G2b: bag sequence number extraction logic circuit, the input of its data input pin and above-mentioned stream numbering extraction logic circuit G2a also connects;
G2c: lost package number register;
G2d: retransmission packet number register;
G2e: out of order bag number register;
G2f:RFC1242 windowing mechanism controller, its 4 inputs respectively with above-mentioned bag sequence number extraction logic circuit
The output of G2b and lost package, retransmission packet, each number register of out of order bag links to each other;
G2g: write data register, its input links to each other with the output of above-mentioned RFC1242 windowing mechanism controller;
G2h: read data register, its data output end links to each other with the input of above-mentioned lost package, retransmission packet, each number register of out of order bag;
G2i: the read/write address register, its data input pin links to each other with the output of above-mentioned stream numbering extraction logic circuit G2a;
G3: the real time delay statistical circuit, it decides according to option territory in the stream label which bar stream is carried out the real time delay statistics, and stores corresponding statistics, reads for the cpu interface circuit of representing with J, and it comprises:
G3a: postpone the extraction logic circuit, in its data input pin and the above-mentioned data analysis pre-process circuit in the routing error counting circuit output of output register one link to each other;
G3b: delay time register, its input links to each other with the output of above-mentioned delay extraction logic circuit;
G3c: write data register, its input links to each other with the output of above-mentioned delay time register;
G3d: next address register;
G3e: writing address register, its input links to each other with the output of above-mentioned next address register, and its output links to each other with the input of above-mentioned next address register after through an one adder, the value that adds after 1 is returned this writing address register;
G4: postpone the distribution statistics circuit, it does the delay distribution statistics according to option territory decision in the stream label to which bar stream, and statistics storage and the cpu interface circuit that supplies to represent with J read, and it comprises:
G4a: postpone the extraction logic circuit, in its data input pin and the above-mentioned data analysis pre-process circuit in the routing error counting circuit output of output register one link to each other;
G4b: 15 outputs that postpone the interval endpoint registers of the cpu interface circuit that data comparison circuit, its two inputs are represented with above-mentioned delay extraction logic circuit G4a, with J respectively link to each other;
G4c: the read/write address register, its input links to each other with the output of above-mentioned data comparison circuit G4b;
G4d: postpone a number register in interval;
G4e: read data register, its data output end links to each other with the input of a delay number register in the above-mentioned interval;
G4f: write data register, its data input pin links to each other with the output of a delay number register in the above-mentioned interval;
G5: every stream statistical circuit, the data that comprise every stream byte number, overall budget number that its statistics receives, and store for the cpu interface circuit of representing with J and read, it comprises:
G5a: in the stream numbering extraction logic circuit, its data input pin and above-mentioned data analysis pre-process circuit in the routing error counting circuit output of output register one link to each other;
G5b: byte number register;
G5c: bag number register;
G5d: read data register, its two data outputs link to each other with the input of above-mentioned byte number register, bag number register respectively;
G5e: write data register, the output valve of above-mentioned bag number register adds the input that is sent to this write data register after 1, and the output valve of above-mentioned byte number register adds the input that is sent to this write data register behind the α;
G5f: the read/write address register, its input links to each other with the output of above-mentioned stream numbering extraction logic circuit G5a;
Wherein, 5 stream statistics memory I, it respectively with above-mentioned every flow delay statistical circuit in, in the out of order statistical circuit of every stream, postpone in the distribution statistics circuit and in every stream statistical circuit the input of read data register link to each other, and link to each other with their write data register, each output of read/write address register; The input of these 5 stream statistics memories also links to each other with each output of write data register, writing address register in the above-mentioned real time delay statistical circuit;
Wherein, cpu interface circuit represents that with J it instructs according to outer CPU and finishes the configuration of each configuration register and the submission of each statistics, and it comprises:
The J1:CPU address register;
J2:CPU control signal register;
The ternary scheduling logic circuit of J3:CPU data/address bus, its input links to each other with the output of above-mentioned CPU control signal register;
Foregoing circuit J1～J3 links to each other with the outer CPU corresponding output end respectively;
J4: address decoder, its input links to each other with the output of above-mentioned cpu address register;
J5: status register group, its input links to each other with frame number counter D1b, byte counter D1c, erroneous packets counter D6b, each output of the wrong counter D7b of route in the above-mentioned data analysis pre-process circuit respectively, and its input also links to each other with ping each output of wrapping number register F3, total delay register F4, current delay time register F6 in the above-mentioned ping bag statistical circuit;
J6: groups of configuration registers, its each output are connected respectively to above-mentioned packet and grasp each continuous input that circuit, data analysis pre-process circuit, protocol frame are submitted circuit, stream statistical circuit;
J7: the external SRAM data register, its input links to each other with the SRAM arbitration circuit that packet grasps circuit;
J8: stream statistics memory data register group, its each input link to each other with each output of above-mentioned 5 stream statistics memories respectively;
J9: the protocol frame memory data register, its each input links to each other with the output of above-mentioned protocol frame memory;
Each output of above-mentioned address decoder J4 links to each other with the input of above-mentioned each circuit of J5～J9 respectively; Each input of the ternary scheduling logic circuit of above-mentioned cpu data bus links to each other with each output of above-mentioned status register group, external SRAM data register and protocol frame memory data register respectively; Simultaneously, interconnect with above-mentioned stream statistics memory data register group again; Its output then links to each other with the input of above-mentioned groups of configuration registers.
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