CN1687867A - Method for regulating internal storage frequency - Google Patents
Method for regulating internal storage frequency Download PDFInfo
- Publication number
- CN1687867A CN1687867A CN 200510072999 CN200510072999A CN1687867A CN 1687867 A CN1687867 A CN 1687867A CN 200510072999 CN200510072999 CN 200510072999 CN 200510072999 A CN200510072999 A CN 200510072999A CN 1687867 A CN1687867 A CN 1687867A
- Authority
- CN
- China
- Prior art keywords
- frequency
- north bridge
- bridge chips
- random access
- adjusted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Power Sources (AREA)
Abstract
The invention relates to an internal memory frequency regulating method, applied to a CPU, a north bridge chip connected with the CPU and a RAM connected with the north bridge chip in a computer system, and comprising the steps of: responding to the change of the operating frequency of the CPU, that of the work load of the north bridge chip, or that of a set value in a software program executed by the user in the computer system, so as to regulate the operating frequency of data access between the north bridge and the RAM.
Description
Technical field
The present invention relates to the method that a kind of clocked memory is adjusted, relate in particular to a kind of north bridge chips in computer system and method for adjustment of random access memory frequency of operation between the two of being applied to.
Background technology
The motherboard of the general computer system of now being sold on the market, its basic comprising mainly is by CPU (central processing unit) (Central Processing Unit, abbreviation CPU), chipset (chipset) and some peripheral circuits are formed, its CPU (central processing unit) is the core place of whole computer system, most principal work be handle and control whole computer system each partly between each other operation, and the computing of carrying out logic; Chipset then is the operation of being responsible between contact CPU (central processing unit) and other interfacing equipment, the combination of chipset also has many different modes, be with north bridge (North Bridge at present, NB) chip and south bridge (South Bridge, SB) chip, the chipset that this two chips constituted is the present common practice of most manufacturer on the market, difference according to function, wherein north bridge chips is responsible for the bus (bus) of high speeds all on the contact. host plate, and South Bridge chip then is responsible in the coupled system part more at a slow speed.
See also Fig. 1 (a), it is the wiring diagram of each arrangement of components on the motherboard 1.Thus shown in the figure as can be known this motherboard 1 be with the framework of single CPU (central processing unit) 10 as system, and form a chipset 2 by a north bridge chips 20 and a South Bridge chip 21, this north bridge chips 20 is by a preposition bus (FrontSide Bus, FSB) 22 and this CPU (central processing unit) 10 get in touch, generally speaking, the frequency of this preposition bus 22 is just can be used under common the support by this CPU (central processing unit) 10 and this north bridge chips 20, and on this motherboard 1, other has an AGP (Accelerated Graphics Port, AGP) interface 30 is via an AGP bus 301, with a random access memory (Random Access Memory, RAM,) 31 via a rambus 311, be linked to separately on this north bridge chips 20.In this Fig. 1 (a) as can be known, one perimeter component links (Peripheral Component Interconnect, PCI) interface 40 links via a pci bus 401 and this South Bridge chip 21, in addition and this South Bridge chip 21 link also have parts more at a slow speed such as an ISA (Industry Standard Architecture) interface 41, an IDE (Integrated DriveElectronics) interface 42, a USB (Universal Serial Bus) interface 43, a keyboard 44 and a mouse 45.
Therefore, chipset 2 is control maincenters of whole computer system as can be known, because this chipset 2 is to be responsible for getting in touch with this CPU (central processing unit) 10, and links with other interfacing equipment, for example: random access memory 31 is carried out the action of access (access).And this north bridge chips 20 in this chipset 2 more can be described as core wherein, because north bridge chips 20 is between this CPU (central processing unit) 10 and random access memory 31, and any signal in computer system or the instruction be read, when carrying out, all need be via the processing and the judgement of CPU (central processing unit) 10, with utilize the space among the random access memory 31 and do the temporary of data, therefore, this north bridge chips 20 just becomes the part of compiling that various signals on each bus are made access action.In addition, part about internal memory, common kind and module has now: DRAM (Dynamic Random Access Memory, DRAM (Dynamic Random Access Memory)), SRAM (Static Random Access Memory, static random access memory), DIMM (DualIn-line Memory Module, DIMM), SDRAM (Synchronous DRAM, SDRAM (Synchronous dynamic random access memory)), DDR SDRAM (Double Data Rate SDRAM, synchronous double data transmit DRAM (Dynamic Random Access Memory)), or DIMM SDRAM or the like.
See also Fig. 1 (b), it is the inter-process synoptic diagram of this north bridge chips 20.Therefore, from the above, in north bridge chips 20, just to be provided with respectively: to the central processing unit controls device (CPU controller) 201 of this CPU (central processing unit) 10, to the Memory Controller Hub (DRAM controller) 202 of this random access memory 31, to the AGP controller (AGP controller) 203 of this AGP interface 30, and to a South Bridge chip controller (SBcontroller) 204 of this South Bridge chip 21.Because any signal is when carrying out writing (write), read (read) or refreshing the action of (refresh) of data via north bridge chips 20 to this random access memory 31, be to do access in the mode of stroke by stroke data, so must pass through this Memory Controller Hub 202 earlier, can reach the sequence arrangement of data access.
Yet, determine which can be introduced into this Memory Controller Hub 202 and does access from the signal of different interface devices for these, be to make decision by a flow controller (trafficcontroller) 205 that is arranged at these north bridge chips 20 inside.So, if each assembly in these computer systems, its the position (bits) of the treatment efficiency that can reach or speed, frequency (MHz) higher (for example: each data access can reach 64bits or frequency can reach the above CPU (central processing unit) of 1GHz), and when having the several data needs pending, the data traffic of bus therebetween also will heal greatly, and cause the too much thermal value of this north bridge chips 20, so that computer system height power consumption; Otherwise, under the performance usefulness that does not change original each assembly (for example: CPU (central processing unit) is (can be described as CPUthrottling again) such as measures that can make to reduce frequency), data or signal pending on its each bus are less and not busy, but be still with the position or the speed of higher performance and handling, when transmitting, then equally also can cause the unnecessary power consumption of computer system.
For instance, the mobile computer of generally carrying all possesses TunePower, in the use that external power supply is arranged simultaneously, just can charge to its battery, but, if mobile computer is under the operating position of no external power supply, then battery wherein is unique power supply unit, so the energy measure of the province of variety of way will be an important problem very.So, how in the correctness that does not influence the data transmission of each inter-module in the computer system, and can bring into play the original usefulness of this computer system itself again, and can save the energy resource consumption situation in its computer system, be the fundamental purpose that the present invention develops.
Summary of the invention
A purpose of the present invention is the method that a kind of clocked memory is adjusted, be applied to a CPU (central processing unit), electrical ties in the computer system in a north bridge chips of this CPU (central processing unit), with the random access memory of electrical ties in this north bridge chips, this method comprises the following step: this CPU (central processing unit) operates on the first frequency, and carries out data access with a second frequency between this north bridge chips and this random access memory; And the variation that responds this first frequency that this CPU (central processing unit) moves, and adjust this second frequency that carries out data access between this north bridge chips and this random access memory.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein the variation of this first frequency can surpass the waiting time that this computer system sets because of user's operation is idle, this computer system is the energy profit and loss of adjusting hardware, and this first frequency that this CPU (central processing unit) is moved is adjusted.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein this CPU (central processing unit) can be adjusted to half of original frequency to the adjustment that this first frequency that it moved carries out, or is lower than the specification of original frequency.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein when this second frequency adjustment of carrying out data access between this north bridge chips and this random access memory is finished, can make this computer system enter the start selftest stage of one among the Basic Input or Output System (BIOS), and the delay that utilizes data and/or data controlling signal is imported and/or the technology of output, this second frequency that adjustment is finished is detected and is calibrated, and the result that adjustment is finished stores into a new setting recording among this Basic Input or Output System (BIOS) simultaneously.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein carry out the adjustment of this second frequency of data access between this north bridge chips and this random access memory, can be adjusted to half of original frequency, or be lower than the specification of original frequency.
Another object of the present invention is the method that a kind of clocked memory is adjusted, be applied to the north bridge chips in the computer system, with the random access memory of electrical ties in this north bridge chips, this method comprises the following step: carry out data access with a first frequency between this north bridge chips and this random access memory; And the variation that responds the workload of this north bridge chips, and this first frequency that carries out data access between this north bridge chips and this random access memory is adjusted.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein the variation of the workload of this north bridge chips can be and utilizes a temperature sensor of being located at this inside computer system, when moving, carry out the sensing of temperature at this north bridge chips, and when showing bigger overheated of this north bridge chips generation workload, and this first frequency that carries out data access between this north bridge chips and this random access memory is adjusted because of its sensed temperature.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein the variation of the workload of this north bridge chips can be and utilizes a flow controller of being located at this north bridge chips inside, when moving, carry out data stream quantitative analysis on its bus at this north bridge chips, and when showing less idle of this north bridge chips generation workload, and this first frequency that carries out data access between this north bridge chips and this random access memory is adjusted because of the data traffic of its analysis.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein when this first frequency adjustment of carrying out data access between this north bridge chips and this random access memory is finished, can make this computer system enter the start selftest stage of one among the Basic Input or Output System (BIOS), and the delay that utilizes data and/or data controlling signal is imported and/or the technology of output, this second frequency that adjustment is finished is detected and is calibrated, and the result that adjustment is finished stores into a new setting recording among this Basic Input or Output System (BIOS) simultaneously.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein carry out the adjustment of this first frequency of data access between this north bridge chips and this random access memory, can be adjusted to half of original frequency, or be lower than the specification of original frequency.
Another purpose of the present invention is the method that a kind of clocked memory is adjusted, be applied to the north bridge chips in the computer system, with the random access memory of electrical ties in this north bridge chips, this method comprises the following step: carry out data access with a first frequency between this north bridge chips and this random access memory; And respond the change of user, and then this first frequency that carries out data access between this north bridge chips and this random access memory is adjusted a setting value in the software program performed in this computer system.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein this setting value in this software program can be for being changed by the user voluntarily, and can therefore be decided by to utilize this computer system to be carried out this software program when which kind of condition takes place, and this first frequency that carries out data access between this north bridge chips and this random access memory is adjusted.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein when this first frequency adjustment of carrying out data access between this north bridge chips and this random access memory is finished, can make this computer system enter the start selftest stage of one among the Basic Input or Output System (BIOS), and the delay that utilizes data and/or data controlling signal is imported and/or the technology of output, this second frequency that adjustment is finished is detected and is calibrated, and the result that adjustment is finished stores into a new setting recording among this Basic Input or Output System (BIOS) simultaneously.
According to above-mentioned conception, the method that clocked memory of the present invention is adjusted, wherein carry out the adjustment of this first frequency of data access between this north bridge chips and this random access memory, can be adjusted to half of original frequency, or be lower than the specification of original frequency.
The present invention gets a more deep understanding by following accompanying drawing and detailed description.
Description of drawings
Fig. 1 (a) is the wiring diagram of each arrangement of components on the motherboard.
Fig. 1 (b) is the inter-process synoptic diagram of north bridge chips.
Fig. 2 is applied in the configuration of each assembly in the computer system and the inter-process synoptic diagram of north bridge chips.
Fig. 3 (a) and Fig. 3 (b) are the process flow diagram of first preferred embodiment of the present invention.
Fig. 4 (a) and Fig. 4 (b) are the process flow diagram of second preferred embodiment of the present invention.
Fig. 5 (a) and Fig. 5 (b) are the process flow diagram of the 3rd preferred embodiment of the present invention.
Wherein, description of reference numerals is as follows:
1 motherboard, 10,50 CPU (central processing unit)
20,60 north bridge chips, 21,61 South Bridge chips
2 chipsets, 22,62 preposition buses
201,601 central processing unit controls devices, 202,602 Memory Controller Hub
203,603 AGP controllers, 204,604 South Bridge chip controllers
205,605 flow controllers, 30,70 AGP interfaces
301,701 AGP buses, 31,71 random access memorys
311,711 rambus, 40 pci interfaces
401 pci buss, 41 ISA interfaces
42 ide interfaces, 43 USB interface
44 keyboards, 45 mouses
Embodiment
See also Fig. 2, it is to be applied in the configuration of each assembly in the computer system and the inter-process synoptic diagram of a north bridge chips 60.In this computer system, mainly have as can be known shown in the figure thus: a CPU (central processing unit) 50, electrical ties in this north bridge chips 60 of this CPU (central processing unit) 50 and electrical ties in a random access memory 71 of this north bridge chips 60.And it is same, this north bridge chips 60 is also got in touch by a preposition bus 62 and this CPU (central processing unit) 50, in addition, have respectively an AGP interface 70 via an AGP bus 701 and a random access memory 71 via a rambus 711, be linked to separately on this north bridge chips 60, simultaneously, a South Bridge chip 61 of responsible processing assembly more at a slow speed also links with this north bridge chips 60.
By the explanation in the prior art as can be known, in order to determine which can be introduced into the access that this random access memory 71 is made data from the signal of different interface devices for these, just need be provided with a flow controller 605 in these north bridge chips 60 inside and be controlled.Therefore, these north bridge chips 60 inside just are respectively equipped with: a central processing unit controls device 601, an one AGP controller 603 and a South Bridge chip controller 604, handle and control these respectively from this CPU (central processing unit) 50, all signals of AGP interface 70 and this South Bridge chip 61, and decide these signals will make the sequencing of data access by this flow controller 605, and after earlier in turn advancing in the Memory Controller Hub 602 in this north bridge chips 60, in turn this random access memory 71 is carried out writing of data again with the mode access of data stroke by stroke, the action of reading or refreshing.
Equally, as the explanation in the prior art, if the performance usefulness of these assemblies in this computer system is high more, for example position or the speed, frequency that can handle heal high, this relative computer system also has than higher power consumption rate, sometimes even can be, and cause the execution usefulness of this computer system integral body to descend, also or cause the overheated of nextport hardware component NextPort and undermine its serviceable life because pending data traffic is excessive.Yet, do some suitable adjustment if this computer system can be in due course, for example: change some ongoing frequency of operation of associated component institute etc., then can improve the power consumption situation of computer system on the one hand, can also promote the execution usefulness of computer system integral body on the other hand.Therefore, the present invention is based on above-mentioned notion, proposes a more appropriate solution at this type of problem further again.
Therefore, in first preferred embodiment of the present invention, at first be that this CPU (central processing unit) 50 is operated on the first frequency, and carry out data access with a second frequency between this north bridge chips 60 and this random access memory 71, then, respond the variation of this first frequency that this CPU (central processing unit) 50 moved, and adjust this second frequency that carries out data access between this north bridge chips 60 and this random access memory 71.Because this CPU (central processing unit) 50 is to do the signal transmission by this preposition bus 62 and this north bridge chips 60, therefore as long as this CPU (central processing unit) 50 and this north bridge chips 60 are words with a common frequency of operation doing in the signal exchange, correct switching signal just, and change, adjustment that the usefulness that this CPU (central processing unit) 50 still can self be set during other is come working frequency.
So from the above; in this first preferred embodiment; the frequency of this CPU (central processing unit) 50 self promptly is set at this first frequency; and the variation of this first frequency can be for instance because the user is left unused under operating system and surpassed the waiting time that general computer system sets; and this computer system usually can be in order to regulate the energy profit and loss of its hardware; just this first frequency that this CPU (central processing unit) 50 is moved carries out the adjustment measure (being so-called CPU throttling) of a reduction frequency; for example: the former CPU (central processing unit) 50 that operated in 1GHz before this; in order to save power consumption; it can be adjusted into half of original frequency; i.e. adjustment operates on the 500MHz, or is brought down below other specification of original frequency.
Because computer system is before each start enters operating system the time, can be introduced into BIOS (BasicInput Output System, Basic Input or Output System (BIOS)) setting, can detect at the initial set value of each nextport hardware component NextPort, but to guarantee the assembly operate as normal, (the Power-On SelfTest of POST especially therein, the start selftest) stage, be the performed testing process of BIOS, can set according to the initial value in the BIOS, automatically each assembly in the detection system; Just generally speaking, POST in the stage we can use one " data (and Data; DQ) and/or data controlling signal (Data Strobe; DQS) delay input and/or output (input/output) " detection and collimation technique, come the clock pulse (clock) of each inter-module institute input and output signal is carried out its phase place (phase) calibration.Because can select the clock pulse of each assembly in this stepped reckoner system is state at intermittent neutral gear, be be idle (idie) on its bus, do not have to calibrate under the state of circulation (cycle) output of access data, therefore just can be to its phase differential that may exist between the two of institute's input and output signal, its calibration is become same-phase (in phase), and synchronous input and output also just can be guaranteed the correctness of data access, to avoid data the situation of erroneous judgement take place when the access.So, under normal condition, computer system start enter the POST stage during, just can detect the original frequency of operation moved between this north bridge chips 60 and this random access memory 71 and the phase differential of its clock pulse, and the calibration of pulse-phase potential difference at that time can be become after the clock pulse same-phase, in BIOS, save as an original start record, make when entering user's operating system can be correct operation.
Therefore, the inventive features of the present invention's first preferred embodiment is to be: respond the possible situation of change of this first frequency that aforesaid this CPU (central processing unit) 50 moved, and adjust this second frequency that carries out data access between this north bridge chips 60 and this random access memory 71.Coordinate when adjusting a new second frequency when this north bridge chips 60 and this random access memory 71 are common, we just again enter this computer system the POST stage among the BIOS, to reactivate this detection and the function of calibrating, promptly with the technology of this " delay of data and/or data controlling signal input and/or output ", the action that this new second frequency that is adjusted is detected and calibrates, make this north bridge chips 60 and this random access memory 71 can correctly carry out the synchronous signal access of clock pulse between the two with this new second frequency between the two; And, in BIOS, store into a new setting recording with this new calibration result.At last, finish this detection and calibration function in BIOS, this north bridge chips 60 and this random access memory 71 just move with this new second frequency between the two, continue to enable user's operating system simultaneously.In addition, this new second frequency also can be adjusted to half of original frequency, and for instance, this adjustment can become the DDR of new frequency 200MHz from original frequency for DDR 400MHz downgrades; And according to the common technology in present the technology of the present invention field, same, except frequency is reduced to half of original frequency, it can certainly be adjusted into the specification that other is lower than original frequency.
Therefore, as mentioned above, utilize the inventive method therefore can respond this CPU (central processing unit) 50 smoothly when carrying out self reducing the adjustment measure of frequency, also side by side can be with the downgrading in the lump of the frequency of operation between this north bridge chips 60 and this random access memory 71, thus success reached of the present invention in order to improve power consumption of computer systems situation and the purpose of saving the energy.
And in second preferred embodiment of the present invention, at first be to make between this north bridge chips 60 and this random access memory 71 to carry out data access with a first frequency, then respond the variation of the workload of this north bridge chips 60, and this first frequency that carries out data access between this north bridge chips 60 and this random access memory 71 is adjusted.Therefore, in this second preferred embodiment, the frequency of operation between this north bridge chips 60 and this random access memory 71 promptly is set at first frequency, and the adjustment of this first frequency is the variation according to the workload of this north bridge chips 60.Because in computer system, the reason workload of living in of each assembly, data volume, or the speed that shows, usefulness, or even the temperature that produces etc., can reflect the state whether this assembly is in busy (busy) certain degree, monitoring via relevant inductor can allow computer system judge and analysis, and the judgement whether state has much to do will help the lifting of this computer system overall efficiency.
So from the above, in this second preferred embodiment, for the variation of the workload of this north bridge chips 60, we can utilize a temperature sensor of being located at this inside computer system, carry out the sensing of temperature when the operation at this north bridge chips 60.If it is less comparatively speaking to work as workload, and sensed temperature demonstrates this north bridge chips 60 for just often, then this computer system remains and can move according to these random access memory 71 best efficiencies own, in the hope of making fast, the most maximum data processing; If but when workload be relative when excessive, sensed temperature just may demonstrate this north bridge chips 60 overheated situation takes place, and for fear of undermining assembly, just this first frequency is carried out the adjustment that frequency reduces, for example: can come down to DDR 200MHz from DDR 400MHz, make this north bridge chips 60 can temporarily reduce data volume to be processed, thereby situation that can assembly own is overheated is got rid of.
In addition,, also can utilize this flow controller 605 of these north bridge chips 60 inside, carry out data stream quantitative analysis on its bus when the operation at this north bridge chips 60 for the variation of the workload of this north bridge chips 60.When the event data stream amount does not exceed the default load of assembly comparatively speaking, then remain equally and can move according to these random access memory 71 best efficiencies own, if show its workload seldom but work as the data traffic of being analyzed, even when reaching a default idle state, then similarly in order to reach the purpose of saving the energy, we just can carry out this first frequency the adjustment that frequency reduces, and the adjustment of this first frequency can also be adjusted into it specification that other is lower than original frequency except coming down to half of original frequency.
And its inventive features of second preferred embodiment of the present invention is to be: respond this north bridge chips 60 possible variations of aforesaid workload own, and then this first frequency that carries out data access between this north bridge chips 60 and this random access memory 71 is adjusted.And in first preferred embodiment same technology, also be applied in this second preferred embodiment, promptly be to testing process that first frequency carries out new after adjusting and this part of calibration process, its practice is identical with this first preferred embodiment.
Therefore, as mentioned above, when utilizing the inventive method therefore can respond the variation of these north bridge chips 60 generation workloads smoothly, also side by side can be with the adjusting in the lump of the frequency of operation between this north bridge chips 60 and this random access memory 71, thus success reached of the present invention in order to improve power consumption of computer systems situation and the purpose of saving the energy.
In addition, in the 3rd preferred embodiment of the present invention, at first be to make between this north bridge chips 60 and this random access memory 71 to carry out data access with a first frequency, and respond the change of user, and then this first frequency that carries out data access between this north bridge chips 60 and this random access memory 71 is adjusted a setting value in the software program performed in this computer system.Therefore, in this 3rd preferred embodiment, the frequency of operation between this north bridge chips 60 and this random access memory 71 promptly is set at first frequency, and the adjustment of this first frequency is the change according to the setting value in this software program.Because among first preferred embodiment and second preferred embodiment, the situation that its mechanism of adjusting institute's foundation is nextport hardware component NextPort changes, for example: the overheated or nextport hardware component NextPort of nextport hardware component NextPort is being adjusted etc., yet the change that is produced on these hardware levels, all be detecting and carrying out of hardware active itself, unless having under the situation of special instruction, the change of this respect be can't by the program setting on the software can Detection ﹠ Controling obtain; So, with regard to complete considering, except on hardware, possessing the mechanism of response to some extent, hardware can be carried out on one's own initiative outside the frequency adjustment, we also need suitable application conditions on software program, the user also can be set by own desirable situation, regulate the effective utilization of using each assembly in this computer system.
So from the above, in this 3rd preferred embodiment, wherein this setting value in this software program can be for being changed by the user voluntarily, and can therefore be decided by to utilize this computer system to be carried out this software program when which kind of condition takes place, and this first frequency that carries out data access between this north bridge chips 60 and this random access memory 71 is adjusted.For instance: general mobile computer is in order to save power consumption, can be designed in user's operating environment, carry out a software program with Power Supply Monitoring function, and visual oneself the operating efficiency demand of user, change setting value wherein voluntarily, in the hope of wherein internal memory will being moved with optimized frequency of operation itself, or only need give play to its half operation usefulness and got final product.
And its inventive features of the 3rd preferred embodiment of the present invention is to be: the user is to performed aforesaid this software program in this computer system in response, the wherein possible change of a setting value, and then this first frequency that carries out data access between this north bridge chips 60 and this random access memory 71 adjusted.And same, to testing process that first frequency carries out new after adjusting and this part of calibration process, its practice also is same as this first and second preferred embodiment.
Therefore, as mentioned above, utilize the inventive method therefore can respond the change of a setting value in this software program smoothly, also side by side can be with the adjusting in the lump of the frequency of operation between this north bridge chips 60 and this random access memory 71, thus success reached of the present invention in order to improve power consumption of computer systems situation and the purpose of saving the energy.
See also Fig. 3 (a) and Fig. 3 (b), it is the process flow diagram of first preferred embodiment of the present invention.In Fig. 3 (a), at first computer system enters the POST stage among the BIOS, to enable the function that detects with calibration, and to the CPU (central processing unit) in the computer system 50 with the operation first frequency, and between north bridge chips 60 and the random access memory 71 the second frequency of operation is detected and calibrates, in BIOS, store into simultaneously an original start record; Secondly, computer system determines that just when entering user's operating system, CPU (central processing unit) 50 will operate on the first frequency, and will carry out data access with second frequency between north bridge chips 60 and the random access memory 71; Then, computer system just enters user's operating system.In Fig. 3 (b), at first be the person's of bringing into use operating system then, CPU (central processing unit) 50 operates on the first frequency, and carries out data access with second frequency between north bridge chips 60 and the random access memory 71; Secondly, if first frequency changes, north bridge chips 60 and random access memory 71 are just coordinated jointly and are adjusted the second frequency that makes new advances; Then, computer system just enters the POST stage among the BIOS, reactivating the function that detects with calibration, with to the adjusted action that the second frequency that makes new advances detects and calibrates, and stores into a new setting recording with this new calibration result in BIOS; At last, finish detection and calibration function in BIOS, north bridge chips 60 and random access memory 71 just move with new second frequency between the two, continue to enable user's operating system simultaneously.
See also Fig. 4 (a) and Fig. 4 (b), it is the process flow diagram of second preferred embodiment of the present invention.In Fig. 4 (a), at first computer system enters the POST stage among the BIOS, to enable the function that detects with calibration, and between north bridge chips in the computer system 60 and the random access memory 71, the first frequency of operation is detected and calibrates, in BIOS, store into simultaneously an original start record; Secondly, computer system just determines when entering user's operating system, will carry out data access with first frequency between north bridge chips 60 and the random access memory 71; Then, computer system just enters user's operating system.In Fig. 4 (b), at first be the person's of bringing into use operating system then, carry out data access with first frequency between north bridge chips 60 and the random access memory 71; Secondly, if north bridge chips 60 produces the bigger overheat condition of workload, or the less idle situation of data traffic, north bridge chips 60 and random access memory 71 are just coordinated jointly and are adjusted the first frequency that makes new advances; Then, computer system just enters the POST stage among the BIOS, reactivating the function that detects with calibration, with to the adjusted action that the first frequency that makes new advances detects and calibrates, and stores into a new setting recording with this new calibration result in BIOS; At last, finish detection and calibration function in BIOS, north bridge chips 60 and random access memory 71 just move with new first frequency between the two, continue to enable user's operating system simultaneously.
See also Fig. 5 (a) and Fig. 5 (b), it is the process flow diagram of the 3rd preferred embodiment of the present invention.In Fig. 5 (a), at first computer system enters the POST stage among the BIOS, to enable the function that detects with calibration, and between north bridge chips in the computer system 60 and the random access memory 71, the first frequency of operation is detected and calibrates, in BIOS, store into simultaneously an original start record; Secondly, computer system just determines when entering user's operating system, will carry out data access with first frequency between north bridge chips 60 and the random access memory 71; Then, computer system just enters user's operating system.In Fig. 5 (b), at first be the person's of bringing into use operating system then, carry out data access with first frequency between north bridge chips 60 and the random access memory 71; Secondly, as if the mutagenic situation of a setting value in the software program performed in the computer system, north bridge chips 60 and random access memory 71 are just coordinated jointly and are adjusted the first frequency that makes new advances; Then, computer system just enters the POST stage among the BIOS, reactivating the function that detects with calibration, with to the adjusted action that the first frequency that makes new advances detects and calibrates, and stores into a new setting recording with this new calibration result in BIOS; At last, finish detection and calibration function in BIOS, north bridge chips 60 and random access memory 71 just move with new first frequency between the two, continue to enable user's operating system simultaneously.
Therefore, by the above as can be known, we have successfully reached development fundamental purpose of the present invention, but the present invention must appoint by those skilled in the art and execute the craftsman and think and do some and modify, however the scope of neither disengaging patent of the present invention institute desire protection.
Claims (10)
1. the method adjusted of a clocked memory, be applied to a CPU (central processing unit), electrical ties in the computer system in a north bridge chips of this CPU (central processing unit) and electrical ties in a random access memory of this north bridge chips, this method comprises the following step:
This CPU (central processing unit) operates on the first frequency, and carries out data access with a second frequency between this north bridge chips and this random access memory; And
Respond the variation of this first frequency that this CPU (central processing unit) moves, and adjust this second frequency that carries out data access between this north bridge chips and this random access memory.
2. the method that clocked memory according to claim 1 is adjusted, wherein the variation of this first frequency can surpass the waiting time that this computer system sets because of user's operation is idle, this computer system is for regulating the energy profit and loss of hardware, and this first frequency that this CPU (central processing unit) is moved is adjusted, and its adjustment can be original frequency half, or is lower than the specification of original frequency.
3. the method that clocked memory according to claim 1 is adjusted, wherein when this second frequency adjustment of carrying out data access between this north bridge chips and this random access memory is finished, can make this computer system enter the start selftest stage of one among the Basic Input or Output System (BIOS), and the delay that utilizes data and/or data controlling signal is imported and/or the technology of output, this second frequency that adjustment is finished is detected and is calibrated, the result that adjustment is finished stores into a new setting recording among this Basic Input or Output System (BIOS) simultaneously, and carry out the adjustment of this second frequency of data access between this north bridge chips and this random access memory, can be adjusted to half of original frequency, or be lower than the specification of original frequency.
4. the method adjusted of a clocked memory is applied to north bridge chips in the computer system and electrical ties in a random access memory of this north bridge chips, and this method comprises the following step:
Carry out data access with a first frequency between this north bridge chips and this random access memory; And
Respond the variation of the workload of this north bridge chips, and this first frequency that carries out data access between this north bridge chips and this random access memory is adjusted.
5. the method that clocked memory according to claim 4 is adjusted, wherein the variation of the workload of this north bridge chips can be and utilizes a temperature sensor of being located at this inside computer system, when moving, carry out the sensing of temperature at this north bridge chips, and when showing bigger overheated of this north bridge chips generation workload, and this first frequency that carries out data access between this north bridge chips and this random access memory is adjusted because of its sensed temperature.
6. the method that clocked memory according to claim 4 is adjusted, wherein the change of the workload of this north bridge chips can be and utilizes a flow controller of being located at this north bridge chips inside, when moving, carry out data stream quantitative analysis on its bus at this north bridge chips, and when showing less idle of this north bridge chips generation workload, and this first frequency that carries out data access between this north bridge chips and this random access memory is adjusted because of the data traffic of its analysis.
7. the method that clocked memory according to claim 4 is adjusted, wherein when this first frequency adjustment of carrying out data access between this north bridge chips and this random access memory is finished, can make this computer system enter the start selftest stage of one among the Basic Input or Output System (BIOS), and the delay that utilizes data and/or data controlling signal is imported and/or the technology of output, this second frequency that adjustment is finished is detected and is calibrated, the result that adjustment is finished stores into a new setting recording among this Basic Input or Output System (BIOS) simultaneously, and carry out the adjustment of this first frequency of data access between this north bridge chips and this random access memory, can be adjusted to half of original frequency, or be lower than the specification of original frequency.
8. the method adjusted of a clocked memory is applied to north bridge chips in the computer system and electrical ties in a random access memory of this north bridge chips, and this method comprises the following step:
Carry out data access with a first frequency between this north bridge chips and this random access memory; And
Respond the change of user, and then this first frequency that carries out data access between this north bridge chips and this random access memory is adjusted a setting value in the software program performed in this computer system.
9. the method that clocked memory according to claim 8 is adjusted, wherein this setting value in this software program can be for being changed by the user voluntarily, and can therefore be decided by to utilize this computer system to be carried out this software program when which kind of condition takes place, and this first frequency that carries out data access between this north bridge chips and this random access memory is adjusted.
10. the method that clocked memory according to claim 8 is adjusted, wherein when this first frequency adjustment of carrying out data access between this north bridge chips and this random access memory is finished, can make this computer system enter the start selftest stage of one among the Basic Input or Output System (BIOS), and the delay that utilizes data and/or data controlling signal is imported and/or the technology of output, this second frequency that adjustment is finished is detected and is calibrated, the result that adjustment is finished stores into a new setting recording among this Basic Input or Output System (BIOS) simultaneously, and carry out the adjustment of this first frequency of data access between this north bridge chips and this random access memory, can be adjusted to half of original frequency, or be lower than the specification of original frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100729991A CN100354794C (en) | 2005-05-25 | 2005-05-25 | Method for regulating internal storage frequency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100729991A CN100354794C (en) | 2005-05-25 | 2005-05-25 | Method for regulating internal storage frequency |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1687867A true CN1687867A (en) | 2005-10-26 |
| CN100354794C CN100354794C (en) | 2007-12-12 |
Family
ID=35305909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100729991A Active CN100354794C (en) | 2005-05-25 | 2005-05-25 | Method for regulating internal storage frequency |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100354794C (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101788847A (en) * | 2010-02-11 | 2010-07-28 | 华硕电脑股份有限公司 | Method for adjusting performance of system memory and computer system |
| WO2012031540A1 (en) * | 2010-09-10 | 2012-03-15 | 联想(北京)有限公司 | Method for adjusting memory running frequency and electronic device |
| CN101561691B (en) * | 2008-04-15 | 2012-05-23 | 联阳半导体股份有限公司 | Method and device for regulating system frequency of storage device |
| CN102498480A (en) * | 2009-09-09 | 2012-06-13 | 意法爱立信有限公司 | Dynamic frequency memory control |
| CN102566655A (en) * | 2010-12-14 | 2012-07-11 | 联芯科技有限公司 | Dynamic bus frequency modulation method of off-chip memory and system thereof |
| CN101876837B (en) * | 2009-04-30 | 2013-04-03 | 华硕电脑股份有限公司 | Computer device, application program, system setting method, control method of memory |
| CN104484030A (en) * | 2014-12-22 | 2015-04-01 | 广东欧珀移动通信有限公司 | Method and device for lowering power consumption of intelligent terminal |
| CN106873664A (en) * | 2017-02-28 | 2017-06-20 | 努比亚技术有限公司 | A kind of temprature control method and mobile terminal |
| CN111274069A (en) * | 2018-12-05 | 2020-06-12 | 锐迪科（重庆）微电子科技有限公司 | Data processing method and device |
| CN111324196A (en) * | 2020-02-03 | 2020-06-23 | Oppo广东移动通信有限公司 | Memory operation frequency adjusting method and device, storage medium and electronic equipment |
| CN117215783A (en) * | 2023-09-11 | 2023-12-12 | 上海合芯数字科技有限公司 | Memory bank frequency adjustment method and device based on real-time temperature |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6763478B1 (en) * | 2000-10-24 | 2004-07-13 | Dell Products, L.P. | Variable clock cycle for processor, bus and components for power management in an information handling system |
| CN1256762C (en) * | 2002-11-12 | 2006-05-17 | 联想(北京)有限公司 | Chip frequency regulation method |
| CN1246751C (en) * | 2003-09-09 | 2006-03-22 | 威盛电子股份有限公司 | Computer system with power management and its method |
-
2005
- 2005-05-25 CN CNB2005100729991A patent/CN100354794C/en active Active
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101561691B (en) * | 2008-04-15 | 2012-05-23 | 联阳半导体股份有限公司 | Method and device for regulating system frequency of storage device |
| CN101876837B (en) * | 2009-04-30 | 2013-04-03 | 华硕电脑股份有限公司 | Computer device, application program, system setting method, control method of memory |
| CN102498480A (en) * | 2009-09-09 | 2012-06-13 | 意法爱立信有限公司 | Dynamic frequency memory control |
| CN102498480B (en) * | 2009-09-09 | 2014-09-17 | 意法爱立信有限公司 | Dynamic frequency memory control |
| CN101788847A (en) * | 2010-02-11 | 2010-07-28 | 华硕电脑股份有限公司 | Method for adjusting performance of system memory and computer system |
| CN101788847B (en) * | 2010-02-11 | 2012-07-04 | 华硕电脑股份有限公司 | Method for adjusting performance of system memory and computer system |
| WO2012031540A1 (en) * | 2010-09-10 | 2012-03-15 | 联想(北京)有限公司 | Method for adjusting memory running frequency and electronic device |
| US9740642B2 (en) | 2010-09-10 | 2017-08-22 | Lenovo (Beijing) Limited | Methods and electronic devices for adjusting the operating frequency of a memory |
| CN102566655B (en) * | 2010-12-14 | 2015-01-07 | 联芯科技有限公司 | Dynamic bus frequency modulation method of off-chip memory and system thereof |
| CN102566655A (en) * | 2010-12-14 | 2012-07-11 | 联芯科技有限公司 | Dynamic bus frequency modulation method of off-chip memory and system thereof |
| CN104484030A (en) * | 2014-12-22 | 2015-04-01 | 广东欧珀移动通信有限公司 | Method and device for lowering power consumption of intelligent terminal |
| CN106873664A (en) * | 2017-02-28 | 2017-06-20 | 努比亚技术有限公司 | A kind of temprature control method and mobile terminal |
| CN111274069A (en) * | 2018-12-05 | 2020-06-12 | 锐迪科（重庆）微电子科技有限公司 | Data processing method and device |
| CN111274069B (en) * | 2018-12-05 | 2023-07-07 | 锐迪科（重庆）微电子科技有限公司 | Data processing method and device |
| CN111324196A (en) * | 2020-02-03 | 2020-06-23 | Oppo广东移动通信有限公司 | Memory operation frequency adjusting method and device, storage medium and electronic equipment |
| CN111324196B (en) * | 2020-02-03 | 2021-09-28 | Oppo广东移动通信有限公司 | Memory operation frequency adjusting method and device, storage medium and electronic equipment |
| CN117215783A (en) * | 2023-09-11 | 2023-12-12 | 上海合芯数字科技有限公司 | Memory bank frequency adjustment method and device based on real-time temperature |
| CN117215783B (en) * | 2023-09-11 | 2024-07-09 | 上海合芯数字科技有限公司 | Memory bank frequency adjustment method and device based on real-time temperature |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100354794C (en) | 2007-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1687867A (en) | Method for regulating internal storage frequency | |
| Udipi et al. | Rethinking DRAM design and organization for energy-constrained multi-cores | |
| US7480792B2 (en) | Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing such devices | |
| Zheng et al. | Mini-rank: Adaptive DRAM architecture for improving memory power efficiency | |
| Luo et al. | CLR-DRAM: A low-cost DRAM architecture enabling dynamic capacity-latency trade-off | |
| US9891855B2 (en) | Memory device capable of adjusting operation voltage and application processor for controlling the memory device | |
| TWI412993B (en) | Increasing workload performance of one or more cores on multiple core processors | |
| US6766385B2 (en) | Device and method for maximizing performance on a memory interface with a variable number of channels | |
| US7506110B2 (en) | Memory controller having programmable initialization sequence | |
| US7590876B2 (en) | Method for adjusting a frequency working between a north bridge chip and a random access memory of a computer system | |
| US20050283630A1 (en) | Changing of operating voltage in semiconductor integrated circuit | |
| KR950009422A (en) | Single chip microcomputer | |
| US8996942B2 (en) | Suspend SDRAM refresh cycles during normal DDR operation | |
| US8438358B1 (en) | System-on-chip with memory speed control core | |
| CN1591368A (en) | Memory controller, smart card and a method of controlling a read operation of a memory | |
| US20150006931A1 (en) | Generic host-based controller latency method and appartus | |
| Lee et al. | Leveraging power-performance relationship of energy-efficient modern DRAM devices | |
| US11703935B2 (en) | Mechanism for saving power on a bus interface | |
| US8719606B2 (en) | Optimizing performance and power consumption during memory power down state | |
| EP3757720B1 (en) | Ddr5 client pmic power up sequence and state transitions | |
| Stevens et al. | An integrated simulation infrastructure for the entire memory hierarchy: Cache, dram, nonvolatile memory, and disk | |
| EP4071583A1 (en) | Avoiding processor stall when accessing coherent memory device in low power | |
| CN101404177B (en) | Computation type memory with data processing capability | |
| Chen et al. | MIMS: Towards a message interface based memory system | |
| WO2019140364A1 (en) | Safety enhancement for memory controllers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |