CN1684155A

CN1684155A - Write pulse generation for recording on optical media

Info

Publication number: CN1684155A
Application number: CNA200510064182XA
Authority: CN
Inventors: 彼得·马尔; 迈克尔·休恩克; 威布克·舍恩
Original assignee: Thomson Licensing SAS
Current assignee: Thomson Licensing SAS
Priority date: 2004-04-16
Filing date: 2005-04-13
Publication date: 2005-10-19
Anticipated expiration: 2025-04-13
Also published as: KR20060046653A; MY142450A; TW200539148A; JP2005310360A; CN100541612C; EP1587071A1

Abstract

The present invention relates to a method and a circuit for write pulse generation for recording on optical media, and to an apparatus for writing to optical recording media using such method. It is an object of the invention to propose a reliable and accurate method for write pulse generation with low hardware complexity. According to the invention, this object is achieved by a method for write pulse generation on the basis of a bit clock, including the steps of: dividing the bit clock by a factor n, multiplying the divided bit clock by a factor n+x or n-x with a phase-locked loop (2, 3) to obtain signal edges which are time-shifted relative to the bit clock, selecting a desired time-shifted signal edge, and multiplying the selected time-shifted signal edge by the factor n with a further phase-locked loop (5, 6) to obtain a time-shifted bit clock.

Description

The pulse that writes that is used for writing down on optical medium produces

Technical field

The present invention relates to a kind of Method and circuits that writes the pulse generation that is used on optical medium, writing down, and relate to a kind of next device that writes to optical record medium of such method that is used to use.

Background technology

The generation that writes pulse is the importance of the write-in policy that is used for writing down on optical medium.Must revise in during writing down and write pulse, because they need be divided into importing, middle and end pulse.And, depending on different aspect such as the manufacturer of optical medium, the length of these three pulses must be variable.According to prior art, realize writing the variation of the length of pulse by very high-frequency bit clock, the pulse of its uniqueness adds up in n pulse to obtain to write the length that is intended to of pulse.The shortcoming of this solution is: the precision at the interval of pulse length is subject to the frequency of major clock.In addition, writing speed be limited to bit clock maximum frequency n doubly.

Summary of the invention

Therefore, the object of the present invention is to provide a kind of reliable and method accurately, be used for producing with low hardware complexity and write pulse, it has overcome above-mentioned shortcoming.

According to the present invention, this purpose is to realize that by produce the method that writes pulse according to bit clock described method comprises step:

With bit clock divided by coefficient n,

Use the bit clock that phaselocked loop will be divided by to multiply by coefficient n+x or n-x, with the signal limit of acquisition with respect to the bit clock time shift,

Select the shifted signal limit of expectation, and

Use another phaselocked loop that coefficient n is multiply by on selected shifted signal limit, to obtain the bit clock of time shift.

Principle of the present invention is to use additional PLL to produce the bit clock of time delay.Under the situation of x=1, described delay equals n the part in bit clock cycle.In each cycle, described time delay is enhanced n.The desired delay device that is re-used is selected valuably.Therefore, produce defined time delay, be used to represent to have the desired length that writes pulse of precision n.The present invention can easily be applied to high-speed driver, because do not need the high frequency bit clock.In addition, realized depending on the precision that defines of time delay spacing.Principle of the present invention does not join with frequency dependence, but is fitted to the frequency that is produced automatically.

Preferably, by carrying out the bit clock that following step produces a plurality of different time shifts: select the shifted signal limit of expectation, and it is parallel several times to use another phaselocked loop that coefficient n is multiply by on selected shifted signal limit.This makes and can produce clear and definite optical output signal based on the signal of the shape of bit clock, one or more time shift bit clock and the pit of indicating to write down.

Similarly, a kind ofly be used for producing the circuit that writes pulse and comprise according to bit clock:

Divider is used for bit clock divided by coefficient n,

Phaselocked loop, the bit clock that is used for being divided by multiply by coefficient n+x or n-x, with the signal limit of acquisition with respect to the bit clock time shift,

Logical block, be used to select the shifted signal limit expected and

Another phaselocked loop is used for coefficient n is multiply by on selected shifted signal limit, to obtain the bit clock of time shift.

Such circuit constitutes the hardware implementation mode according to the low complex degree of method of the present invention.Preferably, a plurality of logical blocks and another phaselocked loop are provided to obtain the bit clock of a plurality of different time shifts, so that can produce clear and definite optical output signal by the pulse steering logic according to the signal of the shape of bit clock, one or more time shift bit clock and the pit of indicating to write down.

Useful is, a kind of being used for reads and/or carry out a kind of method to the device that optical record medium writes from optical record medium, or comprises and be used to write that pulse produces according to circuit of the present invention.Such device makes that can use low hardware complexity to produce writes pulse accurately.

Description of drawings

In order to understand the present invention better, in the following description with reference to description of drawings illustration embodiment.Should be appreciated that to the invention is not restricted to these illustrations embodiment that without departing from the scope of the invention, illustrated feature also can be combined and/or revise easily.In the accompanying drawings:

Fig. 1 illustrates the pulse that writes that is used for writing down on optical medium;

Fig. 2 shows the block scheme that writes pulse-generating circuit according to of the present invention;

Fig. 3 illustrates and uses phaselocked loop to produce the principle that writes pulse;

Fig. 4 has described the more detailed block scheme that writes pulse-generating circuit according to of the present invention;

Fig. 5 shows the hardware of decoder element and realizes.

Embodiment

Fig. 1 illustrates the pulse that writes that is used for writing down on optical medium.Shown is the signal mode that provides to the laser controlling unit from write control unit.Bit clock is used as the major clock of all unit.EFM represents that the overall situation writes the zone.In Fig. 1,8T pit and 3T pit have only been indicated.In optics output control laser power, peak value, wipe the power rank with the different laser of expression of setovering.

In Fig. 2, show the block scheme that writes pulse-generating circuit according to of the present invention.Use bit clock and EFM signal to control laser.Pre-divider 1 with bit clock divided by n.The value of n is determined the resolution of time delay.Postpone step-length PLL 2 and comprise divider 3, this divider has the division factor except n, and preferably n+1 or n-1 postpone the division factor that step-length PLL 2 multiply by the bit clock that is divided by described divider 3.Receive delay selects the logical block 4 of signal to allow to select one of n possible delay.The output frequency that the delay PLL 5 that comprises divider 6 will postpone step-length PLL 2 multiply by n obtaining the bit clock frequency once more, but with respect to the original bit clock and the selected delay of displacement.Another logical block 7 last laser power output modes that produce.For every additional lag line, need another group to postpone PLL, divider and logical block.

In Fig. 3, the illustration pattern of---it is used as major clock---of passing through bit clock, the output signal that postpones step-length PLL 2 and postpone PLL 5 come diagram to use the principle that pulse produces that writes of phaselocked loop.In described accompanying drawing, n is set to 20.Represent to postpone the output signal of PLL 5 for the delay of the delay of a step-length, two step-lengths and the delay of three step-lengths.

Fig. 4 has described the more detailed block scheme that writes pulse-generating circuit.Described block scheme is similar to the block scheme of Fig. 2.Only show major function.The input of divider 1 is a bit clock.At first, this clock quilt is divided by coefficient n.After divider 1, arranged the PLL unit, it comprises phase comparator 20, loop filter 21, voltage controlled oscillator (VCO) 22 and another divider 3.This PLL unit multiply by coefficient n+x with the bit clock frequency.X is defined as+and the 1 or the-the 1st, the easiest and the most useful situation.The plus or minus that algebraic symbol has defined with respect to bit clock postpones.Since x=1 (for n+1 or n-1) poor for example, the output mode of VCO 22 in the one-period of the output signal of divider 1 by the accurate bit clock length of displacement.The value of n determines to postpone the resolution of step-length.For example, under the situation of n=32, the resolution of delay cell be bit clock length 1/32.In other words, the cycle of bit clock is divided into n intermediate value.

First limit of one-period (the relatively pattern of the delay step-length PLL in Fig. 3) is synchronous with bit clock.Limit subsequently is with the step-length displacement of the 1/n of one-period.Demoder 8---has been described its implementation in more detail---and has been used to obtain single limit in Fig. 5, therefore obtain different delays.Use multiplexer 9 to select needed delay then.Illustrate the example that postpones #3 at Fig. 3 with in Fig. 5.The cycle of this signal equals the cycle of the output signal of divider 1, but by time shift.

Additional PLL---it is also as frequency multiplier---is made up of phase comparator 50, loop filter 51, VCO 52 and divider 6 with n step-length.Because multiplier is n, so output frequency equals bit clock, but all limits by displacement the m/n of length of bit clock, wherein m is an integer.In the example of Fig. 3, m is set to 3.The frequency that is not higher than bit clock.Multiplexer 9 and additional PLL form a delayed pulse generator.For each additional delay line, need additional delayed pulse generator.

Behind frequency multiplier, provide pulse steering logic 7.The input signal of this unit is the EFM signal, the shape (referring to Fig. 1) of its expression record pit, bit clock and from the delayed clock of VCO 52.These signals are by 7 combinations of pulse steering logic, to produce optical output signal as shown in Figure 1.

Claims

1. one kind is used for producing the method that writes pulse according to bit clock, comprises step:

With bit clock divided by coefficient n,

Use the bit clock that a phaselocked loop (2,3) will be divided by to multiply by coefficient n+x or n-x, with the signal limit of acquisition with respect to the bit clock time shift,

Select the shifted signal limit of expectation, and

Use another phaselocked loop (5,6) that coefficient n is multiply by on selected shifted signal limit, to obtain the bit clock of time shift.

2. according to the process of claim 1 wherein, by carrying out the bit clock that following step produces a plurality of different time shifts: select the shifted signal limit of expectation, and use that another phaselocked loop (5,6) is parallel to multiply by coefficient n with selected shifted signal limit several times.

3. according to the method for claim 1 or 2, wherein, use multiplexer (4) to select the shifted signal limit of expecting.

4. according to the method for one of claim 1-3, also comprise step: the signal according to the shape of the bit clock of described bit clock, one or more time shifts and the pit of indicating to write down produces optical output signal.

5. according to the method for one of claim 1-4, x=1 wherein.

6. one kind is used for producing the circuit that writes pulse according to bit clock, comprising:

Divider (1) is used for bit clock divided by coefficient n,

Phaselocked loop (2,3), the bit clock that is used for being divided by multiply by coefficient n+x or n-x, with the signal limit of acquisition with respect to the bit clock time shift,

Logical block (4) is used to select the shifted signal limit expected, and

Another phaselocked loop (5,6) is used for coefficient n is multiply by on selected shifted signal limit, to obtain the bit clock of time shift.

7. according to the circuit of claim 6, wherein, a plurality of logical blocks (4) and another phaselocked loop (5,6) are provided to obtain the bit clock of a plurality of different time shifts.

8. according to the circuit of claim 7, also comprise pulse steering logic (7), be used for producing optical output signal according to the signal of the shape of the bit clock of described bit clock, one or more time shifts and the pit of indicating to write down.

9. one kind is used for the device that reads and/or write to optical record medium (1) from optical record medium (1), it is characterized in that it comprises and is used to carry out according to the device of the method for one of claim 1-5 or comprises and be used to produce the circuit according to one of claim 6-8 that writes pulse.