CN1677968A - Mean power frequency discriminator, frequency phase locked loop circuit and digital television demodulator using the same - Google Patents

Mean power frequency discriminator, frequency phase locked loop circuit and digital television demodulator using the same Download PDF

Info

Publication number
CN1677968A
CN1677968A CNA2005100626139A CN200510062613A CN1677968A CN 1677968 A CN1677968 A CN 1677968A CN A2005100626139 A CNA2005100626139 A CN A2005100626139A CN 200510062613 A CN200510062613 A CN 200510062613A CN 1677968 A CN1677968 A CN 1677968A
Authority
CN
China
Prior art keywords
signal
frequency
output
phase
sampled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2005100626139A
Other languages
Chinese (zh)
Inventor
张骏凌
康起铜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN1677968A publication Critical patent/CN1677968A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
    • H04N21/4382—Demodulation or channel decoding, e.g. QPSK demodulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/455—Demodulation-circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0044—Control loops for carrier regulation
    • H04L2027/0053—Closed loops
    • H04L2027/0057—Closed loops quadrature phase

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

Exemplary embodiments of the present invention provide a frequency phase locked loop circuit, which may enable a frequency and phase of a carrier signal to be tracked within a shorter time. Exemplary embodiments of the present invention also provide a digital television demodulator using the frequency phase locked loop circuit. According to an exemplary embodiment of the present invention, the frequency phase locked loop circuit may include a mean power frequency discriminator, a mean calculator, a phase discriminator, a loop-filter, and an adder. The frequency phase locked loop circuit may receive a carrier frequency through a path, and can track the phase of the carrier frequency through another path.

Description

Average power frequency discriminator, Frequency Phase Lock loop circuit and digital television demodulator
Technical field
Exemplary embodiment of the present invention relates to Digital Television.More particularly, exemplary embodiment of the present invention relates to a kind of average power frequency discriminator, and it is exportable to comprise error signal about the information of the offset carrier frequency of carrier signal and/or phase place.Offset carrier frequency can be applied to for example Digital Television (DTV) demodulator (for example, advanced television standard committee Digital Television (ATSC-DTV) demodulator).
Background technology
DTV (for example, the ATSC DTV) demodulator that can be used for the correlation technique in DTV (for example, the ATSC DTV) receiver can be to carrying out demodulation from the analog signal that DTV (for example, ATSC DTV) transmitter sends.DTV (for example, ATSC DTV) receiver can obtain the carrier frequency of analog signal.DTV (for example, ATSC DTV) receiver can utilize the Frequency Phase Lock loop circuit, and can obtain carrier frequency.
For analog signal is carried out demodulation, carrier frequency can be followed the tracks of and obtain to DTV (for example, ATSC DTV) demodulator, and can follow the tracks of the phase place of carrier frequency.
Fig. 1 is the block diagram of DTV (for example, the ATSC DTV) demodulator of correlation technique.With reference to Fig. 1, DTV (for example, ATSC DTV) demodulator 100 can comprise analog to digital (ADC) 110, multiphase filter (PPF) 120, multiplier 130, filter 140, upconverter 150, symbol timing recovery device (STR) 160, frequency and phase locking loop circuit (FPLL) 170, Numerical Control oscillator (NCO) 180 and phase shifter 190.
ADC110 can will be able to convert digital signal to from the analog signal R (t) that DTV (for example, ATSC DTV) transmitter (not shown) sends.
PPF120 can be from the ADC110 receiving digital signals, and can generate signal R[t n].Signal R[t n] can sample frequency f S(=1/T S) sample T wherein SCan represent the sampling time, t n=n * T S, and n can be an integer.The operation of PPF120 can be by controlling from the control signal C1 of STR160 output.
Multiplier 130 also can comprise two multipliers 131 and 132.
Multiplier 131 can be with sampled signal R[t n] multiply by frequency sinusoidal signal fs1, and exportable branch signal, this branch signal can be and sampled signal R[t n] signal of homophase.Multiplier 132 can be with sampled signal R[t n] multiply by another frequency sinusoidal signal fs2, and exportable and sampled signal R[t n] another branch signal Q ' [t of quadrature n].
Filter 140 can comprise two matched filters (MF) 141 and 142.MF141 can be by being included in the first branch signal I ' [t n] in low frequency signal, and exportable another branch signal I[t n].MF142 can be by being included in branch signal Q ' [t n] in low frequency signal, and exportable another branch signal Q[t n].
Upconverter 150 can use branch signal I[t n] and Q[t n] can be from sampled signal R[t n] the real component signal Re[t that extracts n] send to STR160 and FPLL170.Upconverter 150 can use branch signal I[t n] and Q[t n] can be from sampled signal R[t n] the imaginary number component signal Im[t that extracts n] send to FPLL170.
Sample frequency f among the exportable may command PPF120 of STR160 S(=1/T S) and the control signal C1 of timing phase, it can use real component signal Re[t n].
FPLL170 can use real number and imaginary number component signal Re[t n] and Im[t n], and exportable error signal e [t n].Error signal e [t n] can comprise relevant sampled signal R[t n] frequency and the information of phase deviation.
The exportable frequency sinusoidal signal of NCO180 fs1, cos ((ω C+ Δ ω) t n+ Φ)).Frequency sinusoidal signal fs1 can be by can be from the error signal e [t of FPLL170 output n] determine.
Phase shifter 190 can be with 90 ° of the phase shifts of frequency sinusoidal signal fs1, and exportable frequency sinusoidal signal fs2, sin ((ω C+ Δ ω) t n+ Φ)).Δ ω and Φ can represent sampled signal R[t between DTV (for example, ATSC DTV) transmitter and DTV (for example, the ATSC DTV) demodulator 100 respectively n] frequency shift (FS) and phase deviation.
Can comprise the analog signal R (t) of pilot tone (pilot tone) from the transmission of DTV (for example, ATSC DTV) transmitter, and can use FPLL170 to follow the tracks of the frequency and the phase place of carrier signal more reliably.
Analog signal R (t) can not comprise pilot tone, and perhaps pilot tone (for example, in process of transmitting) is faint, and can use FPLL170 can become more unreliable to the frequency of carrier signal and the tracking of phase place.
When DTV (for example, ATSC DTV) receiver for example receives analog signal R (t) by multipath channel, the pilot tone of analog signal R (t) may decay (for example, decay basically).The decay of the pilot tone of analog signal R (t) can cause and can become more unreliable to the frequency of carrier signal and/or the tracking of phase place by using FPLL170.
Summary of the invention
Exemplary embodiment of the present invention (for example provides a kind of average power frequency discriminator, a kind of Frequency Phase Lock loop circuit and a kind of digital television demodulator, ATSC DTV demodulator), it can make it possible to follow the tracks of in the short period of time the frequency and the phase place of carrier signal.
According to exemplary embodiment of the present invention, a kind of Frequency Phase Lock loop circuit can comprise average power frequency discriminator, mean value computation device, phase discriminator, loop filter and adder.The Frequency Phase Lock loop circuit can receive the real number and the imaginary number component signal of first signal branch signal of sampled signal homophase (for example, with), the secondary signal branch signal of sampled signal quadrature (for example, with) and sampled signal.The Frequency Phase Lock loop circuit can use the signal that is received to determine the carrier frequency and/or the phase place of sampled signal.The average power frequency discriminator can be to first and/or the secondary signal executable operations, can first error signal corresponding with the frequency shift (FS) of sampled signal with output.The mean value computation device can calculate the average of first error signal, can comprise second error signal of information of the frequency shift (FS) of relevant carrier signal with output.Phase discriminator can utilize real number and imaginary number component signal, can comprise the signal of information of the phase deviation of relevant carrier signal with output.Loop filter can be from eliminating high-frequency noise from the signal of phase discriminator output.First adder can be added to second error signal from the signal of loop filter output, and exportable the 3rd error signal, and it can comprise the carrier frequency of relevant sampled signal and/or the information of phase deviation.The Frequency Phase Lock loop circuit can pass through average power frequency discriminator, mean value computation device and first adder and obtain carrier frequency, and can pass through the phase place that phase discriminator, loop filter and first adder are followed the tracks of carrier frequency.
According to another exemplary embodiment of the present invention, a kind of digital television demodulator (for example, advanced television standard committee Digital Television (ATSC-DTV) demodulator) can comprise AD converter, multiphase filter, multiplier, low pass filter, upconverter, symbol timing recovery device, Frequency Phase Lock loop circuit, Numerical Control oscillator and phase shifter.AD converter can become digital signal with the analog signal conversion that sends from digital television transmitter (for example, advanced television standard committee Digital Television (ATSC-DTV) transmitter).Multiphase filter can receive from the digital signal of AD converter with from the control signal of symbol timing recovery device, and can generate with sample frequency f SThe sampled signal of sampling, wherein sample frequency f SCan change according to control signal.Multiplier can receive the sampled signal and the first and second frequency sinusoidal signals, and exportable first signal branch signal of sampled signal homophase (for example, with) and the secondary signal branch signal of sampled signal quadrature (for example, with).Respectively, low pass filter can pass through the low frequency signal of first and second signals, and exportable third and fourth signal (for example, branch signal).Upconverter can use the 3rd and/or the 4th branch signal to export can be from the real number and the imaginary number component signal of sampled signal extraction.The symbol timing recovery device can use real component signal output control signal.The Frequency Phase Lock loop circuit can use first and second signals and real number and imaginary number component signal to export the 3rd signal, and it can comprise the information of the frequency shift (FS) and/or the phase deviation of relevant sampled signal.The exportable first frequency sinusoidal signal of Numerical Control oscillator, its frequency of oscillation can be by determining from the 3rd signal of Frequency Phase Lock loop circuit output.Phase shifter can be with phase shifts one angle of first frequency sinusoidal signal, and exportable second frequency sinusoidal signal.
According to another exemplary embodiment of the present invention, a kind of Frequency Phase Lock loop circuit can receive at least with first signal of sampled signal homophase (for example, branch signal), with the secondary signal (for example, branch signal) of sampled signal out-phase and the real number and the imaginary number component signal of sampled signal.The exportable error signal of Frequency Phase Lock loop circuit, it can comprise the carrier frequency of relevant sampled signal and/or the information of phase deviation.
In another exemplary embodiment of the present invention, provide a kind of method that is used to obtain carrier frequency and follows the tracks of the phase place of carrier frequency.This method can comprise the first and second signal executable operations, with output first error signal corresponding with the frequency shift (FS) of sampled signal.Can calculate the average of first error signal, and export second error signal, it can comprise the information of the frequency shift (FS) of relevant carrier signal.Can export first output signal based on real number and imaginary number component signal, and this output signal can comprise the information of the phase deviation of relevant carrier signal.Can produce second output signal by the noise that reduces in first output signal, and can produce the 3rd output signal based on second error signal and second output signal.The 3rd output signal can comprise the carrier frequency of relevant sampled signal and the information of phase deviation.Based on the information in the 3rd output signal, can obtain carrier frequency, and can follow the tracks of the phase place of carrier frequency.
In another exemplary embodiment of the present invention, provide a kind of method of error signal of the information that is used to produce the frequency carrier skew that comprises relevant carrier signal.This method according to Nyquist criterion at least the first signal and secondary signal (for example can comprise, branch signal) carries out filtering, (for example to export the 3rd signal and the 4th signal, branch signal), the 3rd signal and the 4th signal are carried out square operation, and addition the 3rd signal and the 4th signal are with output error signal, and it can comprise the information of the frequency carrier skew of relevant carrier signal.
Description of drawings
With reference to accompanying drawing, exemplary embodiment of the present invention will become apparent, wherein:
Fig. 1 is the block diagram of the ATSC DTV demodulator of correlation technique;
Fig. 2 is the block diagram of ATSC DTV demodulator according to an exemplary embodiment of the present invention;
Fig. 3 is the block diagram of the average power frequency discriminator (MP-FD) 271 of Fig. 2 according to an exemplary embodiment of the present invention;
Fig. 4 is the example of the frequency spectrum of the 3rd branch signal of expression in equation 4; And
Fig. 5 is the error signal e [t that can export from the MP-FD271 of Fig. 3 n] with respect to the example of the function of frequency shift (FS) Δ ω.
Embodiment
Now with reference to accompanying drawing exemplary embodiment of the present invention is described.Yet the present invention can take multiple different form to implement, and should not be construed as limited to the embodiment that sets forth here; On the contrary, these exemplary embodiments are in order to make present disclosure thoroughly and complete and provide, and they will pass on notion of the present invention to those skilled in the art comprehensively.Between each accompanying drawing, identical label is represented identical unit.
Fig. 2 is the block diagram of DTV (for example, ATSC DTV) demodulator according to an exemplary embodiment of the present invention.DTV (for example, ATSC DTV) demodulator 200 can comprise ADC210, PPF220, multiplier 230, low pass filter (LPF) 240, upconverter 250, STR260, frequency and phase tracking circuit 270, NCO180 and phase shifter 290.
ADC210 can will be able to convert digital signal to from the analog signal R (t) that DTV (for example, ATSC DTV) transmitter (not shown) sends.
PPF220 can be from the ADC210 receiving digital signals, and can generate signal R[t n].Signal R[t n] can be according to sample frequency f for example S(=1/T S) be sampled T wherein SCan represent the sampling time, t n=n * T S, and n can be an integer.The operation of PPF220 can be by controlling from least one control signal C1 of STR260 output.
Multiplier 230 also can comprise multiplier 231 and 232 at least.Multiplier 231 can be with sampled signal R[t n] multiply by frequency sinusoidal signal fs1, and exportable and sampled signal R[t n] signal (for example, the branch's in-phase signal) I ' [t of homophase n].Multiplier 232 can be with sampled signal R[t n] multiply by frequency sinusoidal signal fs2, and exportable and sampled signal R[t n] signal (for example, the branch's orthogonal signalling) Q ' [t of quadrature n].
LPF240 also can comprise matched filter MF241 and 242.
MF241 can pass through signal I ' [t n] low frequency signal, and exportable signal (for example, branch signal) I " [t n].MF242 can pass through signal Q ' [t n] low frequency signal, and exportable signal (for example, branch signal) Q " [t n].
Upconverter 250 can use signal I " [t n] and/or Q " [t n] can be from sampled signal R[t n] the real component signal Re[t that extracts n] send to STR260 and PFLL270.Upconverter 250 can use signal I " [t n] and Q " [t n] can be from sampled signal R[t n] the imaginary number component signal Im[t that extracts n] send to PFLL270.
STR260 can utilize real component signal Re[t n], and the exportable C1 of control signal at least, the sample frequency among this control signal may command PPF 220 is f for example S(=1/T S) and/or timing phase.
Frequency and phase tracking circuit 270 can comprise MP-FD271, mean value computation device 272, Costas phase discriminator (PD) 273, loop filter 274 and adder 275 at least.
MP-FD271 can be to can be from the signal I ' [t of multiplier 230 output n] and Q ' [t n] executable operations, and exportable error signal e [t n], it can be corresponding to sampled signal R[t n] frequency shift (FS) Δ ω.
Mean value computation device 272 can calculate the error signal e [t that receives from MP-FD271 n] average, and exportable another error signal e ' [t n].Error signal e ' [t n] can comprise relevant sampled signal R[t n] the information of frequency shift (FS) Δ ω, and the frequency of oscillation of may command (for example, control adaptively) frequency sinusoidal signal fs1.Frequency sinusoidal signal fs1 can export from NCO280, and can obtain the frequency of carrier signal.
Costas PD273 can use real number and/or imaginary number component signal Re[t n] and/or Im[t n], and the signal of the information of the exportable phase deviation that comprises relevant carrier signal.Loop filter 274 can be from eliminating noise (for example, high-frequency noise) from the signal of Costas PD273 output.
Adder 275 can be with error signal e ' [t n] be added to from the signal of loop filter 274 outputs, and exportable another error signal E[t n], it can comprise relevant sampled signal R[t n] carrier frequency and/or the information of phase deviation.
Carrier frequency can obtain by the path that for example comprises MP-FD271, mean value computation device 272 and adder 275.The phase place of carrier frequency can be followed the tracks of by another path that for example comprises Costas PD273, loop filter 274 and adder 275.
Exportable its frequency of oscillation of NCO280 can be by error signal E[t n] definite frequency sinusoidal signal fs1, cos ((ω C+ Δ ω) t n+ Φ)).
Phase shifter 290 can be with frequency sinusoidal signal fs1 cos ((ω C+ Δ ω) t n+ Φ)) 90 ° of phase shifts, and exportable frequency sinusoidal signal fs2 sin ((ω C+ Δ ω) t n+ Φ)).
Δ ω and Φ can represent DTV (for example, ATSC DTV) transmitter and the frequency shift (FS) and the phase deviation that can be used between DTV (for example, the ATSC DTV) demodulator 200 in DTV (for example, ATSC DTV) the receiver (not shown).
Can be from the sampled signal R[t of PPF220 output n] can be shown in equation 1:
R[t n]=x VSB, Re[t n] cos (ω CT n)-x VSB, Im[t n] sin (ω CT n)+n[t n] ... (1) wherein, x VSB, Re[t n] and x VSB, Im[t n] can represent vestigial sideband (vsb) signal, it can be sampled signal R[t n] real part and imaginary part.x VSB, Re[t n] and x VSB, Im[t n] can send to DTV (for example, ATSC DTV) receiver from DTV (for example, ATSC DTV) transmitter, and can be according to for example f S(1=1/T S) sample frequency be sampled.ω CCan represent can be from the carrier frequency of DTV (for example, ATSC DTV) transmitter transmission, n[t n] can represent can be according to for example f SThe noise (for example, additive white Gaussian noise (AWGN)) that is sampled of sample frequency, t wherein n=n * T S, and n can be an integer.
Vestigial sideband (vsb) signal x VSB, Re[t n] and x VSB, Im[t n] can comprise can be according to the pilot tone of DTV standard (for example, ATSC DTV standard) definition.Noise in the equation 1 (for example, AWGN) n[t n] can not influence can be from the error signal e ' [t of frequency and phase tracking circuit 270 outputs n] average characteristics.
As shown in Figure 2, sampled signal R[t n] can multiply by frequency sinusoidal signal fs1cos ((ω by multiplier 231 C+ Δ ω) t n+ Φ)), and can generate signal (for example, branch signal) I ' [t n].
Sampled signal R[t n] can be multiply by by multiplier 232 can be from frequency sinusoidal signal fs2 the sin ((ω of phase shifter 290 outputs C+ Δ ω) t n+ Φ)), and can generate signal (for example, branch signal) Q ' [t n].
Signal (for example, branch signal) I ' [t n] and Q ' [t n] can represent by for example equation 2 and 3 respectively:
I ′ [ t n ] = 1 2 x VSB , Re [ t n ] · [ cos ( Δω · t n + Φ ) + cos ( ( 2 ω C + Δω ) · t n + Φ ) ]
+ 1 2 x VSB , Im [ t n ] · [ sin ( Δω · t n + Φ ) - sin ( ( 2 ω C + Δω ) · t n + Φ ) ] . . . ( 2 )
Q ′ [ t n ] = 1 2 x VSB , Im [ t n ] · [ cos ( Δω · t n + Φ ) + cos ( ( 2 ω C + Δω ) · t n + Φ ) ]
- 1 2 x VSB , Re [ t n ] · [ sin ( Δω · t n + Φ ) + sin ( ( 2 ω C + Δω ) · t n + Φ ) ] . . . ( 3 )
Fig. 3 is the block diagram of MP-FD271 according to an exemplary embodiment of the present invention.MP-FD271 can comprise Nyquist low pass filter (LPF) 301 and 303, chi square function 302 and 304 and adder 305 at least.
Nyquist LPF301 can satisfy Nyquist criterion, and can be to signal (for example, branch signal) I ' [t n] carry out filtering, this exportable signal (for example, branch signal) I " [t n].
Nyquist LPF303 can satisfy Nyquist criterion, and can be to signal (for example, branch signal) Q ' [t n] carry out filtering, this exportable signal (for example, branch signal) Q " [t n].
Signal I " [t n] can represent by for example equation 4:
I ′ ′ [ t n ] = 1 2 x VSB , Re [ t n ] cos ( Δω t n + Φ ) * h [ t n ] + 1 2 x VSB , Im [ t n ] sin ( Δ ωt n + Φ ) * h [ t n ]
...(4)
Wherein, h[] can represent the impulse response of Nyquist LPF301 and 303, and * can represent convolution.
Vestigial sideband (vsb) signal x VSB, Re[t n] and x VSB, Im[t n] can represent by for example equation 5 and 6 respectively:
x VSB，Re[t n]＝[s[t n]cos(ω 1·t n)]*MF Tx ...(5)
x VSB，Im[t n]＝[s[t n]sin(ω 1·t n)]*MF Tx ...(6)
Wherein, s[t n] can represent the data that send, ω 1The operating frequency that can represent the down-converter of DTV (for example, ATSC DTV) transmitter, and MF TxCan represent can be from data and/or homophase (I) component of the transmission signal in the equation 5 and quadrature (Q) component of the transmission signal in the equation 6 of the MF of DTV (for example, ATSC DTV) transmitter output.
Frequency and phase tracking circuit 270 and/or DTV (for example, ATSC DTV) demodulator 200 can reduce the time that is used for tracking frequency and/or phase deviation.
Fig. 4 is by for example signal the I " [t of equation 4 expressions n] the example of frequency spectrum.With reference to Fig. 4, dotted line can be represented H (f), and it can represent impulse response h[] Fourier transform.Respectively, can be to sin (ω 0T) and/or cos (ω 0T) carry out Fourier transform, and can obtain equation 7 and/or 8:
j 2 { δ ( f + f 0 ) - δ ( f - f 0 ) } . . . ( 7 )
1 2 { δ ( f + f 0 ) + δ ( f + f 0 ) } . . . ( 8 )
Wherein, j = - 1 .
Respectively, can be to vestigial sideband (vsb) signal function x VSB, Re[t n] cos (Δ ω t n+ Φ) and/or x VSB, Im[t n] sin (Δ ω t n+ Φ) carry out Fourier transform H (f), and can obtain equation 9 and/or 10:
1 2 { x VSB , Re ( f + Δf ) - x VSB , Re ( f - Δf ) } . . . ( 9 )
1 2 { x VSB , Im ( f + Δf ) + x VSB , Im ( f - Δf ) } . . . ( 10 )
In the exemplary plot at Fig. 4 top, solid line and heavy line can be represented sampled signal R[t respectively n] a left side and right spectrum component.In the exemplary plot of Fig. 4 bottom, solid line and heavy line can be represented respectively can be from residual sideband the I " [t of Nyquist LPF301 output n]={ R[t n] cos (2 π (fc+ Δ f) t n+ Φ) } * h[t n] a left side and right spectrum component.Dotted line can be represented h[t n] frequency spectrum.
In the exemplary plot of Fig. 4 bottom, the width of carrier frequency shift Δ ω can less than or basically less than the slope of H (f) width of a part for example, and signal I[t n] power measurement can change along with carrier frequency shift Δ ω.
Fig. 5 is that illustrate can be from the error signal e [t of MP-FD271 output n] the example of curve of function.For the purpose of example, show curve with respect to frequency shift (FS) Δ ω.With reference to Fig. 5, example plot can be asymmetric about the y direction of principal axis.
With reference to Fig. 4, carrier frequency shift Δ ω can increase, error signal e [t n] can be away from the profile (profile) of Fourier transform H (f), and error signal e [t n] can reduce.
Just, carrier frequency shift Δ ω can reduce, error signal e [t n] frequency spectrum can more close Fourier transform H (f) profile, and error signal e [t n] can increase.
About Fig. 3, can be corresponding to the error signal e [t of carrier frequency shift Δ ω n] can pass through sum signal I ' [t n] and Q ' [t n] power measurement obtain.Can to the Nyquist LPF303 that can form path shown in Figure 3 and/or chi square function 304 application class like or substantially similar process.
According to an exemplary embodiment of the present invention Frequency Phase Lock loop circuit and/or DTV (for example, ATSCDTV) demodulator can be when pilot tone can decay or decay basically time quantum tracking frequency and/or the phase place to reduce.Pilot tone can decay owing to the factor of for example multipath channel or decay basically.
Though exemplary embodiment of the present invention is to describe about the factor such as multipath channel, should be appreciated that a lot of different factors can cause the decay or the basic decay of pilot tone.
Though exemplary embodiment of the present invention is described about Fourier transform, should be appreciated that those of ordinary skill in the art can realize the conversion that any other is fit to as required.
Though exemplary embodiment of the present invention is described about frequency domain, should be appreciated that those of ordinary skill in the art can realize the territory (for example, time domain) that any other is fit to as required.
Though exemplary embodiment of the present invention about the DTV standard (for example is, ATSC DTV standard) describes, but for example pilot tone can be according to the desired any suitable standard of those of ordinary skill in the art to should be appreciated that the each side of exemplary embodiment of the present.
Though exemplary embodiment of the present invention waits about two nyquist filters for example, two chi square functions and illustrates and describe, but be to be understood that, those of ordinary skill in the art can use the assembly (that is, nyquist filter, chi square function etc.) of any number as required.
Though exemplary embodiment of the present invention is described about the Costas phase discriminator, should be appreciated that those of ordinary skill in the art can utilize any suitable phase discriminator as required.
Although the present invention specifically illustrates and describes with reference to its exemplary embodiment, but will be understood by those skilled in the art that, under the situation that does not break away from the spirit and scope of the present invention that are defined by the following claims, can carry out the various modifications of form and details to it.
The application requires the priority of the korean patent application submitted in Korea S Department of Intellectual Property on April 3rd, 2004 2004-23176 number, at this with its hereby incorporated by reference.

Claims (18)

1. Frequency Phase Lock loop circuit comprises:
The average power frequency discriminator is suitable for the first and second signal executable operations, with output first error signal corresponding with the frequency shift (FS) of sampled signal;
The mean value computation device is suitable for calculating the average of first error signal, and exports second error signal of the information of the frequency shift (FS) that comprises relevant carrier signal;
Output comprises the signal of information of the phase deviation of relevant carrier signal with the imaginary number component signal for phase discriminator, the real number that is suitable for using sampled signal;
Loop filter is suitable for eliminating noise from the signal of phase discriminator output; And
First adder, be suitable for second error signal is added to from the signal of loop filter output, the 3rd error signal that comprises the information of the carrier frequency of relevant sampled signal and phase deviation with output, wherein, the Frequency Phase Lock loop circuit is adapted to pass through average power frequency discriminator, mean value computation device and first adder and obtains carrier frequency, and follows the tracks of the phase place of carrier frequency by phase discriminator, loop filter and first adder.
2. Frequency Phase Lock loop circuit as claimed in claim 1, wherein, the average power frequency discriminator also comprises:
At least two Nyquist low pass filters are suitable for according to Nyquist criterion at least the first and second branch signals being carried out filtering, to export third and fourth branch signal;
At least two chi square functions are suitable for third and fourth branch signal is carried out square operation; And
Adder is suitable for to carrying out addition from the data of these two chi square function outputs, with output error signal at least.
3. digital television demodulator comprises:
AD converter, the analog signal conversion that is suitable for sending from digital television transmitter becomes digital signal;
Multiphase filter is suitable for receiving from the digital signal of AD converter with from the control signal of symbol timing recovery device, to generate the sampled signal that is sampled according to the sample frequency that changes according to control signal;
Multiplier is suitable for receiving the sampled signal and the first and second frequency sinusoidal signals, with output and first signal of sampled signal homophase and with the secondary signal of sampled signal out-phase;
Low pass filter is suitable for first and second signals are carried out filtering, to export third and fourth signal;
Upconverter is suitable for the real number and the imaginary number component signal that use the output of the 3rd and/or the 4th signal to extract from sampled signal;
The symbol timing recovery device is suitable for using real component signal output control signal;
The Frequency Phase Lock loop circuit is suitable for using first and second signals and real number and imaginary number component signal to export the 5th signal, and it comprises the information of the frequency shift (FS) and the phase deviation of relevant sampled signal;
The Numerical Control oscillator is suitable for exporting the first frequency sinusoidal signal of determining by from the 5th signal of Frequency Phase Lock loop circuit output; And
Phase shifter is suitable for phase shifts one angle with the first frequency sinusoidal signal, with output second frequency sinusoidal signal.
4. digital television demodulator as claimed in claim 3, wherein:
Sampled signal is expressed as R[t n], t wherein n=n * T S, T wherein S(=1/f S) and the expression sampling time, and n is an integer;
The first frequency sinusoidal signal is expressed as cos ((ω C+ Δ ω) t n+ Φ)), wherein Δ ω and Φ represent digital television transmitter and are used for frequency shift (FS) and phase deviation between the digital television demodulator that DTV receiver uses;
Angle is 90 °; And
The second frequency sinusoidal signal is expressed as sin ((ω C+ Δ ω) t n+ Φ)).
5. digital television demodulator as claimed in claim 3, wherein, multiplier comprises:
At least two multipliers are suitable for sampled signal be multiply by the first frequency sinusoidal signal, with the output and first signal of sampled signal homophase, and sampled signal be multiply by the second frequency sinusoidal signal, with the quadrature secondary signal of 90 ° of output and sampled signal out-phase.
6. digital television demodulator as claimed in claim 3, wherein, low pass filter comprises:
At least two filters are suitable for first signal is carried out filtering exporting the 3rd signal, and secondary signal are carried out filtering to export the 4th signal.
7. digital television demodulator as claimed in claim 3, wherein, the Frequency Phase Lock loop circuit comprises:
The average power frequency discriminator is suitable for the first and second branch signal executable operations, with output first error signal corresponding with the frequency shift (FS) of sampled signal;
The mean value computation device is suitable for calculating the average of first error signal, comprises second error signal of information of the frequency shift (FS) of relevant sampled signal with output;
Phase discriminator is suitable for using real number and imaginary number component signal to export the signal of the information of the phase deviation that comprises relevant carrier signal;
Loop filter is suitable for eliminating noise from the signal of phase discriminator output; And
First adder is suitable for and will be added to from second error signal of mean value computation device output from the signal of loop filter output, comprises the 3rd error signal of the information of the carrier frequency of relevant sampled signal and phase deviation with output,
Wherein, the Frequency Phase Lock loop circuit obtains carrier frequency by first path that comprises average power frequency discriminator, mean value computation device and first adder, and the phase place of the second path trace carrier frequency by comprising phase discriminator, loop filter and first adder.
8. digital television demodulator as claimed in claim 7, wherein, the average power frequency discriminator comprises:
At least two Nyquist low pass filters are suitable for according to Nyquist criterion first and second signals being carried out filtering, to export the 3rd signal and the 4th signal;
At least two chi square functions are suitable for the 3rd signal and the 4th signal are carried out square operation; And
Second adder is suitable for to carrying out addition from the data of these two chi square function outputs, to export first error signal at least.
9. Frequency Phase Lock loop circuit, be suitable for receiving at least with first branch signal of sampled signal homophase, with second branch signal of sampled signal out-phase and the real number and the imaginary number component signal of sampled signal, and output comprises the error signal of the information of the carrier frequency of relevant sampled signal and phase deviation.
10. Frequency Phase Lock loop circuit as claimed in claim 9 also comprises:
The average power frequency discriminator is suitable for the first and second signal executable operations, with output first error signal corresponding with the frequency shift (FS) of sampled signal;
The mean value computation device is suitable for calculating the average of first error signal, and exports second error signal of the information of the frequency shift (FS) that comprises relevant carrier signal;
Phase discriminator, the signal of the information of the phase deviation that is suitable for using real number and imaginary number component signal to comprise relevant carrier signal with output;
Loop filter is suitable for eliminating noise from the signal of phase discriminator output; And
First adder is suitable for second error signal is added to signal from loop filter output, comprises the error signal of the information of the carrier frequency of relevant sampled signal and phase deviation with output.
11. an average power frequency discriminator comprises:
At least two Nyquist low pass filters are suitable for according to Nyquist criterion at least the first and second branch signals being carried out filtering, to export third and fourth branch signal;
At least two chi square functions are suitable for third and fourth branch signal is carried out square operation; And
Adder is suitable for carrying out addition from the data of these two chi square function outputs, with output error signal at least.
12. a method that is used to obtain carrier frequency and follows the tracks of the phase place of carrier frequency comprises:
To the first and second signal executable operations, with output first error signal corresponding with the frequency shift (FS) of sampled signal;
Calculate the average of first error signal, and export second error signal of the information of the frequency shift (FS) that comprises relevant carrier signal;
Export first output signal of the information of the phase deviation that comprises relevant carrier signal based on real number and imaginary number component signal;
Produce second output signal by from first output signal, eliminating noise;
Produce the 3rd output signal based on second error signal and second output signal, and comprise the carrier frequency of relevant sampled signal and the information of phase deviation; And
Based on the information in the 3rd output signal, obtain carrier frequency, and follow the tracks of the phase place of carrier frequency.
13. the method for the error signal of an information that is used to produce the frequency carrier skew that comprises relevant carrier signal, this method comprises:
According to Nyquist criterion at least the first signal and second branch signal are carried out filtering, to export the 3rd signal and the 4th branch signal;
The 3rd signal and the 4th signal are carried out square operation; And
The 3rd signal and the 4th signal are carried out addition, comprise the error signal of the information that the frequency carrier of relevant carrier signal is offset with output.
14. a Frequency Phase Lock loop circuit is used to realize method as claimed in claim 12.
15. a digital television demodulator is used to realize method as claimed in claim 12.
16. a Frequency Phase Lock loop circuit is used to realize method as claimed in claim 13.
17. a digital television demodulator is used to realize method as claimed in claim 13.
18. an average power frequency discriminator is used to realize method as claimed in claim 13.
CNA2005100626139A 2004-04-03 2005-04-01 Mean power frequency discriminator, frequency phase locked loop circuit and digital television demodulator using the same Pending CN1677968A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR23176/2004 2004-04-03
KR1020040023176A KR100594269B1 (en) 2004-04-03 2004-04-03 A frequency phase locked loop circuit and a Advanced Television Systems Committee Digital Television demodulator using the same.

Publications (1)

Publication Number Publication Date
CN1677968A true CN1677968A (en) 2005-10-05

Family

ID=35050270

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2005100626139A Pending CN1677968A (en) 2004-04-03 2005-04-01 Mean power frequency discriminator, frequency phase locked loop circuit and digital television demodulator using the same

Country Status (3)

Country Link
US (1) US20050220241A1 (en)
KR (1) KR100594269B1 (en)
CN (1) CN1677968A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102223498A (en) * 2010-04-14 2011-10-19 新港传播媒介公司 All digital front-end architecture for television with SIGMA-DELTA ADC input
CN101162603B (en) * 2006-09-28 2012-10-10 希捷科技有限公司 Synchronization for data communication
CN103986418A (en) * 2014-05-22 2014-08-13 杨树纲 Digital frequency discriminator and frequency discrimination method thereof
CN107733429A (en) * 2017-09-20 2018-02-23 戴承萍 The band logical frequency discriminator and its frequency discrimination method and its application method of a kind of super low-power consumption

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2469473A (en) * 2009-04-14 2010-10-20 Cambridge Silicon Radio Ltd Digital phase locked loop
KR101829829B1 (en) * 2011-10-04 2018-02-20 에스케이하이닉스 주식회사 Filtering circuit and semiconductor integrated circuit including the same
KR101489597B1 (en) * 2013-10-30 2015-02-04 강원대학교산학협력단 Method for detecting TV signal of ATSC using pattern of synchronization segment

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023491A (en) * 1994-06-21 2000-02-08 Matsushita Electric Industrail Co., Ltd. Demodulation apparatus performing different frequency control functions using separately provided oscillators
US5828705A (en) * 1996-02-01 1998-10-27 Kroeger; Brian W. Carrier tracking technique and apparatus having automatic flywheel/tracking/reacquisition control and extended signal to noise ratio
JPH1056487A (en) * 1996-08-09 1998-02-24 Nec Corp Quadrature demodulation circuit
US6351293B1 (en) * 1998-05-18 2002-02-26 Sarnoff Corporation Decision directed phase detector
US6289061B1 (en) * 1998-09-24 2001-09-11 Sharp Laboratories Of America, Inc. Wideband frequency tracking system and method
KR100348259B1 (en) * 1999-12-21 2002-08-09 엘지전자 주식회사 VSB receiver
JP2002290868A (en) * 2001-03-27 2002-10-04 Texas Instr Japan Ltd Frequency converting circuit, demodulating circuit and tv receiver
US6819911B2 (en) * 2001-04-02 2004-11-16 General Dynamics Decision Systems, Inc. Active interference suppressor utilizing recombinant transmultiplexing
JP2003218968A (en) * 2002-01-22 2003-07-31 Sharp Corp High frequency receiver
KR100505669B1 (en) * 2003-02-05 2005-08-03 삼성전자주식회사 Demodulator circuit of digital television and method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162603B (en) * 2006-09-28 2012-10-10 希捷科技有限公司 Synchronization for data communication
CN102223498A (en) * 2010-04-14 2011-10-19 新港传播媒介公司 All digital front-end architecture for television with SIGMA-DELTA ADC input
CN102223498B (en) * 2010-04-14 2014-01-08 新港传播媒介公司 All digital front-end architecture for television with SIGMA-DELTA ADC input
CN103986418A (en) * 2014-05-22 2014-08-13 杨树纲 Digital frequency discriminator and frequency discrimination method thereof
CN107733429A (en) * 2017-09-20 2018-02-23 戴承萍 The band logical frequency discriminator and its frequency discrimination method and its application method of a kind of super low-power consumption

Also Published As

Publication number Publication date
US20050220241A1 (en) 2005-10-06
KR20050097393A (en) 2005-10-07
KR100594269B1 (en) 2006-06-30

Similar Documents

Publication Publication Date Title
CN1079619C (en) Phase error detecting method and phase tracking loop circuit
CN1677968A (en) Mean power frequency discriminator, frequency phase locked loop circuit and digital television demodulator using the same
CN1106115C (en) Digital carrier wave restoring device and method therefor in television signal receiver
CN1144437C (en) Improved phase estimation for use in reinsertion of phase-modulated signal carrier such as quadrature-amplitude modulated signal carrier
CN1229951C (en) Receiver with comprehensive clock phase position detector
CN1060896C (en) Automatic frequency control method and apparatus therefor
CN101005480B (en) Demodulation circuit and demodulation method
US7751503B2 (en) Method for acquiring timing and carrier synchronization of offset-QPSK modulated signals
CN1881823A (en) Method for correcting sampling frequency offset of a data packet in a communications system
CN1825839A (en) A demodulator and phase compensation method thereof
CN1300947C (en) Device and method for compensating frequency deviation in mobile communication system
CN1691657A (en) Apparatus and method for carrier acquisition of vestigial sideband (vsb) signal
CN1790926A (en) Receiver
US7272197B2 (en) Device for recovering carrier
CN1918873A (en) Method and appts, for carrier recovery in a communications system
US20040161056A1 (en) Digital TV receiver
US6665355B1 (en) Method and apparatus for pilot-aided carrier acquisition of vestigial sideband signal
CN1281039C (en) Frequency correction with symmetrical phase adjustment in each OFDM symbol
CN112468421B (en) Carrier phase recovery method and system based on Q power polarity judgment
CN1286329C (en) Pi/4DQPSK demodulator and its method
CN1813438A (en) Pattern sequence synchronization
US7110475B2 (en) Digital TV receiver
CN1666482A (en) Mobile radio receiver device
CN1269339C (en) Carrier recovery equipment of digital QAM receiver
CN1131627C (en) Apparatus for detecting frequency offset

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20051005