CN1674260A - Method for producing flash storing device - Google Patents
Method for producing flash storing device Download PDFInfo
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- CN1674260A CN1674260A CN200410031216.0A CN200410031216A CN1674260A CN 1674260 A CN1674260 A CN 1674260A CN 200410031216 A CN200410031216 A CN 200410031216A CN 1674260 A CN1674260 A CN 1674260A
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- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 238000000034 method Methods 0.000 claims abstract description 69
- 239000004020 conductor Substances 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 230000005641 tunneling Effects 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 27
- 238000007667 floating Methods 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 51
- 230000008569 process Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000005516 engineering process Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 8
- 238000003701 mechanical milling Methods 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000000428 dust Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000227 grinding Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
A method for preparing flash memory bank includes forming isolation structure on substrate to define out active area and forming mask layer and tunneling dielectric layer on active area substrate, forming a sacrificial layer on substrate and carrying out microimaging etch for it in order to keep sacrificial layer on isolation structure, moving off mask layer, forming conductor layer, moving partial conductor layer off till to expose sacrificial layer top, moving sacrificial layer off, forming control grid on dielectric layer between grids and forming source electrode area / drain electrode area at two sides of control grid.
Description
Technical field
The present invention relates to a kind of manufacture method of memory element, and be particularly related to the manufacture method of a kind of flash memory and floating grid.
Background technology
Flash memory is a kind of can electricity removing and read-only memory (the Electrically ErasableProgrammable Read-Only Memory of programmable, EEPROM), it has the advantage that still can preserve data after can writing, can erasing and cut off the power supply, therefore is extensively a kind of memory element of employing of personal computer and electronic equipment institute.In addition, flash memory is a kind of non-volatile storage (Non-Volatile Memory, NVM) element, it has, and the non-volatility memorizer volume is little, access speed reaches the low advantage of power consumption soon, and the mode that adopts " one one " (Block by Block) to erase when erasing (Erasing) because of its data is so have more the fast advantage of service speed.
Typical flash memory element is made floating grid (Floating Gate) and control grid (Control Gate) with the polysilicon that mixes.And the control grid is set directly on the floating grid, and floating grid is separated by with dielectric layer with controlling between the grid, and between floating grid and substrate with tunnel oxide (Tunneling Oxide) be separated by (that is so-called stacked gate flash memory).This flash memory element is to utilize the plus or minus voltage that is applied on the control grid to control the injection and the discharge of the electric charge in the floating grid, to reach the function of storage.
Figure 1A to Figure 1B illustrate is the part manufacturing process generalized section of existing a kind of flash memory element.
Please refer to Figure 1A, substrate 100 is provided, and in substrate 100, be formed with the active area 104 of a plurality of component isolation structures 102, and on the substrate 100 of active area 104, be formed with tunneling dielectric layer 106 to define element.
Then, on substrate 100, form one deck conductor layer 108, with cladding element isolation structure 102 and tunneling dielectric layer 106.Then, carry out flatening process, remove the conductor layer 108 of part, and make that the top surface of conductor layer 108 is smooth.
Afterwards, please refer to Figure 1B, conductor patterned layer 108, with a plurality of grooves 107 of formation expose portion component isolation structure 102, and the conductor layer 108 that is remained is as floating grid 110.Then, on substrate 100, form gate dielectric layer 112, to cover floating grid 110.Then, on gate dielectric layer 112, form control grid 114.
In above-mentioned technology, (Chemical MechanicalPolishing CMP) comes planarization conductor layer 108, and there is no stop layer as grinding the reference frame that stops in the process of carrying out cmp owing to utilize chemical mechanical milling method.Therefore, the variable thickness of the conductor layer 108 that each technology is remained, promptly the thickness of floating grid 110 can't obtain to control effectively.
On the other hand, if (Gate Couple Ratio, GCR) big more, then the required operating voltage of its operation will be low more for the grid coupling efficiency between floating grid and the control grid.And the method that improves grid coupling efficiency comprises electric capacity that increases gate dielectric layer or the electric capacity that reduces tunneling oxide layer.Wherein, increase the method for gate dielectric layer electric capacity for increasing folded area between control grid layer and the floating grid.Therefore, if the size of formed groove 107 is more little, then folded area can be big more between floating grid and the control grid, and grid coupling efficiency is big more.Yet, in the process of conductor patterned layer 108, the size of groove 107 be subjected to lithography technology its for minute sized process technology limit, promptly can't form more small groove 107.Therefore make that folded area can't further increase between control grid and the floating grid, and then influence the performance of element.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of manufacture method of flash memory, with the grid coupling efficiency between increase floating grid and the control grid, and then improves element efficiency.
A further object of the present invention provides a kind of manufacture method of floating grid, to solve the existing uppity problem of floating grid thickness.
The present invention proposes a kind of manufacture method of flash memory, and the method is that substrate is provided earlier, and is formed with the mask layer of tunneling dielectric layer and patterning on this substrate in regular turn.Afterwards, be etching mask with this mask layer, composition tunneling dielectric layer and substrate are to form a plurality of grooves in substrate.Then, in these grooves, insert insulating material, to form a plurality of component isolation structures.Then, on substrate, form sacrificial material layer, with coverage mask layer and component isolation structure.Afterwards, the composition sacrificial material layer is to form sacrifice layer on component isolation structure.Continue it, remove mask layer, to expose tunneling dielectric layer.Then, on substrate, form conductor layer.Then, the conductor layer that removes part is up to the top that exposes sacrifice layer, to form floating grid, the method for body layer up to the top that exposes sacrifice layer that wherein removes part can be chemical mechanical milling method, and the material of conductor layer has different etching selectivities with the material of sacrifice layer.Then, remove sacrifice layer.Afterwards, on substrate, form gate dielectric layer, to cover floating grid.Continue it, on gate dielectric layer, form the control grid.Then, in the substrate of control grid both sides, form source area and drain region respectively.
Because the thickness of formed its floating grid of flash memory of the present invention is relevant with the thickness of sacrificial material layer, therefore the thickness of floating grid can decide by the thickness of formed sacrificial material layer, so the thickness of floating grid can obtain to control preferably.
In addition, because the present invention can promote folded area between control grid and the floating grid by forming minute sized sacrifice layer, so grid coupling efficiency can obtain to promote, and then improves element efficiency.
The present invention proposes a kind of manufacture method of floating grid, and the method provides substrate earlier, and includes a plurality of component isolation structures in this substrate defining active area, and is formed with tunneling dielectric layer and mask layer in regular turn on the substrate of this active area.Then, on substrate, form sacrifice layer.Then, this sacrifice layer is carried out lithography technology, to retain the sacrifice layer that is positioned on these component isolation structures.Afterwards, remove mask layer, to expose tunneling dielectric layer.Continue it, on substrate, form conductor layer.Then, remove the conductor layer of part up to the top that exposes sacrifice layer.The method of conductor layer up to the top that exposes sacrifice layer that wherein removes part for example is chemical mechanical milling method, and the material of this conductor layer has different etching selectivities with the material of sacrifice layer.Then, remove sacrifice layer.
Extremely thickness is relevant with the thickness of sacrifice layer owing to the formed floating grid of the present invention, so the thickness of floating grid can decide by the thickness of formed sacrifice layer, so the thickness of floating grid can obtain to control preferably.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Figure 1B illustrate is the manufacturing process generalized section of existing a kind of flash memory;
Fig. 2 A to Fig. 2 E illustrate is the manufacturing process generalized section of a kind of flash memory of the preferred embodiment of the present invention.
Description of reference numerals
100,200 substrates, 102,214 component isolation structures
104,204 active areas 106,206,206a tunneling dielectric layer
107,212 grooves
108,208,208a, 218,218a conductor layer
110,220 floating grids, 112,222 gate dielectric layer
114,224 control grids, 202 openings
210 mask layers, 216 sacrificial material layer
The 216a sacrifice layer
Embodiment
Shown in Fig. 2 A to Fig. 2 E, it illustrates the manufacturing process generalized section according to a kind of flash memory of one embodiment of the present invention.
At first, please refer to Fig. 2 A, substrate 200 is provided, this substrate 200 for example is a silicon substrate.Then, on substrate 200, form the mask layer 210 of tunneling dielectric layer 206, conductor layer 208 and patterning in regular turn.The mask layer 210 of patterning has opening 202, and this opening 202 exposes the zone of follow-up predetermined formation component isolation structure.
Wherein, the material of tunneling dielectric layer 206 for example is a silica, and its formation method for example is a thermal oxidation method, and formed thickness for example is 70 dust to 90 dusts.In addition, the material of conductor layer 208 for example is a doped polycrystalline silicon, its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer (not illustrating), carry out the ion implantation step forming it, and formed thickness for example is 500 dust to 1000 dusts.In addition, the material of mask layer 210 comprises with conductor layer 208, tunneling dielectric layer 206 and substrate 200 having the material of different etching selectivities, and it for example is a silicon nitride, and its thickness for example is 1000 dust to 1500 dusts.The method of patterned mask layer 210 for example is a photolithography techniques.
Afterwards, please refer to Fig. 2 B, is etching mask with the mask layer 210 of patterning, removes segment conductor layer 208, tunneling dielectric layer 206, and forms a plurality of grooves 212 in substrate 200, and stays tunneling dielectric layer 206a and conductor layer 208a on substrate 200.Wherein, the degree of depth of formed groove 212 for example is 3000 dust to 4000 dusts.
Then, in groove 212, insert insulating material, forming a plurality of component isolation structures 2 14, and define active area 204.The formation method of component isolation structure 214 for example is to utilize high density plasma chemical vapor deposition method (High Density Plasma Chemical Vapor Deposition, HDP-CVD), after forming one whole layer of insulation material layer (not illustrating), utilize chemical mechanical milling method to remove groove 212 insulation material layer in addition again to form it.
It should be noted that in above-mentioned step, to form tunneling dielectric layer 206 earlier, form the correlation step of component isolation structure 214 again.Therefore can avoid because of forming component isolation structure 214 earlier, and in follow-up carry out thermal process with the process that forms tunneling dielectric layer 206 in, cause and form beak (Bird ' s Beak) at neighbouring element isolation structure 214 places, and then influence the problem of element efficiency.
Then, on substrate 200, form sacrificial material layer 216, with coverage mask layer 210 and component isolation structure 214.Wherein, the material of sacrificial material layer 216 comprises the material that has different etching selectivities with the material of follow-up formed conductor layer, for example is silicon nitride.The formation method of this sacrificial material layer 216 for example is a chemical vapour deposition technique, and formed thickness for example is 1000 dust to 2000 dusts.
Afterwards, please refer to Fig. 2 C, composition sacrificial material layer 216 is to form sacrifice layer 216a on component isolation structure 214.In the present embodiment, because sacrificial material layer 216 is identical (for example being all silicon nitride) with the material of mask layer 210, therefore, remove mask layer 210 in the lump in the process of composition sacrificial material layer 216.And therefore conductor layer 208a can be retained owing to have different etching selectivities with sacrificial material layer 216 and mask layer 210.
Then, on substrate 200, form conductor layer 218.Because conductor layer 218 belows are formed with conductor layer 208a earlier, so conductor layer 218 can be easier to be formed thereon.In addition, the material of conductor layer 218 for example is a doped polycrystalline silicon, and its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer (not illustrating), to carry out the ion implantation step to form it.
Afterwards, please refer to Fig. 2 D, the conductor layer 218 that removes part is up to the top that exposes sacrifice layer 216a, and conductor layer 218a that remains and conductor layer 208a formation floating grid 220.Wherein, the method of conductor layer 218 up to the top that exposes sacrifice layer 216a that removes part for example is chemical mechanical milling method, and in the process of grinding with its sacrifice layer 216a with different etching selectivities as grinding stop layer, therefore the thickness of the conductor layer 218a that is remained can be identical with the thickness of sacrifice layer 216a.So the thickness of floating grid 220 can obtain to control preferably.In other words, in technology each time, the thickness of conductor layer 218a can be consistent by the sacrifice layer 216a that forms same thickness, and then makes the thickness of floating grid 220 be consistent.
In addition, formerly form in the process of sacrifice layer 216a,, therefore can increase the size of conductor layer 218a owing to can form the less sacrifice layer 216a of size, and then make that folded area increases between floating grid 220 and the control grid, and make grid coupling efficiency increase.
Continue it, please refer to Fig. 2 E, remove sacrifice layer 216a, the method that removes of this sacrifice layer 216a comprises wet etching, and it for example is to utilize phosphoric acid solution as etching solution.Then, on substrate 200, form gate dielectric layer 222, to cover floating grid 220.Wherein, the material of gate dielectric layer 222 for example is a silicon oxide/silicon nitride/silicon oxide, and its formation method for example is to form one deck silicon oxide layer with thermal oxidation method earlier, utilize chemical vapour deposition technique to form silicon nitride layer and another layer silicon oxide layer again, and the thickness of formed silicon oxide/silicon nitride/silicon oxide for example is 40 dust to 50 dusts/45 dust to 70 dusts/50 dust to 70 dusts.Certainly, the material of gate dielectric layer 222 also can be silica/silicon nitride etc.
Continue it, on gate dielectric layer 222, form control grid 224.Wherein, the material of control grid 224 for example is a doped polycrystalline silicon, and its formation method for example is after utilizing chemical vapour deposition technique to form one whole layer of undoped polycrystalline silicon layer (not illustrating), to carry out the ion implantation step to form it.Afterwards, form source area (not illustrating) and drain region (not illustrating) respectively in the substrate 200 of control grid 224 both sides, its formation method for example is to carry out the ion implantation step, forms it to inject admixture in the substrate 200 of control grid 224 both sides.And the follow-up technology of finishing flash memory is that those skilled in the art are known, does not repeat them here.
It should be noted that, the present invention is except the above embodiments, in another preferred embodiment, after the step that removes mask layer 210 shown in Fig. 2 C, also comprise and remove conductor layer 208a earlier, form conductor layer 218 and follow-up step shown in Fig. 2 D to Fig. 2 E afterwards more in regular turn, to finish the making of flash memory.Its floating grid 220 of thus formed flash memory only is made of conductor layer 218a.In addition, in another preferred embodiment, in the step that substrate 200 is provided shown in Fig. 2 A, only on substrate 200, form tunneling dielectric layer 206 and mask layer 210, therefore its floating grid 220 of formed flash memory equally only is made of conductor layer 218a.
In sum, the present invention has following advantage at least:
1. because the thickness of formed its floating grid of flash memory of the present invention is relevant with the thickness of sacrificial material layer, therefore the thickness of floating grid can decide by the thickness of formed sacrificial material layer, so the thickness of floating grid can obtain to control preferably.
2. because the present invention can promote folded area between control grid and the floating grid by forming minute sized sacrifice layer, so grid coupling efficiency can obtain to promote, and then improves element efficiency.
3. because the present invention forms tunneling dielectric layer earlier, form the correlation step of component isolation structure again.Therefore can avoid because of elder generation forms component isolation structure, and carry out in the process of thermal process with the formation tunneling dielectric layer, cause at neighbouring element isolation structure place formation beak, and then influence the problem of element efficiency in follow-up.
Though the present invention is open in conjunction with the preferred embodiments as above; so it is not to be used for limiting the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is with being as the criterion that claims were defined.
Claims (20)
1. the manufacture method of a flash memory comprises:
One substrate is provided, and is formed with a mask layer of a tunneling dielectric layer and patterning on this substrate in regular turn;
With this mask layer is an etching mask, and this tunneling dielectric layer of composition and this substrate are to form a plurality of grooves in this substrate;
In those grooves, insert an insulating material, to form a plurality of component isolation structures;
On this substrate, form a sacrificial material layer, to cover this mask layer and those component isolation structures;
This sacrificial material layer of composition is to form a sacrifice layer on those component isolation structures;
Remove this mask layer, to expose this tunneling dielectric layer;
On this substrate, form one first conductor layer;
Remove this first conductor layer of part up to the top that exposes this sacrifice layer, to form a floating grid;
Remove this sacrifice layer;
On this substrate, form a gate dielectric layer, to cover this floating grid;
On this gate dielectric layer, form a control grid; And
In this substrate of these control grid both sides, form an one source pole district and a drain region respectively.
2. the manufacture method of flash memory as claimed in claim 1, wherein the material of this sacrificial material layer has different etching selectivities with the material of this first conductor layer.
3. the manufacture method of flash memory as claimed in claim 2, wherein the material of this sacrificial material layer comprises silicon nitride.
4. the manufacture method of flash memory as claimed in claim 1 wherein removes the method for this first conductor layer of part up to the top that exposes this sacrifice layer and comprises chemical mechanical milling method.
5. the manufacture method of flash memory as claimed in claim 1, wherein this sacrificial material layer is identical with the material of this mask layer, and in the process of this sacrificial material layer of composition, removes this mask layer simultaneously.
6. the manufacture method of flash memory as claimed in claim 5, wherein the material of this sacrificial material layer and this mask layer comprises silicon nitride.
7. the manufacture method of flash memory as claimed in claim 1, wherein the material of this first conductor layer comprises doped polycrystalline silicon.
8. the manufacture method of flash memory as claimed in claim 1 wherein also comprises between this tunneling dielectric layer of this substrate that is provided and this mask layer being formed with one second conductor layer, and expose this second conductor layer after removing this mask layer.
9. the manufacture method of flash memory as claimed in claim 8, wherein after removing this mask layer with form before this first conductor layer, also comprise removing this second conductor layer.
10. the manufacture method of flash memory as claimed in claim 8, wherein the material of this second conductor layer comprises doped polycrystalline silicon.
11. the manufacture method of a floating grid comprises:
One substrate is provided, includes a plurality of component isolation structures in this substrate defining an active area, and be formed with a tunneling dielectric layer and a mask layer in regular turn on this substrate of this active area;
On this substrate, form a sacrifice layer;
This sacrifice layer is carried out a lithography technology, be positioned at this sacrifice layer on those component isolation structures with reservation;
Remove this mask layer, to expose this tunneling dielectric layer;
On this substrate, form one first conductor layer;
Remove this first conductor layer of part up to the top that exposes this sacrifice layer; And
Remove this sacrifice layer.
12. the manufacture method of floating grid as claimed in claim 11, wherein the material of this sacrifice layer has different etching selectivities with the material of this first conductor layer.
13. the manufacture method of floating grid as claimed in claim 12, wherein the material of this sacrifice layer comprises silicon nitride.
14. the manufacture method of floating grid as claimed in claim 11 wherein removes the method for this first conductor layer of part up to the top that exposes this sacrifice layer and comprises chemical mechanical milling method.
15. the manufacture method of floating grid as claimed in claim 11, wherein this sacrifice layer is identical with the material of this mask layer, and in the process that forms this sacrifice layer, removes this mask layer simultaneously.
16. the manufacture method of floating grid as claimed in claim 15, wherein the material of this sacrifice layer and this mask layer comprises silicon nitride.
17. the manufacture method of floating grid as claimed in claim 11, wherein the material of this first conductor layer comprises doped polycrystalline silicon.
18. the manufacture method of floating grid as claimed in claim 11 wherein also comprises between this tunneling dielectric layer of this substrate that is provided and this mask layer being formed with one second conductor layer, and expose this second conductor layer after removing this mask layer.
19. the manufacture method of floating grid as claimed in claim 18, wherein after removing this mask layer with form before this first conductor layer, also comprise removing this second conductor layer.
20. the manufacture method of floating grid as claimed in claim 18, wherein the material of this second conductor layer comprises doped polycrystalline silicon.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100312160A CN1309053C (en) | 2004-03-26 | 2004-03-26 | Method for producing flash storing device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100312160A CN1309053C (en) | 2004-03-26 | 2004-03-26 | Method for producing flash storing device |
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| CN1674260A true CN1674260A (en) | 2005-09-28 |
| CN1309053C CN1309053C (en) | 2007-04-04 |
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| CNB2004100312160A Expired - Fee Related CN1309053C (en) | 2004-03-26 | 2004-03-26 | Method for producing flash storing device |
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| CN107799528A (en) * | 2016-08-30 | 2018-03-13 | 华邦电子股份有限公司 | The manufacture method of memory element |
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| TW413948B (en) * | 1998-11-04 | 2000-12-01 | Taiwan Semiconductor Mfg | Manufacture method to increase the coupling ratio between the source and floating gate |
| KR100406179B1 (en) * | 2001-12-22 | 2003-11-17 | 주식회사 하이닉스반도체 | Method of forming a self aligned floating gate in flash memory cell |
| CN1260821C (en) * | 2002-03-15 | 2006-06-21 | 旺宏电子股份有限公司 | Nonvolatile memory and its manufacturing method |
| CN1225782C (en) * | 2002-12-27 | 2005-11-02 | 中芯国际集成电路制造(上海)有限公司 | Improved mask ROM process and element |
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