TW413948B - Manufacture method to increase the coupling ratio between the source and floating gate - Google Patents

Abstract

This invention provides a process that can produce source to floating gate coupling area and shallow trench isolation as well as shrinking the device size and raise the program speed. The process includes the following steps. (1) Form the first oxide and nitride layers upon the substrate and then define trench isolation region into the interior of the substrate. (2) Form a thin, liner oxide layer on the trench and fill the second oxide in the trench and then etch back the second oxide till it below the substrate surface for 0.1 to 0.2 mu m. (3) Use sacrificial oxide to remove the etching contamination and proceed thermal oxidation process to get good quality gate oxide. (4) The first poly silicon is formed upon the gate and second oxides and then forms another nitride layer to be the hard mask of the oxide layers. After the floating gate is defined, use high temperature thermal oxidation process to form oxide area and remove the remaining nitride and the first poly silicon layers by using the oxide area as hard mask. (5) Form inter-poly oxide layer upon the first poly silicon layer and form the second poly silicon layer. After the word-line is defined, proceed the ion implantation of common source and form spacer on the sidewalls of the first and second poly silicon layers. Finally, proceed drain ion implantation to form the split-gate flash memory arrays.

Description

413948 ΙΓ 5. The photoresist case of the mysterious line of the invention description () covers all areas to define the word 绦, as shown in Figure 16B is a top view of the results of this process. Next, the etching process of the word line is performed by dry etching to form the word line 90. Please refer to the cross-sectional schematic diagram along bV shown in FIG. 7A, and then expose another photoresist pattern of the common source region 95 ( (Not shown) Defines Longjingjing 95. Then apply the β sub-plant. Remove photoresist. In addition, a high-temperature hafnium process and a non-homotropic etch-back technique are implemented to form an oxide layer spacer on the sidewalls of the first polycrystalline silicon layer 55 and the second oxide layer 90, and to suspend the impurity semiconductor crystals of 殛 g. The circle 10 is scattered inside to form a source junction, and diffuses to the semiconducting wafer 10 under the suspended gate region to increase the ratio, please refer to FIG. 7B. Then, the partition wall 98 is formed. Another photoresist pattern (not shown) exposes areas other than the drain region. Finally, another port is planted with n-type conductive rafters to form the drain region 99. Referring to FIG. 7C, a top view after this process is shown. Printed by the National Standards Bureau of the Ministry of Economic Affairs of the Second Consumer Cooperative ------------ · I --- It is worth noting that the opening and closing of the suspension gate by electrons from the source is tenfold. As far as memory is concerned, the more gate area the floating gate can cover or the thinner the gate oxide layer, the greater the programming speed. However, reducing the thickness of the gate oxide layer has the problem of data retention time. At this point, generally more efforts are made to increase the source area coverage of more suspended gates. This is the problem of penetration from the source region to the drain region. Therefore, a combination of manufacturing process from the source region to the suspended gate using the manufacturing process in the shallow trench isolation area is highly expected. It is also a problem to be solved by the present invention. The purpose and summary of the invention: -5- This paper size is applicable to the Chinese National Standard (CNS) Λ4 present grid (2I0X2W male flower) 413948! Γ 5. Description of the invention () The purpose of the present invention is to provide a process method that can achieve the use of shallow trenches In the separation system, the coupling area between the source region and the suspension gate 4 is often manufactured at a fast programming speed. Another object of the present invention is to provide a manufacturing method for manufacturing a shallow trench isolating process by simultaneously manufacturing more of the combined area from the source recovery area to the suspended gate electrode to reduce the size of the suspended gate region to increase the degree of aggregation. Printed by Zhengong Consumer Cooperative of the Central Bureau of Economic Affairs (^ 先 " -Read the memorandum of attention and then ^ Bone page: | Based on the above-mentioned purposes, the present invention forms a trip flash memory A method for manufacturing a body formed on a semiconductor crystal i includes at least the following steps: first, a first oxide layer and a first nitride layer are sequentially formed on the semiconductor crystal i. Then, a trench isolation region, a trench isolation region depth, and a semiconductor are defined. Inside the wafer. After that, a thin oxide layer is formed to line the trench isolation area, and then a second oxide layer is used to isolate the cone area. After that, the second oxide layer is etched back to be 0.1 below the surface of the conductor wafer. -0.2μπι. Then, the sacrificial oxide layer is used to remove the etching contamination, and then the beta thermal oxidation process is used to form a high-quality gate oxide layer on the semiconductor wafer. The first polycrystalline silicon f is then formed on the gate oxide layer and the first On the oxide layer: Then, another nitride layer is formed as a curtain for forming the oxidation region. After defining the size of the suspended gate region, the oxidation region is formed by a high-temperature thermal oxidation process, and the oxidation region is used as Generation screen, remove the remaining nitride f and A first polycrystalline silicon layer. An intermediate polycrystalline silicon oxide layer is formed on the first polycrystalline silicon layer. Then, a second polycrystalline silicon layer is formed. After a predetermined zigzag line is defined, common source chirping is performed. After the heterozygous seeds are implanted, an inverted wall of the first polycrystalline silicon, f, and second polycrystalline silicon layers is then formed. Finally, the lotus seedlings of the lotus root are implanted to form a flash memory array that is opened. -6- This paper size applies to China National Standards (CNS) Λ4 grid (210X 297 total) 413948

Λ. IT 5. Description of the invention 明 Simplified diagram 箪 Simplified diagrams are supplemented by Chinese characters, and then the examples will be implemented: Explaining the details and details of Jiage

The manufacturing method of the quick-disc sub-branch is traditionally shown as a 0 A drawing, a cross-section of the area, and a 0-ditch canal is formed in the form of a hard mask layered in the form of a screen.

Nitrogen is the step of this array after observing in B map.

I can be used to create the method of remembering the flash memory quickly. The method of making the memory of the flash memory is shown in the following formula: f ® Μ surface isf; Three steps after the step

The JMJ 歹 Array memory flashes are divided into B and Flash flashes are divided into B. Figures are taken from three planes; the horizontal view is placed in the posterior position. Figures of the system are shown in Figure 4, which shows the division of the four horizontal planes of plane A.

B ----- II--! 1 ί] —II-____ -Λ '^ wendubei `` 6's note ^? Item again ^' ^; page) Form of body column memory array body flash; & i brake flash diagram cutting A horizontal five figure formation M shows the display surface brake view floating body column memory array memory flash memory quick score fast brake system system method Fang Tong Printed by the Central Ministry of Standards and Technology of the People's Republic of China on the Ayi 7 ^ Picture has been transmitted to the display of Arols; "Seven Figures, Figures, Cut Views, Slopes, and Ditches, Six Figures The control column ', ¾ Ti Li Yi Yi Ji Ji 3 / The quick release gate is divided into the B manufacturing method, which is transmitted to show the seven B-graphs on one side of the cross-section; the body-direction memories on the first side of the cross-section The paper size of the Fang Ji line Shuangyuan quick position brake is applicable to the Chinese National Standard (CNS) Λ4 specification (2IOX 297 public epidemic) 413948 ΙΓ 5. Description of the invention () Surface a, s7c is the flash memory ceremony for opening the gate Top view of the array; Figure 8a shows the top view of the active area and trench isolation area defined by the photoresist method and engraving using the method of this chopstick, and Figure 8b shows the process of the flash memory array after this step. Top view; Figure 9A shows backfilling with an oxide layer by the method of the present invention A cross-sectional view of a trench isolation area. Figure 9B is a schematic cross-sectional view of the planarization process. Figure 9C is a schematic cross-section view covering all areas with a photoresist pattern that exposes the trench isolation area. Figure 9D is a direct nitriding process. The layer is a schematic cross-sectional view of the result after the mask 3 is etched; 'FIG. 10A shows the cross-section of the method of the present invention after removing the first oxide layer on the semiconductor wafer® and the oxide layer deposited in the etched trench isolation region Schematic diagram, Figure 10B is a top view of the flash memory array after this step. Figure 11A shows a cross-sectional view of the method of the present invention after the memory position is defined by a photoresist pattern. Top view of the fast memory array after the process reaches this step: FIG. 12A shows a schematic cross-sectional view of an oxide region formed by the method of the present invention. Figure 12: Top view of the flash memory array after this step in the B-series process; The policy of the Central Government Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives of India-'T ^ " -Reading & ^ 5 items to fill in again: " (Melon page) FIG. 13A shows a cross-sectional view of the method of the present invention, using an oxide region as a mask layer to etch and expose a nitrided layer and a polycrystalline silicon layer to form a floating gate. After the step, the top view of the flash memory array S: Figure 14A shows the cross-sectional view of the control gate defined by the method of the present invention, and Figure 14B is the process to this step, the flash memory array is opened- 8- The size of this paper is applicable to the National Standards of China (CNS) Λ4 (210X2W)

Five. The top view of the description of the invention: and Figure 15A shows the cross-sectional view of the flash memory cross section of the opening block in the direction of a-a1 by the method of the present invention, and Figure 15B is taken along the direction of b-b_ Cross-sectional view of the opening flash memory of the common source area, Figure 15C. Cross-section view of the opening flash memory of the skeletal skeleton along the bl / direction of the plant source / drain region, Figure 15D. Flash memory looks down at the circle. 5. Detailed description of the invention: As described in the background of the invention, the closing of the flash memory of the switching gate is determined by the ability of the heterodyne from the source below the suspension gate to diffuse to the suspension gate. In order to increase the formation ratio without causing the penetration of the source region to the drain region, it must be considered in a two-dimensional space other than the one-dimensional one of the source pin and the drain. On the other hand, when the component channel is reduced from 0.35 μm to 0.25 μm or less, it is necessary to adopt a shallow trench isolation (STI) method for short. In view of this, the present invention is directed to the above-mentioned problem to provide a process method for using the shallow trench to separate chickens in the process of manufacturing more structured areas to achieve the purpose of increasing the composition ratio. The details of the present invention can be described in detail with reference to the tables and figures. As shown in the cross-sectional schematic diagram of the eighth consumer cooperative of the Ministry of Economic Affairs of the Central Government Bureau of Consumer Affairs (4 especially "-please read the back-minus matters again on this page) \ on a semiconductor wafer 100 (this semiconductor Yue_ can be capped silicon, single crystal germanium, single crystal silicon germanium alloy, or single crystal gallium arsenide, which can be an epitaxial layer that is only one of the above semiconductor materials. It can be used at a high temperature of about i5 (M100 ° C) Form a pad of oxide layer 102 (first oxidation -9- this paper size applies Chinese National Standards (CNS) Λ4 now (210X29? Public) 413948 Λ7 ΙΓ 5. Description of the invention () layer). This layer of oxide is used for In order to ease the nitriding, the f-force of the sintered crystal s is then used, and then the first nitride layer 1 1 5 is fully deposited by the LPCVD method. The deposited thickness is about 1 50- 250 nm, typical value is 1 60 am. Finally, a mask pattern 120 is used to define the active area 122 and the shallow trenches 1 to 25. Then, a dry semiconductor method is used to form a recessed semiconductor wafer with a depth of about 350. -650 nm trench 125. The depth of trench 125 is the height from the bottom of the trench to the top surface of the wafer. Refer to FIG. 9A for a schematic cross-sectional view. Firstly, the primary curtain layer 120 is removed, and then an oxide layer 130 (second oxide layer) is lined with a high temperature thermal oxidation process temperature of about 850-U00 ° C. This oxide layer 130 has the function of recovering from previous dry etching to define shallow trench isolation 25 etching damage. In addition, the density of the oxide layer grown by the oxidation method is also better, and the corners are smoother. after that. A third oxidation, f 1 35, is then deposited by chemical vapor deposition at a temperature of about 400-650 ° C. And fill the ditches 1 to 25. The process of chemical / sock-type polishing using the nitrided layer 1 15 as the polishing stop layer is performed next. Printed by the Central Government Bureau of the Ministry of Economic Affairs and Consumers' Cooperatives (" Please refer to the remarks on the back of this page before you ^ this page). Then, in order to connect to the invention, the source source area is added to the suspension gate area. There is rain in the face. The first approach is shown in the schematic cross-sectional view in Figure 9B. First, the third oxide layer 135 is used as a hard mask, and the hot-phosphate removing nitride layer is used to remove the pad oxide layer 102 by dilute hydrofluoric acid or BOE wetting. In another method, the nitride layer 115 and the pad oxide layer 102 are removed by a non-anisotropic dry etching method. Next, cover the silicon wafer with a photoresist pattern 1 3 8 while exposing the trench portion as shown in Figure 9C, and then etch back the trench 125 with dry etching or with diluted hydrofluoric acid or BOE. The oxide layer covers the third oxygen layer 135 and -10-. This paper size applies Chinese National Standards (CNS) M specifications (210X 297 KRW) 413948 A B " Central Bureau of Standards, Ministry of Economic Affairs, Cooperative Cooperatives Description of the invention (dioxide f (mass pad oxidation, f) 1 3 0. 3 The depth of the bismuth etch is about 0. 1-ο · 2 μιη = finally removing the photoresist pattern 1 3 8. The results are shown in FIG. 10A For the second method, please refer to FIG. 9D. First, the first nitride layer 115 is not removed, and the first nitride layer is used as a hard screen. The dry etching method or diluted hydrofluoric acid or BOE is used to etch back. For oxidation in the trench 125, see the second oxide layer 135 and the oxide layer liner 130. The depth of the etch-back is about 0.1-0.2 μm below the surface of the wafer. Then, the first nitride layer is removed with a hot phosphoric acid solution. 115. Figure 10A shows the top view of the results after this process. To reduce etching damage and etching pollution, first use high temperature The thermal oxidation process is longer by a sacrificial oxide layer and then removed. As shown in Figure 11A, a high-temperature thermal oxidation process is used to form a clean gate oxide with a thickness of about 7-10 nm at about 900-1 100 ° C. Layer 150. Next, all trenches 125 are back-filled with a first pseudocrystalline silicon layer 155 by LPCVD chemical vapor deposition at about 500-650 ° C. Next, a second nitride layer 160 is deposited on the first polycrystalline silicon layer. 1 5 5. Finally, cover all areas with another photoresist pattern 1 65 to expose only the position of the memory cover element 1 70. S11B shows the top view of the flash memory array that opens and closes to this process. Please Referring to the schematic cross-sectional view shown in FIG. 12A, the dry-etching method removes the second nitride layer 1 60 of the memory cell region 1 70. After removing the photoresist, the high temperature thermal oxidation process is about 900-1 100 ° Since the adjacent second nitride layer 5 screen 1 60 and the grain boundary of the first polycrystalline silicon layer 15 5 can provide a rapid diffusion path of oxygen, therefore, in the center of the first polycrystalline silicon layer 1 5 5 It oxidizes faster than the edges, resulting in a sharper edge. The highest point of the oxidized region 1 70 is about 150 nm. After partial oxidation The thickness of the first silicon layer is about 50-150 nm. -11- This paper size is applicable to the Chinese National Standard (CNS) Λ4 present grid (2! Ox2F total) (Shi Yuan "-^ back to the other Note: s re ^ page] Order the first polycrystalline silicon 155 in the trench isolation zone. Usually, HBr / Cl2 / 02 gas plasma engraving is a good selectivity for Si02 and only engraved crystalline silicon An etching method. Next, please refer to the schematic cross-sectional view shown in FIG. 14A. Using a high temperature thermal oxidation method at a temperature of about 900-1 to 100 ° C, a dielectric silicon oxide layer 180 of about 12-25 nm thick is formed. Alternatively, the dielectric silicon oxide layer 180 may be formed in an ONO manner. In the ONO process, first, a high temperature thermal oxidation process is used to first form hafnium oxide and then apply LPCVD to deposit a nitride layer and then oxidize again to form an oxide layer. Of course, the thicker the nitride layer, the thinner the oxide layer will be. This is already a known technique. Therefore, I will not repeat them here. Other mesogenic polycrystalline silicon oxide layers such as Ta205 layer, Ti02 layer, LiNb03 and the central standard of the Ministry of Economic Affairs?-Bureau 1®: Printing by Industrial Cooperative Cooperative ^ Η 5. Description of the invention () 1

I! I

Please refer to the schematic cross-sectional view of the decoration shown in i. 13A, with the oxide group 1 70 J as the hard type curtain, and the third oxide layer 13 5 as the engraving termination f, with hot phosphorus [

^ The acid solution etches the remaining second nitride f 1 60. Dry etching

Back I

I i I ί i again

* k (I

Jv binding

The i I (Pb, La) (Zr, Ti) 〇3 layers are all high dielectric constant, so they are also good-i choice. Then, a comprehensive formation of a second complex crystalline silicon 185 that is simultaneously doped with n-type conductive ions on the meso-multicrystalline silicon oxide layer 180 is obtained. This _ (1) The second polycrystalline silicon layer 180 is thicker, about 100-250 nm. See Fig. 10 23 Β. I shows the fruit of J Μ. The drawing of the tenth process of the fourth one is taken as a reference. Please set the field S to cover the meaning of the word shown. 7 0 8 1 pattern view. The four-to-ten fixed map is a reference to Qingxing-3, and the engraved etched dry five-line language characters are engraved in the sequence of AM, so Ο «90 meaning 1 a with .I--1 — 丨--· «ml 2- This paper method scale is applicable to the Chinese National Standard (CNS) Λ4 Regulation ί 210X297 public $ _) 413948 Η 7 5. Please refer to Figure 13 after the description of the invention () B is shown along the cross-section of b-b '; f 囷 is shared by another exposure: _ the original photoresistance region 1 95 photoresist case 1 98 defines the source region 1 95. Then apply n + ion implantation. The energy and dose are about 20-60 keV and lxlOi4-lxl0] 6 / cm2, respectively. Remove the photoresist 8 case 198. Another high-temperature oxidation process temperature of about 800-95 CTC and non-isotropic etch-back technology are used to form an oxide layer spacer 2 01 on the sidewalls of the first polycrystalline silicon layer 15 and the second oxide layer 1 90 And diffuse the Zagar semiconductor wafer 100 in the floating gate region to form a source junction, and diffuse to the semiconductor crystal picture 100 under the floating gate region to increase the tip ratio, please refer to FIG. 15B. Then, the partition wall 201 is formed. Finally, another tap is implanted with an n-type conductive pin to form a drain region 205. The n-type impurity is selected from one of the tritium group consisting of arsenic and phosphorus. 3 The energy and dose of the plant are about 20-60 keV and ixl0t4-lxl016 / cm2, respectively, to form a drain electrode. See FIG. 15C. Figure 15D shows a top view after this process. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention; any other effective changes or modifications made under the spirit disclosed by the present invention should be included in the following Within the scope of the application for patents mentioned in the above 3 Central Government Bureau of Standards, Ministry of Economic Affairs and Consumer Cooperatives Seal 13-13 This paper is in accordance with the Chinese National Standard (CNS) A4 standard (210X297)

Claims (1)

Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * 'generation 413948 t, patent application scope 1. A manufacturing method for increasing the source area to the ratio of the suspended idler to memory, which is formed on a semiconductor wafer, at least The method includes the following steps: forming a first oxide layer on the semiconductor wafer; forming a first nitride layer on the first oxide layer; defining a trench isolation region, the trench isolation region being deep inside the semiconductor wafer; forming an oxide A layer is lined on the bottom and sidewalls of the trench isolation area; forming a second oxide layer on the first nitride layer and filling the trench isolation area; performing a planarization process using the first nitride layer as a termination layer; Etching the first nitride layer, using the first oxide layer as a stop layer; etching the first oxide layer to expose the surface of the semiconductor wafer: covering all parts with a first photoresist pattern exposing the trench isolation region; proceeding Etch back the second oxide layer and the oxide layer liner not covered by the first photoresist pattern; remove the first photoresist pattern; form a gate oxide layer on the semiconductor wafer: A first polycrystalline silicon layer on the gate oxide layer and the second oxide layer; forming a second nitride layer on the first polycrystalline silicon layer; exposing a second light of a predetermined suspended gate region The resist pattern covers the second nitride layer: the exposed second nitride layer is etched to expose the first polycrystalline silicon layer; the second photoresist pattern is removed: the exposed first complex silicon layer is oxidized to form Oxidation zone 'is based on this 14-14- This paper size applies to Shen® National Standard (CNS) Al specification (21ϋ X 297 g) Γ:;' take -------- order ------ --- Line- 彳 bu (please read the notes on the back before filling out this page), printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * 'generation 413948 t, the scope of patent application 1. increasing the source area to the suspended idle pole A manufacturing method for forming a quick-memory memory on a semiconductor wafer, the method includes at least the following steps: forming a first oxide layer on the semiconductor wafer; forming a first nitride layer on the first oxide layer ; Define the trench isolation area, the trench isolation area is deep and inside the semiconductor wafer; forming an oxide layer lining Forming a second oxide layer on the first nitride layer and filling the trench isolation area; performing a planarization process using the first nitride layer as a stop layer; etching the first A nitride layer, using the first oxide layer as a termination layer; etching the first oxide layer to expose the surface of the semiconductor wafer: covering all parts with a first photoresist pattern exposing the trench isolation area; The first photoresist pattern covers the second oxide layer and the oxide layer lining; removing the first photoresist pattern; forming a gate oxide layer on the semiconductor wafer: forming a first polycrystalline silicon layer on the gate On the second oxide layer and the second oxide layer; forming a second nitride layer on the first polycrystalline silicon layer; covering the second nitride layer with a second photoresist pattern exposing a predetermined floating gate region Above: The exposed second nitride layer is etched to expose the first polycrystalline silicon layer; the second photoresist pattern is removed: the exposed first polycrystalline silicon layer is oxidized to form an oxidized region ' -This paper size applies to Shen® National Standard (CNS) Al Specifications (21ϋ X 297g) Γ:; 'take -------- order --------- line— 彳 bu (please read the precautions on the back before filling this page) 413948 λ8 CS ns 6. The scope of patent application is that the nitride layer is an etch stop layer; f Please close the back of the page first; ± Notes before filling out this page) Remove the second nitride layer to expose the first polycrystalline silicon layer: The first polycrystalline sand layer is etched and exposed, and the second oxide layer and the gate oxide layer are used as an etching stop layer; a polycrystalline silicon oxide layer is formed on the first polycrystalline silicon layer; a second polycrystalline silicon layer is formed; Layer on the mesogenic polycrystalline silicon oxide layer; covering the second polycrystalline sand layer with a third photoresist pattern exposing a predetermined zigzag line; and etching the second polycrystal not covered by the third photoresist pattern The flash memory is formed by a silicon layer and an oxide region as a termination layer. 2. The method of the first scope of the application ', wherein the first nitride layer is about I 50-25 ϋ nm thick, and is formed at 75 0-85 G ° C by a low pressure chemical vapor deposition method. 3. For the method of applying for the first item of the patent scope, wherein the above-mentioned step of defining the trench isolation area comprises: covering the first nitride layer with a photoresist pattern that exposes the predetermined trench isolation area: the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy Printing and etching the first nitride layer, the first oxide layer, and the semiconductor wafer not covered by the photoresist pattern; and removing the photoresist pattern. 4. If the method of applying for the third item of the patent scope, wherein the above-mentioned trench isolation area is from -15- This paper size applies Chinese National Standard (CNS) Al Regulations (210 X 297 mm) 413948 Λ8 RH CS I '> S VI. Patent application: The surface of the semiconductor wafer to the bottom of the trench isolation zone is about 350-650 deep. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The layer lining is formed by a high-temperature thermal oxidation process, and the temperature is about 85 0-1 100 ° C. 6. The method according to item 1 of the patent application range, wherein the above-mentioned second oxide layer is formed by a chemical vapor deposition method at 400-6 00 ° C. 7. The method according to item 丨 of the scope of patent application, wherein the planarization process described above is a method of chemical / mechanical honing. 8. As described in Method 1 of the scope of the patent application, wherein the above-mentioned back-to-touch step is to etch back the second oxide layer to the surface of the wafer 0.1-0.2 μΓΠ purpose to create additional coupling area. 9. The method according to item 1 of the patent application scope, after the step of etching the first oxide layer, further comprises: forming a sacrificial oxide layer on the semiconductor wafer by a thermal oxidation process; and removing the sacrificial oxide layer. 10. The method according to item 1 of the scope of patent application, wherein the above-mentioned gate oxide layer is deposited at a temperature of 900- 1 1 00 ° C to a thickness of about 7-10 ηπ ^ -16- (CNLS) Al gauge (21ϋ X 297mm. ¾) l · Cracking -------- Order · --------- (Please read the precautions on the back before filling this page) Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperative Cooperative 413948 f 6. Application for Patent Scope 15: For the method of the scope of Patent Application No. 14 where the ion implantation in the source region is implanted with η-type conductive ions' energy And doses are approximately 20-W keV and U 1 〇! 4-1 X 1 lb, cm :. 16. The method of claim 15 in which the aforementioned η-type conductive ion system is selected from one of the group consisting of phosphorus and arsenic. 1 7. As the scope of patent application! The method of item 5, wherein the ion implantation in the drain region is implanted with n-type conductive ions, and the energy and dose are about 20-60 keV and 1 X 1 0i4-1 X 1 0 / cm2, respectively. 18. The method according to claim 17 in which the aforementioned η-type conductive ion is selected from the group consisting of phosphorus or arsenic. 19. A manufacturing method for forming a flash memory on a semiconductor wafer that increases the coupling ratio of the source region to the floating gate, the method includes at least the following steps: engraving a first oxide layer on the semiconductor wafer; forming A first nitride layer on the first oxide layer; defining a trench isolation region, the trench isolation region being deep inside the semiconductor wafer: forming an oxide layer lining the bottom and sidewalls of the trench isolation region; forming a second An oxide layer is on the first nitride layer and fills the trench isolation area; the second oxide layer and the partial oxide layer are etched back to etch back to the trench isolation area, leaving a portion of the second oxide layer and the portion Within the oxide layer -18- This paper size is suitable for 0® furniture standard (CNS) Λ. 丨 gauge (210 X 297 cm) • --- h --------- 泉 —— (Please Read the precautions on the back before filling out this page)) SJ. Line 413948 A8 ns CH ns VI. Patent Application Scope Printed by the Intellectual Property Bureau Employees Consumer Cooperatives of the Ministry of Economic Affairs I use the first nitride layer as a rigid single screen; Etching the first nitride layer 1 with the first oxide layer as a stop layer; Carving the first oxide layer to expose the surface of the semiconductor wafer: forming a gate oxide layer on the surface of the semiconductor wafer: forming a first polycrystalline silicon layer in a second region of the gate oxide layer and the trench isolation region On the oxide layer; forming a second nitride layer on the first polycrystalline silicon layer; covering the second nitride layer with a first photoresist pattern exposing a predetermined suspended gate region: etching the exposed second The nitride layer is exposed to expose the first polycrystalline silicon layer: removing the first photoresist pattern; oxidizing the exposed first polycrystalline silicon layer to form an oxidized region, and using the denitrifying nitride layer as an etch stop layer: removing The second nitrided layer is used to expose the first polycrystalline silicon layer; the first polycrystalline silicon layer is etched and exposed; the second oxide layer and the gate oxide layer are used as an etching stop layer; and a dielectric polycrystalline silicon oxide layer is formed. On the first polycrystalline silicon layer; forming a second polycrystalline silicon layer on the mesocrystalline silicon oxide layer: covering the second polycrystalline silicon layer with a second photoresist pattern exposing a predetermined zigzag line : And etch the second polycrystalline silicon layer that is not covered by the second photoresist pattern, with the oxidized area as Tong stop layer into the flash memory. 20. The method of item 19 in the scope of patent application, in which the above-mentioned first nitride layer -19- this paper size is applicable to the National Standard (CNS) Al specification X 297 G. ¾) Γ. ---- ----- Order --------- (Please read the Italian notice on the back before filling out this page) .... \ 8 Η8 CS IXS VI. Application for patent scope 413948 Yomo 【5 0-2 5 0 nm, and is formed by low pressure chemical vapor deposition at 750-850 ° C, 2 1. The method of item 19 in the scope of patent application, wherein the above steps of defining the trench isolation area include: A predetermined photoresist pattern of the trench isolation region is covered on the first nitride layer; the first nitride layer, the first oxide layer, and the semiconductor wafer not covered by the photoresist pattern are etched; and the photoresist pattern is removed. 22. The method according to item 19 of the patent application scope, wherein the above-mentioned trench isolation area is approximately 3 50-650 deep from the surface of the semiconductor wafer to the bottom of the trench isolation area (please read the precautions on the back before filling this page) ) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 3. If the method of the scope of application for patent No. I 9 is applied, the above-mentioned oxide layer lining is formed by a high-temperature thermal oxidation process at a temperature of about 85CM100aC. 24. The method according to item 19 of the application, wherein the forming the second oxide layer is formed by a chemical vapor deposition method at 400-600 ° C. 2 5. The method according to item 19 of the scope of patent application, wherein the above-mentioned etch-back step is to etch back the second oxide layer below the surface of the wafer. The purpose is to create an additional coupling area. • 20 · This paper size is applicable to the Chinese Storehouse Standard (CNS) M specification (2UJX297 mm) 413948 iS CS _ ΠΗ 六 、 Scope of patent application Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 26. In the method, after the step of etching the first oxide layer, the method further includes: forming a sacrificial oxide layer on the semiconductor wafer by a thermal oxidation process; and removing the sacrificial oxide layer. 27. The method according to item 19 of the patent application range, wherein the gate oxide layer is deposited at a thickness of about 7-1 Onm at 900-1 100 ° C. 28_ The method according to item 19 of the patent application range, wherein the first polycrystalline silicon layer is about 50-150 nm thick, and is formed at 500-650 ° C by a low-pressure chemical vapor deposition method. 29_ The method according to item 19 of the patent application range, wherein the above-mentioned meso-crystalline silicon oxide layer is selected from the group consisting of ONO layer, Ta205 layer, Ti02 layer, LiNb03 and (Pb, La) (ZriTi) 03 layer. one. 30. The method according to item 19 of the scope of patent application, wherein the second polycrystalline silicon region is about 100-250 nm thick, and the 'n-type conductive ion is deposited in a manner of simultaneous doping of the n-type conductive ion. It is selected from one of the groups consisting of phosphorus and arsenic, and is in the range of 500-650 by low pressure chemical vapor deposition. (: Formation. 3 1 · If the method of item 19 of the patent application scope, the following steps are included after etching the second polycrystalline silicon layer and steps: • 21- This paper size applies to China National Standard (CNS) A4 specifications d〇x297) 4 ---- --- I -------- 5 ^ --- (Please read the precautions on the back before filling in this page) Order · -line