CN1665310A - Video signal transduce device and video signal transduce method - Google Patents
Video signal transduce device and video signal transduce method Download PDFInfo
- Publication number
- CN1665310A CN1665310A CN 200510051347 CN200510051347A CN1665310A CN 1665310 A CN1665310 A CN 1665310A CN 200510051347 CN200510051347 CN 200510051347 CN 200510051347 A CN200510051347 A CN 200510051347A CN 1665310 A CN1665310 A CN 1665310A
- Authority
- CN
- China
- Prior art keywords
- signal
- mentioned
- video signal
- circuit
- composite
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Processing Of Color Television Signals (AREA)
Abstract
The objective of the invention is to make a 4 fsc frequency clock circuit for a YC separation unnecessary by providing only the clock circuit of a reference frequency (27 MHz) as an analog clock circuit in a composite analog/component digital image signal converter. Generated from a synchronizing signal extracted from an input analog signal is 27 MHz clock used as the reference of the component digital image signal. The input signa is A/D converted by this clock. The subcarrier signal synchronized with the burst signal of the composite image signal is generated from the clock and the A/D converted digital video signal only by a digital circuit. The YC separation of the composite image signal is performed by this subcarrier signal to a component image signal. Further, a burst AGC circuit is added in which the amplitude of the burst signal of the input image signal becomes constant. Consequently, the stable subcarrier signal can be extracted, and the accuracy of the YC separation is improved.
Description
Technical field
The present invention relates to composite analog video signal be transformed to component digital video signal apparatus for changing of video signals, its transform method, with and used circuit.
Background technology
In the radio station, in the past, the analog video signal (complex form) of input was still handled with simulated mode or after being transformed to composite digital video signal (D2 signal).In recent years, the digitlization in the radio station has obtained progress, because digital processing is easy to, so handle after how analog signal being transformed to component digital video signal (D1 signal).Therefore, the expanded demand of composite analogy/component digital video signal conversion, importance has strengthened.Be transformed to the example of conventional device of the digital video signal of component form as the analog video signal with complex form, the device that analog pal video signal is transformed to component digital video (D1) signal is illustrated in Fig. 1.Composite analog video signal also can be called analog composite video signal.And component digital video signal also can be called digital component video signal.
In Fig. 1, the PAL composite analog video signal S101 that is input in the input terminal 101 is input in low pass filter (LPF) 102, synchronizing separator circuit 109, the BCO circuit (burst signal control generator) 111 by branch respectively.LPF 102 has the frequency band that is used for extracting from input signal S101 the 6MHz of vision signal.Synchronizing separator circuit 109 extracts synchronizing signal from input signal S101.BCO circuit 111 produces 4 times of clocks to subcarrier frequency (fsc) (4fsc clock) according to input signal S101.The output signal of LPF 102 is input in the A/D translation circuit 104 by clamp circuit 103.Clamp circuit 103 is fixed on the back edge (reference voltage) of the composite analog video signal of input on the constant voltage.A/D translation circuit 104 is pressed the 4fsc clock that BCO circuit 111 generates, and composite analog video signal is carried out A/D conversion (analog/digital conversion).
Synchronous pulse-generating circuit 110 is according to the output signal of synchronizing separator circuit 109 and BCO circuit 111, generates the lock-out pulse of the 4fsc system that is used to control each module.H-PLL circuit 113 is exported reference frequency clock benchmark, single fixed frequency as component digital video signal, for example the 27MHz clock according to the output signal of BCO circuit 111 and synchronous pulse-generating circuit 110.Synchronous pulse-generating circuit 112 is according to the output signal of synchronous pulse-generating circuit 110 and H-PLL circuit 113, generates the lock-out pulse of each circuit module that is used to control 27MHz clock system.
Y/c separation circuit 105 is difference separating luminance component Y, color difference components U, V (C) from the complex digital signal of A/D translation circuit 104 outputs.D2/D1 translation circuit 106 is used to make data and the reference clock of D1--the conversion process (component digital video signal conversion and signal rate conversion) that 27MHz coincide from the 4fsc clock system of y/c separation circuit 105 outputs.
The output signal of 107 pairs of D2/D1 translation circuits 106 of treatment circuit is carried out the insertion of each sign, the gain adjustment of video.P/S translation circuit (parallel/the serial converted circuit) 108 will be a serial signal from the treatment circuit 107 parallel digital signal conversions of sending here, and (PALD1 component video signal S114) outputs to lead-out terminal 114 as the component serial digital video signal.
As mentioned above, the composite analogy of prior art/component digital video signal converting means need be used for the 4fsc clock that YC separates and these 2 clocks systems of 27MHz clock that are used for the component digital video signal conversion.The generation circuit of this 4fsc clock and 27MHz clock is made of analog circuit, so be difficult to reduce circuit scale.
(Japan) spy opens the 2000-102032 communique and has put down in writing the device example that the analog video signal of TSC-system is transformed to component digital video (D1) signal.What carry out the Y/C separation is YC separator 102, and what carry out component digital video signal conversion (signal rate conversion) is speed conversion device 104.In addition, (Japan) spy opens clear 57-053192 and discloses spendable subcarrier signal regenerative circuit when forming the 4fsc clock in the Phase Alternation Line system.This subcarrier signal regenerative circuit also is made of analog circuit.(Japan) spy opens the 2000-92507 communique and also discloses similar techniques.
As mentioned above, the composite analogy of prior art shown in Figure 1/component digital video signal converting means need be used for the 4fsc clock that YC separates and these 2 clocks systems of reference frequency clock (27MHz clock) that are used for the component digital video signal conversion.The generation circuit of clock is made of analog circuit, so be difficult to reduce circuit scale.Therefore, for small-sized product is provided, the composite analogy/component digital video signal converting means that need reduce the analog circuit scale, replace with digital circuit.But in above-mentioned document, the unexposed detailed structure that is used for the parts of figure signal speed is not described the technology of clock circuit, generation (regeneration) subcarrier yet.
The objective of the invention is to, the simulated clock simulation clock circuit only is made of the clock circuit of generation as the reference frequency clock of the benchmark of component digital video, reduces the analog circuit member.Therefore, reduced circuit scale, realized miniaturization, cheap than existing apparatus.
Summary of the invention
According to an aspect of the present invention, a kind of apparatus for changing of video signals is provided, composite analog video signal is transformed to component digital video signal, it is characterized in that, comprise: the reference frequency clock generates parts, from the composite analog video signal of input, extract synchronizing signal, generate reference frequency clock as the frequency of the benchmark of component digital video signal according to this synchronizing signal; The analog/digital conversion parts according to the said reference frequency clock, carry out analog/digital conversion to above-mentioned input composite analog video signal, export as composite digital video signal; And the subcarrier production part, according to said reference frequency clock and above-mentioned composite digital video signal, regenerate, the synchronous subcarrier signal of burst signal of output and above-mentioned input composite analog video signal.
According to a further aspect in the invention, a kind of video signal conversion method is provided, composite analog video signal is transformed to component digital video signal, wherein, from the composite analog video signal of input, extract synchronizing signal, generate reference frequency clock as the frequency of the benchmark of component digital video signal according to this synchronizing signal; According to the said reference frequency clock, above-mentioned input composite analog video signal is carried out analog/digital conversion, become composite digital video signal; According to said reference frequency clock and above-mentioned composite digital video signal, regenerate, the synchronous subcarrier signal of burst signal of output and above-mentioned input composite analog video signal; According to above-mentioned subcarrier signal, difference separating luminance component and color difference components are exported as component digital video signal from above-mentioned composite digital video signal.
Description of drawings
Fig. 1 illustrates an example of conventional device--analog pal video signal is transformed to the example of the device of component digital video (D1) signal.
Fig. 2 is the block diagram of the apparatus for changing of video signals of embodiments of the invention.
Fig. 3 is the block diagram of the embodiment of burst signal agc circuit.
Fig. 4 is the block diagram that subcarrier produces embodiment of circuit.
Fig. 5 is the block diagram of the embodiment of y/c separation circuit.
Fig. 6 is the block diagram of another embodiment of y/c separation circuit.
Embodiment
Summary of the present invention at first is described.Composite analogy of the present invention/component digital video signal converting means (hereinafter to be referred as apparatus for changing of video signals) is the device that is used for composite analog video signal is transformed to component digital video signal.Composite analog video signal is with the superposeed analog signal of luminance signal and colour signal of subcarrier (colour subcarrier).Component digital video signal is the digital signal that luminance signal (luminance component) is separated with colour signal (color difference components).
This apparatus for changing of video signals is according to the synchronizing signal that extracts the composite analog signal from input, generates the clock as the frequency of the benchmark of component digital video signal.This frequency as benchmark (reference frequency) is single fixed frequency, and the clock of this frequency is called reference frequency clock or reference clock.Apparatus for changing of video signals generates and makes the various lock-out pulses of controlling synchronously by each circuit and the vision signal of this clock work (reference frequency is a lock-out pulse) also according to this reference frequency clock.Supporting that common transmission rate is that reference frequency adopts 27MHz under the situation of serial component digital video signal of 270Mbps.In the case, reference frequency clock (reference clock) is called the 27MHz clock.
Apparatus for changing of video signals also carries out A/D conversion (analog/digital conversion) by the said reference frequency clock to the input composite analog signal, becomes composite digital video signal.In the prior art, carry out this A/D conversion by 4 times of clocks to the frequency of subcarrier frequency.
The composite digital video signal that this apparatus for changing of video signals then goes out according to said reference frequency clock (comprising lock-out pulse) and above-mentioned A/D conversion produces and imports the synchronous subcarrier signal of burst signal of composite analog video signal with digital circuit.This subcarrier signal is also synchronous with the burst signal of composite digital video signal.Burst signal is the signal as the benchmark of colour signal processing.That is, colour signal is being separated timing, need make frequency, the Phase synchronization of subcarrier, this burst signal is as this fixed phase.This apparatus for changing of video signals and then separate (luminance signal (Y) and colour signal (C) separate) with the YC that above-mentioned subcarrier signal carries out composite digital video signal is transformed to component digital video signal.
Like this,, can only carry out composite analog video signal is transformed to the processing of component digital video signal, can only generate subcarrier with digital circuit by single reference frequency clock (27MHz clock) according to the present invention.Therefore, the circuit scale of composite analogy/component digital video signal converting means integral body reduces, and can make this apparatus for changing of video signals more small-sized than in the past, cheap.The present invention separates in order to carry out more stable YC, can add burst signal AGC (automatic gain control) circuit of the amplitude constant that makes input composite analogy burst signal.Thus, this apparatus for changing of video signals can extract stable subcarrier signal, so the precision that YC separates improves.
Fig. 2 is the frame assumption diagram of an execution mode of composite analogy of the present invention/component digital video signal converting means.This routine apparatus for changing of video signals is the PAL/D1 converting means that the Phase Alternation Line system composite analog video signal is transformed to component digital video signal (D1 signal).The clock that this apparatus for changing of video signals uses is that clock constitutes by 27MHz only.Composite analog video signal also can be called analog composite video signal.And component digital video signal also can be called digital component video signal.In Fig. 2, apparatus for changing of video signals comprises input terminal 1, clamp circuit 2, burst signal agc circuit the 3, the 1st low pass filter (LPF) 4, A/D translation circuit 5 and the 2nd low pass filter (LPF) 6.Apparatus for changing of video signals comprises that also synchronizing separator circuit 7, synchronous pulse-generating circuit 8, H-PLL circuit 9, subcarrier produce circuit 10, y/c separation circuit 11, treatment circuit 12, P/S translation circuit 13 and lead-out terminal 14.
The work of this routine apparatus for changing of video signals (PAL/D1 converting means) then, is described.Being input to PAL composite analog video signal S1 in the input terminal 1 is branched and is input to clamp circuit 2 and synchronizing separator circuit 7.Clamp circuit 2 will be fixed on the constant voltage from the back edge (reference voltage) of the composite analog video signal S1 of input terminal 1 input.Synchronizing separator circuit 7 extracts synchronizing signal (horizontal-drive signal and vertical synchronizing signal) from the composite analog video signal S1 of input terminal 1 input.H-PLL circuit 9 is the oscillating circuits that comprise phase-locked loop (PLL), and the synchronizing signal (level (H) synchronizing signal) that extracts according to synchronizing separator circuit 7 generates the clock of 27MHz.That is, H-PLL circuit 9 carries out the phase bit comparison of PLL, make between 1 departure date in cycle of vibration output be 1728 weeks.
Synchronous pulse-generating circuit 8 is according to each output signal of synchronizing separator circuit 7 and H-PLL circuit 9, generates a plurality of lock-out pulses of the 27MHz clock system that is used to control each module.These lock-out pulses are various timing signals of the time relationship between various signals in expression and the used corresponding component digital video signal of standard.Burst signal agc circuit (automatic gain control circuit) 3 be according to the output signal of synchronous pulse-generating circuit 8, and the burst signal of the output composite analog video signal of clamp circuit 2 is partly become constant amplitude.By keeping the amplitude constant of burst signal, the burst signal part after the A/D conversion can not blured, and can access stable burst signal phase place.The LPF 4 of the aliasing of the output signal of burst signal agc circuit 3 when preventing the A/D conversion is input to A/D translation circuit 5.The composite analog video signal of 5 pairs of inputs of A/D translation circuit carries out A/D conversion (analog/digital conversion), becomes composite digital video signal.
It is the circuit that produce subcarrier according to the 27MHz clock that subcarrier produces circuit 10.Subcarrier produces circuit 10 each output signal according to synchronous pulse-generating circuit 8 and H-PLL circuit 9, by the outputting video signal of A/D translation circuit 5, digitally generates color difference components--the subcarrier on U component, the V component that is locked in the vision signal.Subcarrier produces circuit 10 and is made of digital circuit, and is integrated easily, thus compared with the past, can realize small-sized PAL/D1 converting means.The output signal of the A/D translation circuit 5 also LPF 6 of the frequency band by extracting vision signal is input to y/c separation circuit 11.
Y/c separation circuit 11 produces the output signal of circuit 10 according to subcarrier, is component with the output signal type of A/D translation circuit 5 from complex transformation.At this moment, y/c separation circuit 11 extracts luminance signal (luminance component) Y, colour signal C (color difference components U, V) by the single clock that has only the 27MHz clock.Treatment circuit 12 is according to each output signal of synchronous pulse-generating circuit 8 and H-PLL circuit 9, and the output signal of y/c separation circuit 11 is carried out the gain adjustment of Y, U, V component, insertion of video timing base code (SAV, EAV) that the D1 form is used etc.SAV is the reference code (control bit) of expression 1 row beginning, and EAV is the reference code (control bit) that expression 1 row finishes.P/S translation circuit (parallel/the serial converted circuit) 13 will be transformed to serial data from the parallel data (PAL component signal) of treatment circuit 12 outputs, and S14 outputs to lead-out terminal 14 as PAL D1 component video signal.
Like this, this routine apparatus for changing of video signals (PAL/D1 converting means) is transformed to PAL component (D1) serial signal (S14) and output with the PAL composite analog video signal (S1) of input.Circuit of the present invention can only come work by the 27MHz clock, and only generates subcarrier with digital circuit.Therefore, the circuit scale of apparatus for changing of video signals integral body of the present invention reduces, and can provide than more small-sized in the past apparatus for changing of video signals (PAL/D1 converting means).
Fig. 3 is the frame assumption diagram of detailed structure example of the burst signal agc circuit 3 of Fig. 2.In Fig. 3, this routine burst signal agc circuit 3 has gain (GAIN) and adjusts circuit 33, band pass filter (BPF) 34, rectification circuit 35, low pass filter (LPF) 36, sampling hold circuit 37 and comparison circuit 38.In addition, burst signal agc circuit 3 also has input terminal 30,31,32 and lead-out terminal 39.
Supply with 2 kinds of lock-out pulses to the input terminal 30,31 of burst signal agc circuit 3 from the 27MHz clock system of synchronous pulse-generating circuit 8.Be input to lock-out pulse in the input terminal 30 and be the pulse during the burst signal that is used for only extracting composite analog video signal, use by gain adjustment circuit 33.Be input to lock-out pulse in the input terminal 31 and be the pulse (sampling pulse) of (sampling timing) during certain 1 in being used for only extracting during the above-mentioned burst signal, use by sampling hold circuit 37.The input signal of input terminal 32 is to carry out the composite analog video signal that clamp is handled by clamp circuit 2, is input to BPF 34 by gain adjustment circuit 33.BPF 34 is used for extracting from the output signal of gain adjustment circuit 33 bandpass filtering of chrominance component (subcarrier frequency component).The frequency component that 35 couples of BPF 34 of rectification circuit extract is carried out rectification, is undertaken smoothly being input in the sampling hold circuit 37 by LPF 36.Sampling hold circuit 37 according to timing from the synchronous sampling pulse of certain point of the burst signal of synchronous pulse-generating circuit 8, keep the value (magnitude of voltage) of input signal.Comparison circuit 38 detects the output voltage (sustaining voltage) of sampling hold circuit 37 and the difference of predefined reference voltage, and testing result is returned to gain adjustment circuit 33.Gain adjustment circuit 33 according to from the synchronous pulse of the burst signal of synchronous pulse-generating circuit 8, adjust the gain of the burst signal amplitude of input signal, make the difference of comparison circuit 38 be " 0 ", thus, constitute feedback loop.Gain adjustment circuit 33 makes the amplitude constant of the burst signal part of input signal, from lead-out terminal 39 outputs.
Fig. 4 is the frame assumption diagram that the subcarrier of Fig. 1 produces the detailed structure example of circuit 10.In Fig. 4, this routine subcarrier produces circuit 10 and has the 1st, the 2nd, and the 3rd corrected value generative circuit 51,52,53, corrected value adder circuit 54, fixed value output circuit 55, phase value adder circuit 56, phase value latch cicuit 57, sinusoidal wave (SIN ripple) ROM 58 and cosine wave (COS ripple) ROM 59.Subcarrier produces circuit 10 and also has band pass filter (BPF) 61, mlultiplying circuit 63, low pass filter (LPF) the 64, the 1st and the 2nd phase difference latch cicuit 65,66, phase difference adder circuit 68, correction value circuit 69, counter 71 and circuit for reversing 72.In addition, subcarrier generation circuit 10 also has video signal input terminal (Video In) 60, subcarrier (U component) lead-out terminal 62 and the 1st and the 2nd synchronous signal input end 67,70.
Here, illustrate that subcarrier produces circuit 10 generates subcarrier according to the 27MHz clock principle.In the composite video signal of Phase Alternation Line system, the line number of 1 frame is 625, and per 1 second average frame number is 25 frames (interlacing scans in 2: 1).In this vision signal, the frequency f sc of subcarrier and line frequency fh have the relation of fsc=(1135/4+1/625) * fh.Fh=625 * 25[Hz], so fsc=(1135/4+1/625) * 625 * 25[Hz].The frequency of 1 frame is 25Hz (frame rate=25fps), all number of value representation 25 frames of above-mentioned fsc.Therefore, all numbers of 4 image durations of subcarrier are 709379 weeks (=(1135/4+1/625) * 625 * 25 * 4/25).On the other hand, 27MHz clock average per 4 image durations are 4320000 weeks (=27000000 * 4/25).Cut apart the phase place (angle: 360 °) in 1 week of subcarrier equably with 2 16 powers, represent each phase position with value corresponding (phase value).That is, make 0 °, successively numerical value is increased progressively " 1 ", make 360 ° corresponding to numerical value " 65536 " along with the increase of phase place (phase position that is partitioned into) corresponding to numerical value " 0 ".Therefore, on 709379 weeks suitable with 4 frames, phase place is 709379 * 360 °, so can be expressed as " 46489862144 " (=65536 * 709379).Here, the phase place of constructing subcarrier according to 27MHz is so need the phase place (phase value) of subcarrier is shown as " 46489862144 " on 4320000 weeks suitable with 4 frames of 27MHz clock.Therefore, (360 °: 1 clock) phase changing capacity of average subcarrier is made as 46,489862144/4320000=10761.54 with per 1 week of 27MHz clock ...Here, be " 10762 " with this numerical value integer approximation.Carrying out under the above-mentioned approximate situation, 4320000 weeks of 27MHz clock are " 46491840000 " of the phase place of subcarrier, the error of "+1977856 " occurs.As the 1st correction of this approximate error, by per 2 weeks adding " 1 ", the error on 4320000 weeks is " 182144 ".As the 2nd correction, per 24 weeks add "+1 " 1 time, and then the error on 4320000 weeks is " 2144 ".As the 3rd correction, per 2015 weeks add "+1 " 1 time, and then error is " 1 ".Proofread and correct as last (the 4th), per 4320000 weeks add "+1 " 1 time.Like this, can calculate the phase place of the frequency f sc of high-precision subcarrier according to the clock of 27MHz.Above-mentioned part is equivalent to the work of each circuit of the label 51～57 of Fig. 4.
Each corrected value generative circuit 51,52,53 has counter, decoder and fixed value output circuit respectively.Each counter is according to 27MHz clock (CLK), and clock of every input is just with count increments " 1 ".Each decoder monitors the count value of corresponding counter, when reaching set point, with counter reset.The value of each fixed value output circuit output regulation when the value of the decoder of correspondence or counter becomes set point.Corrected value generative circuit 53 has 23 counter, decoder, is responsible for above-mentioned the 1st time and the 4th correction.That is per 2 clocks output of 53 pairs of 27MHz clocks of corrected value generative circuit 1 time, (corresponding to " 0 "/" 1 " of the LSB (minimum bit) of counter) " 1 " is as corrected value.Corrected value generative circuit 53 is also exported 1 time "+1 " as corrected value to per 4320000 clocks.Corrected value generative circuit 52 has 5 counter, decoder, is responsible for above-mentioned the 2nd time and proofreaies and correct.That is, per 24 clocks outputs 1 time "+1 " of 52 pairs of 27MHz clocks of corrected value generative circuit are as corrected value.In addition, the counter reset that corrected value generative circuit 52 produces according to 4320000 clock counts in the corrected value generative circuit 53 is with the counter reset of this circuit.Corrected value generative circuit 51 has 11 counter, decoder, is responsible for above-mentioned the 3rd time and proofreaies and correct.That is, per 2015 clocks outputs 1 time "+1 " of 51 pairs of 27MHz clocks of corrected value generative circuit are as corrected value.In addition, the counter reset that corrected value generative circuit 51 produces according to 4320000 clock counts in the corrected value generative circuit 53 is with the counter reset of this circuit.
Corrected value adder circuit 54 self-correctings in the future output to phase value adder circuit 56 on the occasion of the corrected value of each approximate error corresponding with the 27MHz clock of generative circuit 51,52,53 with from corrected value addition, the total (16 additions) corresponding with phase difference of correction value circuit 69.Fixed value output circuit 55 is exported the approximation " 10,762 " of the phase value of the subcarrier corresponding with 1 clock (1 week: 360 °) of 27MHz clock all the time.Corrected value that phase value adder circuit 56 will go out from the approximation " 10,762 " of fixed value output circuit 55, from the total of corrected value adder circuit 54 and phase value latch cicuit 57 last time clock retention value addition, total.Per 1 clock of 57 pairs of 27MHz clocks of phase value latch cicuit is taken into the aggregate result of phase value adder circuit 56 phase value as the output subcarrier, keep, export.
SIN ripple ROM (Read Only Memory, read-only memory) 58 and COS ripple ROM 59 in store respectively and the level value (data) of each phase value corresponding (sine wave) and the level value (data) of COS ripple (cosine wave).SIN ripple ROM 58 read successively with from the corresponding output phase value of each 27MHz clock of phase value latch cicuit 57, as the digital SIN ripple (subcarrier: SC) output to lead-out terminal 62 that is locked on the U component.COS ripple ROM 59 reads and the corresponding level value of output phase value from each 27MHz clock of phase value latch cicuit 57 successively, outputs to mlultiplying circuit 63 and circuit for reversing 72 as digital COS ripple.In the present embodiment, be respectively equipped with the COS ripple ROM59 that is used to export the SIN ripple ROM 58 of SIN wave datum and is used to export the COS wave datum, if but proofread and correct the phase value of reading, wherein some getting final product then arranged.For example, only be provided with SIN ripple ROM 58, when reading the COS wave datum, make leading 90 ° of the output phase value of phase value latch cicuit 57.
On the other hand, the composite analog signal (VIDEO IN) that is input to the A/D translation circuit 5 A/D conversion in the input terminal 60 extracts the subcarrier frequency component by BPF 61, is input in the mlultiplying circuit 63.Mlultiplying circuit 63 is phase comparators, for the output COS ripple of COS ripple ROM 59 relatively with passed through the phase place of burst signal part of the incoming video signal of BPF 61, they is multiplied each other.LPF 64 removes high-order component from the multiplication result of mlultiplying circuit 63, extract phase difference.Each phase difference latch cicuit 65,66 and phase difference adder circuit 68 are coordinated, according to the H pulse that is input in the input terminal 67, and to phase difference from LPF 64, interior average phase-difference during the detection 2H (2 row).So-called H pulse (H PULSE), be synchronous pulse-generating circuit 8 that generate, with the suitable lock-out pulse of a part of burst signal.Correction value circuit 69 is by feeding back to corrected value adder circuit 54 with the corrected value corresponding with phase difference adder circuit 68 detected phase differences, and makes the Phase synchronization of the subcarrier of the phase place of SIN ripple and COS ripple and incoming video signal.
The V component of subcarrier reverses (positive and negative counter-rotating) when every 1H (OK), generates the COS ripple so need reverse when every 1H.Therefore, with 1 counter--counter 71, according to the 1H clock that is input in the input terminal 70, make count value alternately be reversed to " 0 " or " 1 ", should count output and supply to circuit for reversing 72.For example, can when count value is " 0 ", the symbol of COS ripple be remained untouched in (note work+), and when count value is " 1 ", make the sign-inverted (note work-) of COS ripple.Wherein, which is "+", which is "-" in order to specify, and counter 71 decides " 0 "/" 1 " of count value with reference to the output of LPF 64.So-called 1H clock (1H CKL), be synchronous pulse-generating circuit 8 generate being the lock-out pulse in cycle between 1 departure date.Circuit for reversing 72 is according to the output of counter 71, makes from the counter-rotating (positive and negative counter-rotating) when every 1H of the COS ripple of COS ripple ROM, as the digital COS ripple (subcarrier: SC) output to lead-out terminal 73 that is locked on the V component.
Fig. 5 is the frame assumption diagram of detailed structure example of the y/c separation circuit 11 of Fig. 1.In Fig. 5, this routine y/c separation circuit 11 has signal delay portion the 80, the 1st and the 2nd add circuit the 84,85, the 1st and the 2nd mlultiplying circuit 86,88,1H delay circuit the 90, the 1st and the 2nd low pass filter (LPF) 91,92 and the 1st and the 2nd transmission distortion and removes circuit 94,95.Y/c separation circuit 11 also has the 2nd and the 3rd input terminal and the 1st, the 2nd and the 3rd lead-out terminal 96,97,98.Signal delay portion 80 comprises 2 the 2H delay circuits (2H DELAY) 82,83 that are connected in series from the 1st input terminal 81.The output point (input point of 2H delay circuit 83) of input terminal 81 (input point of 2H delay circuit 82), 2H delay circuit 82, the output point of 2H delay circuit 83 are connected respectively on add circuit 84 and the add circuit 85.The digital signal that 5 pairs of composite analog video signals of A/D translation circuit carry out A/D conversion gained is input to input terminal 81 by LPF 6.This signal is totally applied the time delay (2H delay) of 2 1H (1 row: be the cycle of horizontal-drive signal in time) successively by 2 2H delay circuits 82,83.Add circuit 84 and add circuit 85 extract U, V component (color difference signal) and Y component (luminance signal) respectively by weighting and addition to stipulating from the signal of input terminal 81,2H delay circuit 82,2H delay circuit 83.Promptly, add circuit 84 by will less than postpone from the signal times of input terminal 81 with " 1/4 ", with postponed 2H from the signal times of 2H delay circuit 82 with " 1/2 ", with postponed 4H from the signal times of 2H delay circuit 83 with " 1/4 ", with their additions, total, extract U, V component.Add circuit 85 by will less than postpone from the signal times of input terminal 81 with " 1/4 ", with postponed 2H from the signal times of 2H delay circuit 82 with " 1/2 ", with postponed 4H from the signal times of 2H delay circuit 83 with " 1/4 ", with their additions, total, extract the Y component.
Here, the principle of extracting Y component and U, V component is described from digital composite video signal.
The suppose object composite signal is M, and subcarrier frequency is fsc, and the time is t, and then the relation table between Y, U, V is shown
《1》M＝Y+U?sin?2πfsc?t±V?cos?2π?fsc?t。
The U of PAL, V component subcarrier have following relation.
(a) U, V component 90 ° of phase deviations line by line.
(b) V component phasing back line by line.
Therefore, suppose that Y, U, the V component on the row h is respectively Y (h), U (h), V (h), the pass of then going between h-2, row h, row h+2 is
《2》Y(h-2)＝Y(h)＝Y(h+2)，
《3》U(h-2)＝-U(h)＝U(h+2)，
《4》V(h-2)＝-V(h)＝V(h+2)。
The composite video signal M (h) of the A/D conversion on therefore, can enough h capable shows as
《5》Y(h)＝1/4*M(h-2)+1/2*M(h)+1/4*M(h+2)、
《6》U(h)+V(h)＝1/4*M(h-2)-1/2*M(h)+1/4*M(h+2)，
Can extract Y component and U, V component.These formulas be equivalent to the add circuit 84 of Fig. 5 and add circuit 85 (if with the output of 2H delay circuit 82 as benchmark (not postponing), then the signal of input terminal 81 be-2H postpones, 2H delay circuit 83 is output as the 2H delay.)。
Here, in (a), said 90 ° of phase deviations, but strictly speaking, be offset 90 °+0.576 ° just now.This be because, the PAL standard is (fsc=1135/4+1/625) * fh, thus the sampled point offset slightly, the phase place delayed slightly.In order to improve the separation accuracy of Y component and U, V component, need to proofread and correct this phase deviation, the example of having added this consideration in the circuit structure of signal delay portion 80 is as follows.In signal delay portion 80, will in the PAL of input terminal 81 vision signal, mix several one-tenth than this signal delay the signal of component gained of 1 clock be input in the add circuit 84,85 as M (h-2).Signal delay portion 80 also will in 2H delay circuit 82 has postponed the signal of 2H, mix several one-tenth than this signal delay the component gained signal of 1 clock be input in the add circuit 84,85 as M (h).Like this, the U that signal delay portion 80 can the corrected sub carrier wave, the phase deviation of V component, can precision more the highland separate Y component and U, V component.The circuit structure example of signal delay portion 80 will be described hereinafter.
Being locked in the COS ripple that produces on the V component that circuit 10 is input to the subcarrier the input terminal 87 from subcarrier is imported in the mlultiplying circuit 86.Equally, being locked in the SIN ripple that produces on the U component that circuit 10 is input to the subcarrier the input terminal 89 from subcarrier is imported in the mlultiplying circuit 88.The COS ripple on the V component that is locked in subcarrier is multiply by in the output of the add circuit 84 of mlultiplying circuit 86 by will extracting out U, V component, can extract the V component.Equally, the SIN ripple on the U component that is locked in subcarrier is multiply by in the output of the add circuit 84 of mlultiplying circuit 88 by will having extracted U, V component, can extract the U component.The frequency component that the output signal of mlultiplying circuit 86 (V component) is removed 2 residual * fsc by LPF 91 is removed circuit 94 by transmission distortion and is removed distortion under the situation of phase delay, outputs to lead-out terminal 96.The frequency component that the output signal of mlultiplying circuit 88 (U component) is removed 2 residual * fsc by LPF 92 is removed circuit 95 by transmission distortion and is removed distortion under the situation of phase delay, outputs to lead-out terminal 97.Transmission distortion removes that circuit 94 and transmission distortion remove that circuit 95 has 2 1H delay circuits being connected in series respectively and with the add circuit of the input and the output addition of each 1H delay circuit.U component, V component are removed the result that circuit 94,95 handles by transmission distortion and are postponed 1H, postpone so 1H delay circuit 90 is used to aim at the 1H of the output phase of Y component.Like this, can from the input (digital composite video signal) of input terminal 81, extract V, U, Y component, become component digital video signal, respectively from lead-out terminal 96,97,98 outputs.In the explanation of above-mentioned execution mode, the composite analog video signal of input has adopted the signal of Phase Alternation Line system.But the present invention is not limited to this, also can be applied to the signal of other standards such as signal of TSC-system.
The circuit of Fig. 6 has further inserted single clock delay circuit (1CLOCK DELAY) 801 and add circuit 802 to the circuit of Fig. 5 between input terminal 81 and 2H delay circuit 82.Moreover, between 2H delay circuit 82 and 2H delay circuit 83, inserted single clock delay circuit 803 and add circuit 804.The PAL vision signal that add circuit 802 mixes input terminals 81 with by single clock delay circuit 801 than this signal delay component several of 1 clock become to generate M (h-2).Add circuit 804 mix by 2H delay circuit 82 than the output delay of single clock delay circuit 801 2H signal with by single clock delay circuit 803 than this signal delay component several of 1 clock become to generate M (h).In addition, will by 2H delay circuit 83 than the output delay of single clock delay circuit 803 signal of 2H as M (h+2).
Claims (11)
1. an apparatus for changing of video signals is transformed to component digital video signal with composite analog video signal, it is characterized in that, comprising:
The reference frequency clock generates parts, extracts synchronizing signal from the composite analog video signal of input, generates reference frequency clock as the frequency of the benchmark of component digital video signal according to this synchronizing signal;
The analog/digital conversion parts according to the said reference frequency clock, carry out analog/digital conversion to above-mentioned input composite analog video signal, export as composite digital video signal; And
The subcarrier production part according to said reference frequency clock and above-mentioned composite digital video signal, is regenerated, the synchronous subcarrier signal of burst signal of output and above-mentioned input composite analog video signal.
2. apparatus for changing of video signals as claimed in claim 1, wherein,
In the prime of above-mentioned analog/digital conversion parts, be provided with the burst signal automatic gain control assembly of the amplitude constant that makes the burst signal in the above-mentioned input composite analog video signal.
3. apparatus for changing of video signals as claimed in claim 1, wherein,
Also comprise: the brightness/colour signal split circuit, according to above-mentioned subcarrier signal, difference separating luminance component and color difference components are exported as component digital video signal from above-mentioned composite digital video signal.
4. apparatus for changing of video signals as claimed in claim 1, wherein,
Above-mentioned subcarrier production part has:
The phase value calculating unit is counted the clock of said reference frequency, calculates the phase value of subcarrier signal;
Memory unit is stored the level data of each the prescribed phases value corresponding with the waveform of subcarrier signal; And
Signal generates parts, according to proofreading and correct the phase value that above-mentioned phase value calculating unit is calculated with the comparative result of the phase value of the burst signal of above-mentioned composite digital video signal, from above-mentioned memory unit, read and the corresponding level data of above-mentioned corrected phase value, generate the synchronous subcarrier signal of burst signal with above-mentioned composite analog video signal.
5. apparatus for changing of video signals as claimed in claim 1, wherein,
Above-mentioned subcarrier production part has:
The fixed value output block, the fixed value of output and the variable quantity of the cycle phase value corresponding, the approximate representation subcarrier of the clock of said reference frequency;
The approximate error corrected value generates parts, to each defined amount of above-mentioned clock, generates the approximate error corrected value of the approximate error that is used to proofread and correct the said fixing value;
Phase value phase made component to the phase value accumulative total addition of above-mentioned each clock with said fixing value, above-mentioned approximate error corrected value and maintenance, is exported addition result as the phase value of subcarrier;
The sinusoidal wave data output block, preserve sinusoidal wave level data, read successively with from the above-mentioned phase value corresponding level data of phase value of each clock of made component mutually, output is locked in the sine wave signal on the U component in the color difference components of above-mentioned subcarrier;
Cosine wave data output section part is preserved the level data of cosine wave, read successively with from the above-mentioned phase value corresponding level data of phase value of each clock of made component mutually, export as cosine wave signal;
The phase difference correction value generates parts, the phase place of the burst signal of more above-mentioned composite digital video signal and from the phase place of the cosine wave signal of above-mentioned cosine wave data output section part output, generate with these signals between the corresponding above-mentioned phase difference correction value of phase difference, output to above-mentioned phase value phase made component; And
The phasing back parts, according to the horizontal-drive signal that from above-mentioned composite analog video signal, obtains, reverse line by line from the phase place of the cosine wave signal of above-mentioned cosine wave data output section part output, export as the cosine wave signal on the V component in the color difference components that is locked in above-mentioned subcarrier.
6. apparatus for changing of video signals as claimed in claim 5, wherein,
Above-mentioned cosine wave data output section part is not preserved the level data of above-mentioned cosine wave, but the level data of the above-mentioned sine wave of the above-mentioned sinusoidal wave data output block of reference, make leading 90 degree of phase value, read the level data of corresponding level data successively as cosine wave from each clock of above-mentioned phase value phase made component.
7. apparatus for changing of video signals as claimed in claim 5, wherein,
The clock of said reference frequency is the 27MHz clock;
All numbers of 4 frames of the subcarrier of above-mentioned composite analog video signal--709379 weeks are corresponding to 4320000 weeks of above-mentioned 27MHz clock;
Said fixing value output block output 10,762, the said fixing value during as the phase place in 1 week of coming the vice carrier wave with 16 bit data;
Above-mentioned approximate error corrected value generates per 2 the clocks output-1 of parts to above-mentioned 27MHz clock, to per 24 clocks output 1, to per 2015 clocks output 1, to per 4320000 clocks output 1, as above-mentioned approximate error corrected value.
8. apparatus for changing of video signals as claimed in claim 3, wherein,
The brightness/colour signal split circuit has:
Signal lag part, be connected in series respectively input signal is applied the delays of 2 row and the 1st 2H delay circuit and the 2nd 2H delay circuit of output constitutes, make above-mentioned composite digital video signal lead to above-mentioned the 1st 2H delay circuit and the 2nd 2H delay circuit successively, export respectively as the 1st composite video signal that does not postpone, the 2nd composite video signal of delays that has applied 2 row and the 3rd composite video signal that has applied the delays of 4 row;
The 1st adding unit, to above-mentioned the 1st composite video signal, the 2nd composite video signal, and the 3rd composite video signal carry out weighting and the addition of 1:-2:1 respectively, extract U component and V component color difference components altogether;
The 2nd adding unit, to above-mentioned the 1st composite video signal, the 2nd composite video signal, and the 3rd composite video signal carry out weighting and the addition of 1:2:1 respectively, extract Y component--luminance component;
The 1st multiplying unit multiply by digitized sine wave signal from the U component that is locked in subcarrier of outside input with the output of above-mentioned the 1st adding unit, extracts the U component; And
The 2nd multiplying unit multiply by digital cosine wave signal from the V component that is locked in subcarrier of outside input with the output of above-mentioned the 1st adding unit, extracts the V component.
9. apparatus for changing of video signals as claimed in claim 8, wherein,
Above-mentioned signal lag part has:
The 1st single clock delay circuit is arranged on the prime of above-mentioned the 1st 2H delay circuit, and above-mentioned composite digital video signal is applied the delay of 1 clock and outputs to above-mentioned the 1st 2H delay circuit;
The 2nd single clock delay circuit is arranged between above-mentioned the 1st 2H delay circuit and the 2nd 2H delay circuit, and the output signal of above-mentioned the 1st 2H delay circuit is applied the delay of 1 clock and outputs to above-mentioned the 2nd 2H delay circuit;
The 1st add circuit, the signal that will branch out from the input of above-mentioned the 1st single clock delay circuit adds the signal that branches out of regulation ratio from the output of the 1st single clock delay circuit, addition result is exported as above-mentioned the 1st composite video signal; And
The 2nd add circuit, the signal that will branch out from the input of above-mentioned the 2nd single clock delay circuit adds the signal that branches out of regulation ratio from the output of the 2nd single clock delay circuit, addition result is exported as above-mentioned the 2nd composite video signal.
10. a video signal conversion method is transformed to component digital video signal with composite analog video signal, wherein,
From the composite analog video signal of input, extract synchronizing signal, generate reference frequency clock as the frequency of the benchmark of component digital video signal according to this synchronizing signal;
According to the said reference frequency clock, above-mentioned input composite analog video signal is carried out analog/digital conversion, become composite digital video signal;
According to said reference frequency clock and above-mentioned composite digital video signal, regenerate, the synchronous subcarrier signal of burst signal of output and above-mentioned input composite analog video signal;
According to above-mentioned subcarrier signal, difference separating luminance component and color difference components are exported as component digital video signal from above-mentioned composite digital video signal.
11. video signal conversion method as claimed in claim 10, wherein,
After making the amplitude constant of the burst signal in the above-mentioned input composite analog video signal, this input composite analog video signal is carried out analog/digital conversion.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004060844A JP2005252688A (en) | 2004-03-04 | 2004-03-04 | Composite analog/component digital image signal converter and conversion method, and subcarrier generating circuit used for it, and luminance/color signal generating circuit |
| JP060844/2004 | 2004-03-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1665310A true CN1665310A (en) | 2005-09-07 |
| CN100576927C CN100576927C (en) | 2009-12-30 |
Family
ID=35032756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200510051347A Active CN100576927C (en) | 2004-03-04 | 2005-03-04 | Apparatus for changing of video signals and video signal conversion method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2005252688A (en) |
| CN (1) | CN100576927C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102223496A (en) * | 2010-04-13 | 2011-10-19 | 新港传播媒介公司 | Dual burst locked oscillator architecture for an analog television receiver |
| CN104410848A (en) * | 2014-03-31 | 2015-03-11 | 奈斯特株式会社 | Method and apparatus for trasmitting and receiving video signal |
| CN106791839A (en) * | 2016-12-19 | 2017-05-31 | 中国航空工业集团公司洛阳电光设备研究所 | It is a kind of to CCIR or EIA standard analog video digitized sampling method and devices |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005022928A1 (en) | 2003-08-29 | 2005-03-10 | Mitsubishi Denki Kabushiki Kaisha | Video signal processing circuit, video signal display apparatus, and video signal recording apparatus |
| JP5185212B2 (en) * | 2009-06-12 | 2013-04-17 | 株式会社東芝 | Color signal processing circuit |
| CN102263964B (en) * | 2010-05-31 | 2014-04-09 | 北京创毅视讯科技有限公司 | Method and device for stably displaying mobile analog television image |
| DE102011088810B4 (en) * | 2011-12-16 | 2023-02-02 | Endress+Hauser Conducta Gmbh+Co. Kg | Electronic circuit and method for demodulating useful signals from a carrier signal and a modem |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000102032A (en) * | 1998-09-18 | 2000-04-07 | Hitachi Denshi Ltd | Composite-component converter |
| JP2001095005A (en) * | 1999-09-20 | 2001-04-06 | Matsushita Electric Ind Co Ltd | Clock-generating circuit |
-
2004
- 2004-03-04 JP JP2004060844A patent/JP2005252688A/en active Pending
-
2005
- 2005-03-04 CN CN200510051347A patent/CN100576927C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102223496A (en) * | 2010-04-13 | 2011-10-19 | 新港传播媒介公司 | Dual burst locked oscillator architecture for an analog television receiver |
| CN102223496B (en) * | 2010-04-13 | 2013-12-25 | 新港传播媒介公司 | Dual burst locked oscillator (BLO) architecture for analog television receiver |
| CN104410848A (en) * | 2014-03-31 | 2015-03-11 | 奈斯特株式会社 | Method and apparatus for trasmitting and receiving video signal |
| CN106791839A (en) * | 2016-12-19 | 2017-05-31 | 中国航空工业集团公司洛阳电光设备研究所 | It is a kind of to CCIR or EIA standard analog video digitized sampling method and devices |
| CN106791839B (en) * | 2016-12-19 | 2020-03-27 | 中国航空工业集团公司洛阳电光设备研究所 | Method and device for digitally sampling CCIR (China center IR) or EIA (electronic article Association) standard analog video |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005252688A (en) | 2005-09-15 |
| CN100576927C (en) | 2009-12-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1665310A (en) | Video signal transduce device and video signal transduce method | |
| US4870661A (en) | Sample rate conversion system having interpolation function | |
| KR0161678B1 (en) | Sampling frequency converter | |
| CN100426835C (en) | Clamp control method and related circuit | |
| CN1801951A (en) | Over-sampling a/d converting circuit | |
| CN1117487C (en) | YC separation circuit | |
| CN1008583B (en) | Digital scaling circuit with truncation deviation compensation | |
| US4982179A (en) | Composite video signal generation method and device | |
| CN1158858C (en) | External synchronous system using composite synchronous signal and camera chain using the same system | |
| CN1189041C (en) | Digital colour signal reproducing system | |
| US5621477A (en) | Digital decoder and method for decoding composite video signals | |
| US5285263A (en) | Sample rate converter for digital video signals having reduced phase error and sync point coincidence | |
| JP4679406B2 (en) | Video signal converter | |
| JP4461521B2 (en) | Sampling clock generation circuit | |
| CN1098586A (en) | The demodulator circuit of colour signal and demodulation method | |
| JP3209187B2 (en) | Clock frequency conversion circuit, conversion method therefor, and image receiving apparatus provided with clock frequency conversion function | |
| JP3119662B2 (en) | Component signal sampling circuit and reproduction circuit | |
| JP2004048088A (en) | Signal processor | |
| JP2014036236A (en) | Video signal processing device | |
| CN1105459C (en) | Poly phase filter for dot sequential color difference signal conversion | |
| JP2537821B2 (en) | Signal processor | |
| JPS62164379A (en) | Signal generator circuit for blanking | |
| JPH0522751A (en) | Color signal processing circuit | |
| JPH10155162A (en) | Sampling phase converter | |
| JPH0851553A (en) | Synchronization processing unit for television receiver |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |