CN1664909A - LCD and integrated drive chips - Google Patents
LCD and integrated drive chips Download PDFInfo
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- CN1664909A CN1664909A CN 200510064184 CN200510064184A CN1664909A CN 1664909 A CN1664909 A CN 1664909A CN 200510064184 CN200510064184 CN 200510064184 CN 200510064184 A CN200510064184 A CN 200510064184A CN 1664909 A CN1664909 A CN 1664909A
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- 239000004973 liquid crystal related substance Substances 0.000 claims description 4
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- 239000003990 capacitor Substances 0.000 description 2
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Abstract
This invention relates to LCD device, which comprises LCD display module, integration drive chip and power circuit, wherein, the chip is to drive the LCD module to display image according to visual signals with pulse wide modulation control circuit; the PWM control circuit is to orderly output N pieces of signals; the power circuit orderly outputs N branches of direct current with part to LCD module and the other part to the integration chip.
Description
Technical field
The present invention relates to a kind of LCD, particularly a kind of LCD with integrated pwm control circuit chip for driving.
Background technology
Please refer to Fig. 1, it is the structural representation of conventional liquid crystal.LCD 100 comprises video signal preprocessor (Video processor) 102, sequential control circuit (Timingcontroller) 104, power circuit (Power Circuit) 106 and LCD MODULE 108.
So, except above-mentioned+5 with+3.3 volts, power circuit 106 still needs and provides+7.5 ,-10 with+15 volts operating voltage so that LCD 100 operations, and power circuit 106 has three groups of DC-to-DC converter (DC-DC converter), with provide respectively+7.5 ,-10 with+15 volts operating voltage.So LCD 100 just needs a pulse-length modulation, and (Pulse Width Modulation, PWM) control circuit 110 drives three groups of DC-to-DC converter (not being shown among Fig. 1).
In addition, traditional LCD 100, in the flow process of power supply, pwm control circuit 110 is not exported pwm control signal in regular turn and is given power circuit 106.Like this, power circuit 106 after start, just required voltage during output scanning driving circuit operation simultaneously ,+15 volts with-10 volts, and required voltage during the logical circuit operation.Like this, required operating voltage inputs to earlier in the scan drive circuit when+15 volts operating voltage are operated than logical circuit, might cause scan drive circuit, and moment produces big electric current, and causes the damage probability of scan drive circuit higher.
In addition, when start, if provide simultaneously logical circuit when operation required voltage and scan drive circuit required+15 volts with-10 volts operating voltage, will cause video processing circuit 102 also not output pixel data to data drive circuit, the just first output scanning signal of scan drive circuit makes display frame the situation of mess code occur to pel array.
In sum, LCD 100 needs video signal preprocessor 102, sequential control circuit 104 and pwm control circuit at least, totally three IC.This kind way is made required cost based on cost consideration with significantly increasing.In addition, the design of pwm control circuit 110 also can cause the problem that the damage probability of scan drive circuit improves and mess code occurs when start.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of LCD that comprises integrated drive electronics, make the required cost to reduce except the quantity that can reduce chip for driving, occur the problem of mess code in the time of also can reducing the probability of scan drive circuit damage and solve start.
According to purpose of the present invention, a kind of LCD is proposed.This LCD comprises LCD MODULE, integrated drive chips and power circuit.Integrated drive chips comes the display image picture according to vision signal to drive LCD MODULE, and it comprises pulse-length modulation (Pulse Width Modulation, PWM) control circuit (following common name pwm control circuit).Pwm control circuit is in order to export N pwm signal in regular turn, and N is a positive integer.Power circuit is exported N DC voltage in regular turn according to N pwm signal, and the part of this N DC voltage exports LCD MODULE to, and another part of this N DC voltage exports integrated drive chips to.
According to another object of the present invention, a kind of integrated drive chips of LCD is proposed.LCD has LCD MODULE and power circuit.Power circuit is exported N group DC voltage in regular turn according to N pwm signal.Integrated drive chips comprises video signal preprocessor, sequential control circuit and pwm control circuit.Video signal preprocessor is used for according to the vision signal output pixel data to LCD MODULE.Sequential control circuit makes LCD MODULE display image picture in order to the operation of control LCD MODULE.When integrated drive chips was enabled, pwm control circuit was exported N pwm signal in regular turn.Wherein, the part of N DC voltage exports LCD MODULE to, and another part of N DC voltage exports integrated drive chips to.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail as follows:
Fig. 1 is the structural representation of conventional liquid crystal.
Fig. 2 is the synoptic diagram of a kind of LCD of a preferred embodiment of the present invention.
Fig. 3 is the calcspar of LCD.
Fig. 4 is the circuit diagram of pwm control circuit.
Fig. 5 is the generation sequential of pwm signal and the sequential chart of capacitance voltage.
Embodiment
The invention provides a kind of LCD and integrated drive chips thereof, except reducing the quantity of chip for driving, make outside the required cost to reduce, integrated drive chips of the present invention more can be controlled pwm signal that integrated drive chips exports and time delay to each other by the capacitance of adjusting external capacitive, occurs the problem of mess code when reducing the probability that scan drive circuit damages and solving start.
Please refer to Fig. 2, it is the synoptic diagram of a kind of LCD of a preferred embodiment of the present invention.LCD 200 comprises LCD MODULE 202, integrated drive chips 204 and power circuit 206.Integrated drive chips 204 is according to vision signal, and for example CVBS, Y/C, RGB or YCbCr are to drive LCD MODULE 202 display image pictures.Integrated drive chips 204 also comprises pwm control circuit 208.This pwm control circuit 208 is exported N pwm signal P (N) in regular turn.Power circuit 206 is exported N DC voltage V (N) in regular turn according to N pwm signal P (N).The part of N DC voltage V (N) exports LCD MODULE 202 to, and another part of N DC voltage V (N) exports integrated drive chips 204 to.
Please refer to Fig. 3, it is the composition block schematic diagram of LCD.LCD MODULE 202 also comprises data drive circuit 302, scan drive circuit 304 and pel array 306.Integrated drive chips 204 also comprises video signal preprocessor 210, sequential control circuit 212, phase-locked loop and IIC communication interface (phase-locked loop and IIC communication interface are not shown among Fig. 3).During integrated drive chips 204 operation, receive that external power source produces+5 volts with+3.3 volts operating voltage.Required operating voltage when for example+3.3 volt being the logical circuits operation in the integrated drive chips 204 is+3.3 volts with voltage regulator with+5 volts of step-downs for example again.Voltage regulator is not shown among Fig. 3.Video signal preprocessor 210 comprises an image processor (Video Processor) and a color data processor (RGB processor), and image processor and color data processor are not shown among Fig. 3.Video signal preprocessor 210 is according to vision signal, CVBS for example, output pixel data, R for example, G, B data, to data drive circuit 302 so that data drive circuit 302 according to pixel data output pixel voltage to pel array 306.Sequential control circuit 212 makes data drive circuit 302 and scan drive circuit 304 drive pel array 306 display image pictures in order to the operation of control data driving circuit 302 with scan drive circuit 304.Required clock signal during phase-locked loop output timing control circuit 212 operation.
An above-mentioned N pwm signal comprises the first pwm signal P (1), the second pwm signal P (2) and the 3rd pwm signal P (3), i.e. N=3.Pwm control circuit 208 in regular turn output pwm signal P (1), P (2) and P (3) to power circuit 206.Power circuit 206 has more three groups of DC-to-DC converter (DC-DCconverter), is respectively the first DC-to-DC converter DC (1), the second DC-to-DC converter DC (2) and the 3rd DC-to-DC converter DC (3).
First group of DC-to-DC converter DC (1) is in order to receive the first pwm signal P (1) and to export the first DC voltage V1 and the first feedback signal FB1.Required power supply when the first DC voltage V1 is integrated drive chips 204 operation.Second group of DC-to-DC converter DC (2) is in order to receive the second pwm signal P (2) and to export the second DC voltage V2 and the second feedback signal FB2.Required power supply when the second DC voltage V2 is scan drive circuit 304 operation.The 3rd DC-to-DC converter DC (3) receives the 3rd pwm signal P (3) and exports the 3rd DC voltage V3 and the 3rd feedback signal FB3, required power supply when the 3rd DC voltage V3 is scan drive circuit 304 operation.
Please refer to Fig. 4, it is the circuit diagram of pwm control circuit.Pwm control circuit 2 08 comprises resistance R, first comparer 402 (1), second comparer 402 (2), the 3rd comparer 402 (3), the first pwm signal generator 404 (1), the second pwm signal generator 404 (2) and the 3rd pwm signal generator 404 (3).One end of resistance R optionally receives one first voltage vcc, for example+5 volt.The other end of resistance R is coupled to one first fixed voltage, for example ground voltage via external capacitive C.External capacitive C has capacitance voltage Vc.After an end of resistance R began to receive first voltage vcc, external capacitive C begins charging promoted capacitance voltage Vc gradually.
First comparer 402 (1) is in order to export the first control signal E1.Second comparer 402 (2) is in order to export the second control signal E2.The 3rd comparer 402 (3) is in order to export the 3rd control signal E3.The first pwm signal generator 404 (1) when enabling, produces first pwm signal P (1) according to the first feedback signal FB1 in the first control signal E1.The second pwm signal generator 404 (2) when enabling, produces second pwm signal P (2) according to the second feedback signal FB2 in the second control signal E2.The 3rd pwm signal generator 404 (3) when enabling, produces three pwm signal P (3) according to the 3rd feedback signal FB3 in the 3rd control signal E3.
When pwm control circuit 208 operation, begin to receive+5 volts first voltage vcc.+ 5 volts are charged to outside capacitor C via resistance R, and the voltage rate of rise of its capacitance voltage Vc is by the resistance value of resistance R and the capacitance decision of external capacitive C.Please be simultaneously with reference to Fig. 5, it is the generation sequential of pwm signal and the sequential chart of capacitance voltage.The curve RC of capacitance voltage Vc as shown in Figure 5, when capacitance voltage Vc rises to greater than first reference voltage level, 0.25 times Vcc for example, first comparer 402 (1) makes the first control signal E1 for enabling.When the first control signal E1 when enabling, the first DC-to-DC converter DC (1) just exports the first DC voltage V1 to integrated drive chips 204, for example provide+7.5 volts DC voltage V1 is to video signal preprocessor 210, so that video signal preprocessor 210 energy output image data (R, G, B date), first feedback signal FB1 to the first pwm signal generator 404 (1) of the first DC-to-DC converter DC (1) output simultaneously, make the first pwm signal generator 404 (1) adjust the turn-on cycle of the first pwm signal P (1) according to this, make output voltage+7.5 of the first DC-to-DC converter DC (1) volt keep stable.
Then, capacitance voltage Vc continues to rise to greater than second reference voltage level, 0.5 times Vcc for example, and second comparer 402 (2) makes the second control signal E2 for enabling.When the second control signal E2 when enabling, the second DC-to-DC converter DC (2) just exports the second DC voltage V2 to scan drive circuit 304,-10 volts DC voltage V2 for example is provided, so that the sweep signal VGL of scan drive circuit 304 energy output low levels, second feedback signal FB2 to the second pwm signal generator 404 (2) of the second DC-to-DC converter DC (2) output simultaneously, so that second PWM generator 404 (2) is adjusted the turn-on cycle of the second pwm signal P (2) according to this, so that the output voltage-10 of the second DC-to-DC converter DC (2) volt is kept is stable.
Capacitance voltage Vc continues to rise to greater than the 3rd reference pressure value, 0.75 times Vcc for example, and as above-mentioned principle of work, the 3rd comparer 402 (3) makes the 3rd control signal E3 for enabling.The 3rd DC-to-DC converter DC (3) just exports the 3rd DC voltage V3 to scan drive circuit 304, for example provide+15 volts DC voltage V3, make scan drive circuit 304 can export the sweep signal VGH of high level, and export the 3rd feedback signal FB3 simultaneously.So far in the whole LCD 200, except backlight module drive circuit, just only need+5 volts operating voltage to bring into operation.
Like this, when LCD 200 starts, produce+5 volts of operating voltage by external power source earlier and use, make+5 volts to begin outside capacitor C charging for corresponding circuit with+3.3 volts.So the drive IC in the scan drive circuit 304 can be first during the receive logic computing behind required operating voltage+3.3 volt, just receives-10 volts second DC voltage V2 and+15 volts the 3rd DC voltage V3 in regular turn.Like this, before the drive IC in the scan drive circuit 304 can avoid logical signal also not start, just the big electric current that is produced by moment earlier burnt.
In addition, provide earlier+after 7.5 volts the first DC voltage V1 allows view data be ready to earlier to video signal preprocessor 210, second DC voltage and+15 volts the 3rd DC voltage that provide-10 volts again are to scan drive circuit 304, avoiding sweep signal to enable, but view data does not also input to the problem that mess code appears in the display frame that causes in the data drive circuit 302.And integrated drive chips 204 of the present invention can be by adjusting the capacitance size of external capacitive C, controls pwm signal P (1), P (2) and P (3) time delay to each other, changes time delay in more resilient mode.
In disclosed in the above-described embodiments LCD and the integrated drive chips thereof, only need an integrated drive chips and power circuit just can drive the LCD MODULE operation, so, can significantly reduce and make required cost.In addition, the design by pwm control circuit more can reduce the probability of scan drive circuit damage and solve the problem that occurs mess code when starting shooting.
In sum; though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can change and modification, so protection scope of the present invention is as the criterion with the claim institute restricted portion that is proposed.
Claims (10)
1. a LCD comprises:
One LCD MODULE;
One integrated drive chips comes the display image picture according to a vision signal to drive this LCD MODULE, and this integrated drive chips comprises a pulse-length modulation (PWM) control circuit, and in order to export N pwm signal in regular turn, N is a positive integer; And
One power circuit is exported N DC voltage in regular turn according to this N pwm signal, and the part of this N DC voltage exports this LCD MODULE to, and another part of this N DC voltage exports this integrated drive chips to.
2. LCD as claimed in claim 1, wherein this LCD MODULE has a data drive circuit, scan driving circuit and a pel array.
3. LCD as claimed in claim 2, wherein this integrated drive chips also comprises:
One video signal preprocessor is in order to export a pixel data to this data drive circuit according to this vision signal; And
One sequential control circuit is in order to control the operation of this data drive circuit and this scan drive circuit, so that this data drive circuit and this scan drive circuit drive this pel array.
4. LCD as claimed in claim 3, wherein, this N pwm signal comprises one first pwm signal, one second pwm signal and one the 3rd pwm signal, this pwm control circuit comprises:
One resistance, one end of this resistance optionally receives one first fixed voltage, the other end of this resistance is coupled to one second fixed voltage via an external capacitive, this external capacitive has a capacitance voltage, after an end of this resistance began to receive this first fixed voltage, this external capacitive begins charging promoted described capacitance voltage gradually;
One first comparer, in order to exporting one first control signal, when this capacitance voltage during greater than one first reference voltage level, this first control signal is for enabling;
One second comparer, in order to exporting one second control signal, when this capacitance voltage during greater than one second reference voltage level, this second control signal is for enabling;
One the 3rd comparer, in order to exporting one the 3rd control signal, when this capacitance voltage during greater than one the 3rd reference voltage level, the 3rd control signal is for enabling;
One first PWM generator, in order in this first control signal when enabling, produce this first pwm signal;
One second PWM generator, in order in this second control signal when enabling, produce this second pwm signal; And
One the 3rd PWM generator, in order in the 3rd control signal when enabling, produce the 3rd pwm signal.
5. LCD as claimed in claim 4, wherein, this N DC voltage comprises one first DC voltage, one second DC voltage and one the 3rd DC voltage, this power circuit comprises:
One first DC-to-DC converter, in order to receiving this first pwm signal and to export this first DC voltage, this first DC voltage required power supply during for this integrated drive chips operation;
One second DC-to-DC converter, in order to receiving this second pwm signal and to export this second DC voltage, this second DC voltage required power supply during for this scan drive circuit operation; And
One the 3rd DC-to-DC converter, in order to receiving the 3rd pwm signal and to export the 3rd DC voltage, the 3rd DC voltage required power supply during for this scan drive circuit operation.
6. LCD as claimed in claim 5, wherein, this first reference voltage level is less than this second reference voltage level, and this second reference voltage level is less than the 3rd reference voltage level.
7. the integrated drive chips of a LCD, this LCD has a LCD MODULE and a power circuit, and this power circuit is exported N group DC voltage in regular turn according to N pwm signal, and N is a positive integer, and this integrated drive chips comprises:
One video signal preprocessor is in order to export a pixel data to this LCD MODULE according to a vision signal;
One sequential control circuit is in order to control the operation of this LCD MODULE, so that this LCD MODULE display image picture; And
One pulse-length modulation (PWM) control circuit when this integrated drive chips is enabled, is exported this N pwm signal in regular turn;
Wherein, the part of this N DC voltage exports this LCD MODULE to, and another part of this N DC voltage exports this integrated drive chips to.
8. integrated drive chips as claimed in claim 7, wherein, this N pwm signal comprises one first pwm signal, one second pwm signal and one the 3rd pwm signal, this pwm control circuit comprises:
One resistance, one end of this resistance optionally receives one first fixed voltage, the other end of this resistance is coupled to one second fixed voltage via an external capacitive, this external capacitive has a capacitance voltage, after an end of this resistance began to receive this first fixed voltage, this external capacitive begins charging promoted this capacitance voltage gradually;
One first comparer, in order to exporting one first control signal, when this capacitance voltage during greater than one first reference voltage level, this first control signal is for enabling;
One second comparer, in order to exporting one second control signal, when this capacitance voltage during greater than one second reference voltage level, this second control signal is for enabling;
One the 3rd comparer, in order to exporting one the 3rd control signal, when this capacitance voltage during greater than one the 3rd reference voltage level, the 3rd control signal is for enabling;
One first PWM generator is used to this first control signal when enabling, and produces this first pwm signal;
One second PWM generator is used to this second control signal when enabling, and produces this second pwm signal; And
One the 3rd PWM generator is used to the 3rd control signal when enabling, and produces the 3rd pwm signal.
9. integrated drive chips as claimed in claim 8, wherein, this N DC voltage comprises one first DC voltage, one second DC voltage and one the 3rd DC voltage, this power circuit comprises:
One first DC-to-DC converter, in order to receiving this first pwm signal and to export this first DC voltage, this first DC voltage required power supply during for this integrated drive chips operation;
One second DC-to-DC converter, in order to receiving this second pwm signal and to export this second DC voltage, required power supply when this second DC voltage is this liquid crystal display mode block operations; And
One the 3rd DC-to-DC converter receives the 3rd pwm signal and exports the 3rd DC voltage, required power supply when the 3rd DC voltage is this liquid crystal display mode block operations.
10. integrated drive chips as claimed in claim 9, wherein, this first reference voltage level is less than this second reference voltage level, and this second reference voltage level is less than the 3rd reference voltage level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100641849A CN100365697C (en) | 2005-04-13 | 2005-04-13 | LCD and integrated drive chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100641849A CN100365697C (en) | 2005-04-13 | 2005-04-13 | LCD and integrated drive chips |
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| Publication Number | Publication Date |
|---|---|
| CN1664909A true CN1664909A (en) | 2005-09-07 |
| CN100365697C CN100365697C (en) | 2008-01-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005100641849A Expired - Fee Related CN100365697C (en) | 2005-04-13 | 2005-04-13 | LCD and integrated drive chips |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102789754A (en) * | 2011-05-17 | 2012-11-21 | 联咏科技股份有限公司 | Date driver and display module employing same |
| CN109410859A (en) * | 2018-11-21 | 2019-03-01 | 惠科股份有限公司 | A kind of display device and driving method and display |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07281641A (en) * | 1994-04-11 | 1995-10-27 | Oki Electric Ind Co Ltd | Active matrix type liquid crystal display |
| JP2002351417A (en) * | 2001-05-24 | 2002-12-06 | Internatl Business Mach Corp <Ibm> | Driving power supply circuit which generates driving power supply voltage of driver circuit used in display device and reference voltage used in the driver circuit to generate gradation voltage, driver circuit voltage generating method to generate the driving power supply voltage and the reference voltage and display device having the driving power supply circuit |
| JP3854173B2 (en) * | 2002-02-27 | 2006-12-06 | 東北パイオニア株式会社 | Driving method of light emitting display panel and organic EL display device |
-
2005
- 2005-04-13 CN CNB2005100641849A patent/CN100365697C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102789754A (en) * | 2011-05-17 | 2012-11-21 | 联咏科技股份有限公司 | Date driver and display module employing same |
| CN102789754B (en) * | 2011-05-17 | 2015-04-15 | 联咏科技股份有限公司 | Date driver and display module employing same |
| CN109410859A (en) * | 2018-11-21 | 2019-03-01 | 惠科股份有限公司 | A kind of display device and driving method and display |
| US11308911B2 (en) | 2018-11-21 | 2022-04-19 | HKC Corporation Limited | Display device, driving method, and display system |
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| Publication number | Publication date |
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| CN100365697C (en) | 2008-01-30 |
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