CN1664685A - Method of manufacturing array substrate and thin film transistor array panel - Google Patents
Method of manufacturing array substrate and thin film transistor array panel Download PDFInfo
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- CN1664685A CN1664685A CN 200510066934 CN200510066934A CN1664685A CN 1664685 A CN1664685 A CN 1664685A CN 200510066934 CN200510066934 CN 200510066934 CN 200510066934 A CN200510066934 A CN 200510066934A CN 1664685 A CN1664685 A CN 1664685A
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Abstract
This invention relates to an array base board process method, which comprises the following steps: forming a first metal layer on one base board; executing one first etching process for the first metal layer pattern; forming one grating wire with its one grating electrode connected to the wire and with one connection pad to the base board; forming an insulating layer, a semi-conductive layer and an ohmic contact layer on the base board, which all cover the grating wire, grating electrode and the connection pad; executing a second etching process for the pattern of ohmic contact layer, the semi-conductive layer, the grating electrode and part of the insulating layer; forming a semi-conductive structure on the said base board and a dielectric hole in the insulating layer on connection pad to emerge part of the pad, wherein, said semi-conductive structure contains the said insulating layer grossly covering the grating electrode, patterning semi-conductive layer and the patterning ohmic contact layer.
Description
Technical field
The present invention relates to the manufacturing of display device, particularly relate to a kind of manufacture method of thin-film transistor array base-plate.
Background technology
In order to realize high speed image processing and high-quality show image, use widely as the flat-panel screens of color liquid crystal display arrangement in recent years.In liquid crystal indicator, generally include two upper and lower substrates, with bonding or the involution material is bonded together with electrode.And liquid crystal material is received between two substrates, in order to keep distance fixing between two plates, has certain size particles and is interspersed among between above-mentioned two plates.Usually the infrabasal plate surface is formed with the thin film transistor (TFT) that is used for being used as on-off element, this thin film transistor (TFT) have the gate electrode (gate electrode) that is connected in sweep trace (scanning line), the drain electrode (drain electrode) that is connected in signal wire (signal line), with the source electrode (source electrode) that is connected in pixel electrode (pixelelectrode).And upper substrate places the infrabasal plate top, and this upper substrate surface is formed with an optical filter and a plurality of light screening material (as being made of chromium).The periphery of this two substrates has the involution material and is adhesively fixed, and has liquid crystal material between the two substrates.Infrabasal plate also is referred to as array base palte (array substrate), and a plurality of elements formed thereon are then made by the multiple tracks photoetching process usually.The access times of photoetching process and the cost of manufacture of array base palte and output time are closely bound up.
Figure 1A～1F is a series of synoptic diagram, icon use the array base palte technology of six road photoetching processes in the prior art, to be illustrated in the section situation of each operation stage.In herein, each road photoetching process has comprised resistance agent coating, has used the patterning photomask, resistance agent exposure, resistance agent development, etched film and remove the photoetching correlation step that residual resistance agent etc. is well known to those skilled in the art, this only with " photoetching process " be referred to as it.
Please refer to Figure 1A, at first use the first road photoetching process, be formed at a metal level on the substrate 104, and then be formed for the grid 100 and lead 102 of the patterning of thin-film transistor element with definition.Lead 102 can be used as a gate line (or sweep trace) or a data line (or signal wire), and it is formed on the substrate 104 with continuous kenel.
Please refer to Figure 1B, follow smooth formation insulation course 106, semiconductor layer 108 and ohmic contact layer 110 on substrate 104 with covering, and use the second road photoetching process on the insulation course 106 at place, grid 100 tops, to define the semiconductor layer 108 and the ohmic contact layer 110 of patterning.
Please refer to Fig. 1 C, then utilize the 3rd road photoetching process, selectively on each corresponding lead 102, form the interlayer hole 112 that penetrates insulation course 106.
Please refer to Fig. 1 D, then 104 smooth another metal levels that form also then utilize the 4th road photoetching process with covering on substrate, the conductive layer 114 that is positioned at lead 102 and is positioned at the patterning of adjacent gate 100 tops with formation.And in the 4th road photoetching process, metal level 114, ohmic contact layer 110 and the part semiconductor layer 108 of adjacent gate 100 tops passed in etching simultaneously, and then forms recess 116.So, be convenient to finish on the substrate 104 making of thin film transistor (TFT)
Please refer to Fig. 1 E, follow the smooth property covered ground and cover a protective seam 118 in Fig. 1 D on the icon structure, and then form interlayer hole 120 with patterning protective seam 118, to expose the contact area that is positioned at the appropriate location via the use of the 5th road photoetching process.
Please refer to Fig. 1 F, then in protective seam 118 and interlayer hole 120, cover a transparency conducting layer 122, and pass through the use of the 6th road photoetching process, and on protective seam 118, form the transparency conducting layer 122 of patterning, with usefulness as pixel electrode.So, the making of array base palte just comes to an end.
Generally speaking, the lead as sweep trace and signal wire that is present in substrate 104 surfaces is formed with the single conductive layer of continuous kenel.And along with liquid crystal indicator size increase tendency, the sweep trace of being formed with continuous kenel conductive layer and the length of signal wire also increase thereupon, have so just increased the impedance (resistance) of sweep trace and signal wire.So increase of impedance may cause the loss of signal on these a little circuits when liquid crystal indicator is operated, and is unfavorable for the making of large scale liquid crystal display device.And in the active array base plate technology as Figure 1A～1F institute icon, its extra conductive layer 114 that forms on lead 102 is used the lead that be combined into one has thicker degree.So, just can reduce the overall impedance of lead, and can improve on the loss of signal on the lead.Yet above-mentioned arts demand six road photoetching processes make that the making of array base palte is comparatively time-consuming.So, just, need a kind of technology comparatively succinct and be applicable to the array base palte technology of large scale flat display apparatus.
Summary of the invention
Fundamental purpose of the present invention just provides the display device manufacturing method of the less relatively lithographic process steps of use, required cost of manufacture and output time when making to save.
According to above-mentioned purpose, the invention provides a kind of manufacture method of array base palte, comprise the following steps:
Form a first metal layer on a substrate; Implement one first photoetching process with this first metal layer of patterning, form a grid lead, be linked to a gate electrode of this grid lead and a connection pad on this substrate; Form an insulation course, semi-conductor layer and an ohmic contact layer on this substrate, be covered in this grid lead, this gate electrode and this connection pad; And implement one second photoetching process with this ohmic contact layer of patterning, this semiconductor layer and this insulation course partly, form an interlayer hole in semiconductor structure and this insulation course on this connection pad in forming on this substrate, with this connection pad of exposed portions serve, wherein this semiconductor structure comprises this insulation course that is covered in substantially on this gate electrode, this semiconductor layer of patterning and this ohmic contact layer of patterning.
According to above-mentioned purpose, the invention provides a kind of manufacture method of thin-film transistor display panel, comprise the following steps:
Form a first metal layer on a substrate; Implement one first photoetching process with this first metal layer of patterning, on this substrate, form and extend at least one grid lead continuously along first direction, and a plurality of data conductor fragments of extending along a second direction, wherein this first direction differs from this second direction and those data conductor fragments and those grid leads and is separation mutually in intersection; Form an insulation course, semi-conductor layer and an ohmic contact layer on this substrate; Implement one second photoetching process with this ohmic contact layer of patterning, this semiconductor layer and this insulation course, form a plurality of semiconductor structures and a plurality of stack architecture, those stack architectures across those data conductor fragments and those grid leads in intersection; Form one second metal level on this substrate; Implement one the 3rd photoetching process with this second conductive metal layer of patterning, in forming the many continuous data leads that a plurality of source/drain electrodes and formation extend on those bridging structures and is electrically connected those data conductor fragments on those semiconductor structures; Form a protective seam on this substrate; Implement one the 4th photoetching process with this protective seam of patterning, form a plurality of interlayer holes and exposed a plurality of connection pads of those data conductor and those grid leads and one of those source/drain electrodes; And form a transparency conducting layer on this substrate, and fill in those interlayer holes; Implement one the 5th photoetching process with this transparency conducting layer of patterning, form a plurality of pixel electrodes and reservior capacitor, wherein those reservior capacitors partially overlap on those grid leads.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Figure 1A～1F is a series of synoptic diagram, icon use the array base palte technology of six road photoetching processes in the prior art, to be illustrated in the section situation of each operation stage.
Fig. 2 A, 3A, 4A, 5A and 6A are a series of synoptic diagram, have illustrated according to looking situation on the making flow process of the active array base plate of one embodiment of the invention.
Fig. 2 B, 3B, 4B, 5B and 6B illustrate the sectional view of making flow process of the array base palte of one embodiment of the invention, have shown the section situation of 2B-2B, 3B-3B, 4B-4B, 5B-5B and 6B-6B line segment among Fig. 2 A, 3A, 4A, 5A and the 6A respectively.
Fig. 2 C, 3C, 4C, 5C and 6C illustrate the sectional view of making flow process of the array base palte of one embodiment of the invention, have shown the section situation of 2C-2C, 3C-3C, 4C-4C, 5C-5C, 6C-6C line segment among Fig. 2 A, 3A, 4A, 5A and the 6A respectively.
Fig. 3 D to Fig. 3 G illustrates the sectional view of making flow process of the array base palte of one embodiment of the invention, has shown the making flow process of the employed second road photoetching process among Fig. 3 A～3C respectively.
Fig. 7 A and 8A have illustrated according to looking situation on the making flow process of the active array base plate of another embodiment of the present invention.
Fig. 7 B and 8B illustrate the sectional view of making flow process of the array base palte of one embodiment of the invention, have shown the section situation of 7B-7B and 8B-8B line segment among Fig. 7 A and Fig. 8 A respectively.
Fig. 7 C and 8C illustrate the sectional view of making flow process of the array base palte of one embodiment of the invention, have shown the section situation of 7C-7C and 8C-8C line segment among Fig. 7 A and the 8A respectively.
Fig. 7 D to Fig. 7 G illustrates the sectional view of making flow process of the array base palte of another embodiment of the present invention, has shown the making flow process of the employed second road photoetching and etch process among Fig. 7 A～7C respectively.The simple symbol explanation
100～grid; 102～lead;
104,204～substrate; 106,300～insulation course;
108,302～semiconductor layer; 110,304～ohmic contact layer;
112,120～interlayer hole; 114～conductive layer;
116～recess; 118～protective seam;
122～transparency conducting layer;
200,700～thin-film transistor display panel;
202～grid lead; 202a～gate electrode;
202b, 206b～connection pad; 206a～data conductor fragment;
208～the first recesses; 210～the second recesses;
306,308～stack architecture; 320～photoresist layer;
340,304 '～photomask; 340a～light tight district;
340b～photic zone; 340c～part photic zone;
350,360,370～etching program; The thickness of H1, H2～photoresist layer;
400,402,404,406,408,410～metal level;
308,310,312,412～opening;
500～protective seam; 502,504,506～interlayer hole;
600,602,604～transparency conducting layer.
Embodiment
Fig. 2～6 are a series of synoptic diagram, icon according to the array base palte technology of one embodiment of the invention, to be illustrated in the manufacturing situation of each operation stage, wherein Fig. 2 A, 3A, 4A, 5A and 6A have shown respectively and have looked situation on one, and Fig. 2 B～2C, 3B～3C, 4B～4C, 5B～5C and 6B～6C have then shown the section situation of B-B and C-C line segment in the corresponding top view respectively.Each road photoetching process described herein comprises resistance agent coating, uses the patterning photomask, resistance agent exposure, resistance agent development, etched film and remove the photoetching correlation step that residual resistance agent etc. is well known to those skilled in the art, each road photoetching process can be implemented by the normal standard lithographic equipment that uses of industry, above-mentioned processing step in hereinafter only with " photoetching process " be referred to as it.
Please refer to Fig. 2 A, the part shown a thin-film transistor display panel 200 on look situation.Thin-film transistor display panel 200 comprises a substrate 204, and it is provided with many leads, and for example grid lead 202.In addition, on substrate 204, also be provided with a plurality of lead fragments, for example data conductor fragment 206a.Grid lead 202 comprises metal or other conductive material with data conductor fragment 206a, and in Fig. 2 A according to shown in row arrange with the formed specific pattern of column direction, but it also can and not limit with the arrangement mode in Fig. 2 A according to the alternate manner arrangement.At this, its pattern forms via the first road photoetching process.
In this first road photoetching process, definition forms and is covered in the metal level on the substrate 204 and forms this a little grid leads 202 and data conductor fragment 206a simultaneously, and it is arranged according to a column direction substantially.In addition, in this first photoetching process, also formed other member on substrate, for example linked a plurality of gate electrode 202a be linked to each grid lead 202 respectively, it is arranged according to a line direction substantially, as the usefulness of the gate electrode of each thin film transistor device.In addition, the large-area connection pad 206b etc. that has also formed the large-area connection pad 202b that links grid lead 202 and be linked to data conductor fragment 206 is used for the zone that circuit links.
Shown in Fig. 2 A, be formed with first recess 208 in the intersectional region of data conductor fragment 206a and grid lead 202, use and separate data conductor fragment 206a and contiguous grid lead 202.In addition, between gate electrode 202a and proximity data lead fragment 206a, then separate by second recess 210.
Please refer to Fig. 2 B, the section situation that has shown 2B-2B line segment in Fig. 2 A, wherein be formed with a grid lead 202 on the substrate 204, be used for a gate electrode 202a of thin film transistor device and be positioned at gate electrode 202a and proximity data lead fragment (not icon) between second recess 210.The thickness of grid lead 202 and gate electrode 202a is approximately between 1500～5000 dusts, its material for example is aluminium (Al), molybdenum (Mo), chromium (Cr), aluminium alloy metal materials such as (Al alloy), and for example molybdenum and aluminium ruthenium (Mo/AlNd or AlNd/Mo), molybdenum and aluminium (Mo/Al), titanium and aluminium ruthenium (Ti/AlNd or AlNd/Ti), titanium and aluminium (Ti/Al or Ti/Al/Ti), chromium and aluminium (Cr/Al), chromium and aluminium ruthenium (Cr/AlNd or AlNd/Cr) formed composite metal or other metal material.Fig. 2 C has then shown the section situation of 2C-2C line segment in Fig. 2 A, wherein forms data conductor fragment 206a and grid lead 202 that promising first recess 208 is separated and the connection pad 202b that is linked to grid lead 202 on the substrate 204.The thickness of data conductor fragment 206a, grid lead 202 and connection pad 202b is approximately between 1500～5000 dusts, its material for example is aluminium, molybdenum, chromium, aluminium alloy metal materials such as (Al alloy), and for example molybdenum and aluminium ruthenium (Mo/AlNd or AlNd/Mo), molybdenum and aluminium (Mo/Al), titanium and aluminium ruthenium (Ti/AlNd or AlNd/Ti), titanium and aluminium (Ti/Al or Ti/Al/Ti), chromium and aluminium (Cr/Al), chromium and aluminium ruthenium (Cr/AlNd or AlNd/Cr) formed compound substance or other metal material.
Please refer to Fig. 3 A, part shown form on the then thin-film transistor display panel 200 in Fig. 2 A have behind insulation layer patterned 300, semiconductor layer 302 and the ohmic contact layer 304 on look situation, the rete of these a little patternings forms simultaneously via the second road photoetching process institute.Wherein, insulation course 300 is formed at gate electrode 202a and is adjacent on the part of grid pole lead 202 of gate electrode 202a, data conductor 206a and the substrate 204, and fills in first recess 208 (seeing Fig. 3 B for details) and second recess 210 (seeing Fig. 3 C for details) between these a little members.At this, ohmic contact layer 304 is shown as the pattern of inverted L shape and covers semiconductor layer 302 substantially, so semiconductor layer 302 and in not being shown in Fig. 3 A.
Please be simultaneously with reference to Fig. 3 B and Fig. 3 C, the section situation that has shown interior 3B-3B of Fig. 3 A and 3C-3C line segment respectively, the material that wherein forms insulation course 300, semiconductor layer 302 and ohmic contact layer 304 at first in regular turn and smoothly form with covering and be stacked on the substrate 204, by the execution of the second road photoetching process, the photomask and the single photoetching that are provided with the photic zone of different printing opacity degree by collocation have the situation of multiple photoresist thickness to form on ohmic contact layer 304.And by follow-up continuous three road etching programs, define respectively as the storehouse respectively as shown in Fig. 3 B and Fig. 3 C and be adjacent to stack architecture 306,308 on gate electrode 202a, first recess 208 and its adjacent substrates 204.Wherein, the material of insulation course 300, semiconductor layer 302 and ohmic contact layer 304 for example is silicon nitride or silicon oxynitride (SiO respectively
xN
y), α-Si:H material and n
+α-Si:H material, its thickness then for example are respectively 2000～5000 dusts, 1000～3000 dusts and 100～1000 dusts.
In this second photoetching process, simultaneously the insulation course 300 in the formed stack architecture 306 and 308 has formed a dielectric barrier with 302 of semiconductor layers near corresponding to substrate 204 places of each first recess 208 and each second recess 210, with avoid contiguous grid lead 202 and data conductor fragment 206a with and/or the data conductor fragment 206a of vicinity is electrically connected with 202 of grid leads and the bad situation of short circuit.Fig. 3 B has shown that Fig. 3 C has then shown the stack architecture of being made up of patterned insulation course 300, semiconductor layer 302 and the ohmic contact layers 304 inserted in first recess 208 308 by the stack architecture of inserting in second recess 210 of being made up of patterned insulation course 300, semiconductor layer 302 and ohmic contact layer 304 306.
At this, employed photomask of the second road photoetching process and subsequent etch program will be by Fig. 3 D～3G in hereafter.Please refer to Fig. 3 D, only illustrate in the second road photoetching process at this, in be adjacent to gate electrode 202a with in the manufacturing situation in connection pad 202b zone, those skilled in the art be when understanding the present invention, and can be applied to the manufacturing in other zone according to actual design.Substrate 204 at first is provided, has been formed with gate electrode 202a and connection pad 202b on it.Gate electrode 202a and connection pad 202b are then covered by the gate insulation layer 300, semiconductor layer 302 and the ohmic contact layer 304 that are formed in regular turn on the substrate 204.Then, painting photoresist layer 320 on substrate 304, and implement the second road photoetching process by the normal standard lithographic equipment that uses of industry, adopted the photomask 340 shown in Fig. 3 D.At this, photomask 340 comprises that light tight district 340a, photic zone 340b and part photic zone 340c etc. have the zone of different transmittances.The transmittance of wherein light tight district 340a is 0%, its aligned in general is in the top of gate electrode 202a, and the transmittance of photic zone 340 is 100%, and its aligned in general is in connection pad 202b top, and the transmittance of part photic zone 340c is approximately between 20～80%, and its aligned in general is in other specific region.After implementing the second road photoetching process,, and after development of photoresist, then form the situation shown in Fig. 3 D by single exposure program.Patterned photoresist layer 320 only residues on gate electrode 202a and the contiguous ohmic contact layer 204 thereof.Because the different factor of penetrability of zones of different, the photoresist layer 320 that is positioned at photic zone 340b below will be removed through developing fully because of exposing, and the photoresist floor 320 that is positioned at light tight district 340a and part photic zone 304c below will stay the photoresist floor 320 with different-thickness because of the exposure of not accepting exposure or only accept on the part degree after developing, the photoresist floor 320 that wherein is positioned at 340a below, light tight district has the thickness H1 that is about 15000～30000 dusts, and the photoresist layer 320 that is positioned at part photic zone 304c below then has the thickness H2 that is about 3000～20000 dusts.
Please refer to Fig. 3 E, then implement an etching program 350, for example use to comprise sulfur hexafluoride (SF
6), carbon tetrafluoride (CF
4) or the dry etch procedure (please replenish) of other appropriate reaction gas; by photoresist layer 320 as etch protection layer; ohmic contact layer 304, semiconductor layer 302 and the insulation course of not protected by the photoresist layer 300 removed in etching, and etching stops at substrate 204 and connection pad 202b.
Please refer to Fig. 3 F, then implement another etching program 360, for example use to comprise oxygen (O
2), sulfur hexafluoride and oxygen (SF
6/ O
2) or the dry etch procedure (please replenish) of other appropriate reaction gas, etching photoresist layer 320, exposed portions serve is adjacent to the ohmic contact layer 304 of gate electrode 202a.At this moment, photoresist layer 320 still residues in the zone of gate electrode 202a top.
Please refer to Fig. 3 G, then implement another etching program 370, for example use to comprise chlorine (Cl
2), sulfur hexafluoride and chlorine (SF
6/ Cl
2), chlorine and boron chloride (Cl
2/ BCl
3), carbon tetrafluoride (CF
4) or the dry etch procedure (please replenish) of other reacting gas, with etching be not the ohmic contact layer 304 that covered of photoresist layer 320 with its under semiconductor layer 302, and stop on the insulation course 300.And then stack architecture 360 and connection pad 202b shown in Fig. 3 B have been formed.
Please refer to Fig. 4 A, part shown behind the metal level 400,402,404,406,408,410 that forms patterning on the then thin-film transistor display panel 200 in Fig. 3 A and the opening 412 on look situation, the metal level of these a little patternings forms simultaneously via the 3rd road photoetching process institute.Wherein metal level 400 and 402 follows direction and is covered in data conductor fragment 206a (not icon) respectively substantially, is formed on the ohmic contact layer 304 and connection pad 206b (not shown) between data conductor fragment 206a, and links the data conductor fragment 206a of its below and form data conductor.It is low-resistance value (resistance) that the data conductor of structure like this can have the morphogenetic data conductor of more traditional continuous type, is more suitable for large-sized display device, to be reduced to the loss of signal on this circuit.Metal level 404 and 406 are covered in respectively on the grid lead 202a (not icon) and contiguous insulation course 300 and connection pad 202b thereof of part substantially along column direction.408 of metal levels are covered on substrate 204, insulation course 300 and the ohmic contact layer 304 of part, and metal level 410 then is covered on the ohmic contact layer 304 and is linked to metal level 400.In the 3rd road photoetching process, also etching is passed the ohmic contact layer 304 that is positioned at gate electrode 202a pars intermedia top and part semiconductor layer 302 and has been formed an opening 412 that exposes semiconductor layer 302.
At this, metal level 400,402,404,406 is overlapped and directly is linked to grid lead 202, data conductor fragment 206a and the connection pad 202a and the 202b of previous formation, thereby has increased the thickness of partial data lead 202 with data conductor fragment 206a.These a little metal layer thickness are approximately between 2000～4000 dusts, and its material for example is aluminium (Al), molybdenum (Mo), chromium (Cr) or other metal material.
Please show the section situation of interior 4B-4B of Fig. 4 A and 4C-4C line segment respectively simultaneously with reference to Fig. 4 B and Fig. 4 C.Wherein, Fig. 4 B has shown to be via opening 412 that is formed at stack architecture 306 places and the patterned metal layer of being separated for opening 412 408 and 410 in the 3rd road photoetching process.Opening 412 has exposed the semiconductor layer 302 in it, and thereby has defined the source/drain regions of thin film transistor (TFT).So far, stack architecture 306 just is applicable as the usefulness of thin film transistor (TFT), directly be formed at metal level 408 and 410 on its ohmic contact layer 302 and then can be used as the usefulness of source/drain electrodes, wherein metal level 408 can more extend on the substrate 204 of part, and metal level 410 then extends second recess, 210 places and and then is linked to its contiguous metal level 400 (not shown).
Please refer to Fig. 4 B and Fig. 4 C, metal level 400,404 and 406 has increased the thickness of data conductor fragment 206a, grid lead 200 and connection pad 202b, and it is discrete formation in the interlaced area place, and separates mutually to each other to prevent that short circuit condition from taking place.
Please refer to Fig. 5 A; part shown form on the then thin-film transistor display panel 200 in Fig. 4 A after the patterned protective layer 500 on look situation; it forms via the 4th road photoetching process, and forms interlayer hole 502,504 and 506 to have exposed the metal level 402,406 and 408 of part respectively in protective seam 500.The thickness of the material of protective seam 500 is approximately between 1000～50000 dusts, and its material for example is silicon nitride (SiN
X), monox (SiO
X), silicon oxynitride (SiO
XN
y), organic material or other material.
Please show the section situation of interior 5B-5B of Fig. 5 A and 5C-5C line segment respectively simultaneously with reference to Fig. 5 B and Fig. 5 C.Wherein, protective seam 500 is smooth to be formed on the substrate 204 with covering and to be covered in the structure of previous formation, and defines interlayer hole 502 and 504 via the 4th road photoetching etching.Opening 502 and 504 is the metal level 408 and 406 of exposed portions serve respectively.
Please refer to Fig. 6 A, part shown behind the transparency conducting layer 600,602 and 604 that forms a patterning on the then thin-film transistor display panel 200 in Fig. 5 A on look situation, it forms via the 5th road photoetching process, wherein transparency conducting layer 600 is formed in the viewing area that is defined by data conductor and grid lead, and see through opening 506 and be linked to the metal level 408 of its below, with transmission from the electric current of metal level 408 in it.Transparency conducting layer 602 and 604 see through opening 502 and 504 and be electrically connected on metal level 402 and 406 below it respectively.Transparency conducting layer 600,602 and 604 its materials for example be indium tin oxide (indium tin oxide, ITO) or indium-zinc oxide (indium zincoxide, IZO), its thickness is about 400～2000 dusts.At this, be covered in the usefulness that transparency conducting layer 600 parts on the protective seam 500 can be used as pixel electrode, be covered in the usefulness that transparency conducting layer 600 parts on the grid lead 204 then can be used as the reservior capacitor member.Fig. 6 B and Fig. 6 C have then shown the section situation of interior 6B-6B of Fig. 6 A and 6C-6C line segment respectively, and transparency conducting layer 600,604 sees through opening 502,504 respectively and is electrically connected with the metal level 408 and 406 formation of its below.
Fig. 7～8 are a series of synoptic diagram, icon according to the array base palte technology of another embodiment of the present invention, the processing step broadly similar of the manufacturing situation in its operation stage is in last embodiment, only show the difference place of its two embodiment at this, wherein Fig. 7 A and 8A have shown respectively and have looked situation on one, and Fig. 7 B～7C and 8B～8C have then shown the section situation of B-B and C-C line segment in the corresponding top view respectively.
Please refer to Fig. 7 A, part shown after forming gate insulation layer 300, semiconductor layer 302 and ohmic contact layer 304 on the thin-film transistor display panel 700 with patterning on look situation.Before these a little retes form, be formed with conductive film crystal array panel 200 structures that are same as Fig. 2 A on this thin-film transistor display panel 700, and the rete of these a little patternings forms simultaneously via one second road photoetching process institute.Wherein, compared to Fig. 3 A, gate insulation layer 300 smooth being covered on the whole base plate 204 (not shown) with covering, and fill in first recess 208 (seeing Fig. 7 B for details) and second recess 210 (seeing Fig. 7 C for details) between these a little members.Ohmic contact layer 304 with inverted L shape then is formed on the gate insulation layer 300, and is covered in substantially on the data conductor fragment 206a of gate electrode 202a and vicinity thereof.In gate insulation layer 300, then be formed with opening 308,310 and 312 grid lead 202 and connection pad 202b and 206b with the difference exposed portions serve.Fig. 7 B and Fig. 7 C, the section situation that has then shown interior 7B-7B of Fig. 7 A and 7C-7C line segment respectively, the material that wherein forms gate insulation layer 300, semiconductor layer 302 and ohmic contact layer 304 at first in regular turn and smoothly form with covering and be stacked on the substrate 204, by the execution of the second road photoetching process, the single photo mask and the single photoetching that are provided with different photic zones by collocation have the situation of multiple photoresist thickness to form on ohmic contact layer 304.And by follow-up continuous three road etching programs, define respectively and be adjacent to gate electrode 202a, first recess 208 as the storehouse respectively as shown in Fig. 7 B and Fig. 7 C and be close to stack architecture 306,308 on gate insulation layer 204 with it.Wherein, the material of gate insulation layer 300, semiconductor layer 302 and ohmic contact layer 304 for example is silicon nitride, α-Si:H material and n respectively
+α-Si:H material, its thickness then for example are respectively 2000～5000 dusts, 1000～3000 dusts and 100～1000 dusts.
At this, above-mentioned employed photomask of the second road photoetching process and subsequent etch program will be by Fig. 7 D～7G in hereafter.Please refer to Fig. 7 D, only illustrate in the second road photoetching process at this, in be adjacent to gate electrode 202a with in the manufacturing situation in connection pad 202b zone, those skilled in the art be when understanding the present invention, and can be applied to the manufacturing in other zone according to actual design.Substrate 204 at first is provided, has been formed with gate electrode 202a and connection pad 202b on it.Gate electrode 202a and connection pad 202b are then covered by the gate insulation layer 300, semiconductor layer 304 and the ohmic contact layer 306 that are formed in regular turn on the substrate 204.Then, painting photoresist layer 320 on substrate 304, and implement the second road photoetching process by the normal standard lithographic equipment that uses of industry, adopted the photomask 340 ' shown in Fig. 7 D.At this, photomask 340 ' comprises that light tight district 340a, photic zone 340b and part photic zone 340c etc. have the zone of different transmittances.The transmittance of wherein light tight district 340a is 0%, its aligned in general is in the top of gate electrode 202a, and the transmittance of photic zone 340 is 100%, its aligned in general is in the connection pad 202b top of a part, and the transmittance of part photic zone 340c is approximately between 20～80%, and its aligned in general is in other specific region.After implementing the second road photoetching process,, and after development of photoresist, then form the situation shown in Fig. 7 D by single exposure program.In the photoresist layer 320 that is formed at connection pad 202b top, be formed with an opening 310, exposed the ohmic contact layer 304 in it.Because the different factor of penetrability of zones of different, the photoresist layer 320 that is positioned at photic zone 340b below will be removed through developing fully because of exposing, and the photoresist floor 320 that is positioned at light tight district 340a and part photic zone 304c below will stay the photoresist floor 320 with different-thickness because of the exposure of not accepting exposure or only accept on the part degree after developing, the photoresist floor 320 that wherein is positioned at 340a below, light tight district has the thickness H1 that is about 15000～30000 dusts, and the photoresist layer 320 that is positioned at semi-opaque region 304c below then has the thickness H2 that is about 3000～15000 dusts.
Please refer to Fig. 7 E, then implement an etching program 350, for example use to comprise sulfur hexafluoride (SF
6), carbon tetrafluoride (CF
4) or the dry etch procedure (please replenish) of other appropriate reaction gas; by photoresist layer 320 as etch protection layer; etching remove the ohmic contact layer 304 that exposes in the opening 310, semiconductor layer 302 with gate insulation layer 300, and stop on the connection pad 202b.
Please refer to Fig. 7 F, then implement another etching program 360, for example use to comprise oxygen (O
2), sulfur hexafluoride and oxygen (SF
6/ O
2) or the dry etch procedure (please replenish) of other appropriate reaction gas, etch-back photoresist layer 320 exposes ohmic contact layer 304.At this moment, photoresist layer 320 only residues in the zone of gate electrode 202a top, and has covered a part of contiguous ohmic contact layer 304.
Please refer to Fig. 7 G, then implement another etching program 370, for example use to comprise chlorine (Cl
2), sulfur hexafluoride and chlorine (SF
6/ Cl
2), boron chloride and chlorine (BCl
3/ Cl
2), carbon tetrafluoride (CF
4) or the dry etch procedure (please replenish) of other reacting gas, with etching be not the ohmic contact layer 304 that covered of photoresist layer 320 with its under semiconductor layer 302, and stop on the gate insulation layer 300.And then stack architecture 360 and connection pad 202b shown in Fig. 7 B have been formed.Required twice photoetching process can be made structures such as the connection pad 202b that makes shown in Fig. 7 G and stack architecture 306 in the prior art of aforementioned Figure 1A～1F, the second road photoetching process used in the present invention, the use that it has saved one photomask has the effect of saving cost of manufacture and photoetching process.
Then carry out subsequent technique, the illustrated technology in Fig. 4～6 for example, form at last as shown in Figure 8 the transparency conducting layer that on substrate, is formed with a patterning 600,602 and 604 thin-film transistor display panel 700.Fig. 8 B and Fig. 8 C have then shown the section situation of 8B-8B and 8C-8C line segment in Fig. 8 A respectively, its cross-section structure cardinal principle be same as Fig. 6 B and Fig. 6 C.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (23)
1, a kind of manufacture method of array base palte comprises the following steps:
Form a first metal layer on a substrate;
Implement one first photoetching process with this first metal layer of patterning, form a grid lead, be linked to a gate electrode of this grid lead and a connection pad on this substrate;
Form an insulation course, semi-conductor layer and an ohmic contact layer on this substrate, be covered in this grid lead, this gate electrode and this connection pad; And
Implement one second photoetching process this insulation course with this ohmic contact layer of patterning, this semiconductor layer and part, form an interlayer hole in semiconductor structure and this insulation course on this connection pad in forming on this substrate, with this connection pad of exposed portions serve, wherein this semiconductor structure comprises this insulation course that is covered in substantially on this gate electrode, this semiconductor layer of patterning and this ohmic contact layer of patterning.
2, the manufacture method of array base palte as claimed in claim 1 also comprises the following steps:
Form one second metal level on this substrate, cover this semiconductor structure and insert this interlayer hole to be electrically connected on this connection pad; And
Implement one the 3rd photoetching process and be positioned at this ohmic contact layer and the semiconductor layer of a center section of this semiconductor structure, to define two source/drain regions and one second metal level on those source/drain regions and this connection pad with this second metal level of patterning and patterning.
3, the manufacture method of array base palte as claimed in claim 1, wherein this second photoetching process comprises the following steps:
Form a photoresist layer on this ohmic contact layer;
Implement a lithographic procedures, use has a light tight district, one photomask of one photic zone and a part of photic zone is with this photoresist layer of patterning, in substantially to forming an opening in should the photoresist layer of photic zone and exposing this ohmic contact layer of a part, in this photoresist floor in this light tight district of aligned in general, form the first photoresist floor of one first thickness, in this this semi-transparent photoresist layer of aligned in general, form the second photoresist layer of one second thickness, wherein this first thickness is greater than this second thickness, this this connection pad of photic zone aligned in general, this light tight district this gate electrode of aligned in general, and other outer zone of this this connection pad of part photic zone aligned in general and this gate electrode;
Implement etching program for the first time, adopting this first photoresist layer and this second photoresist layer is etching mask, this ohmic contact layer that the etching removal is exposed for this opening, with and under this semiconductor layer and this insulation course, and stop at this connection pad;
Implement etching program for the second time, this first photoresist layer of etching and this second photoresist layer, only stay this first photoresist layer that is covered in this gate electrode top substantially and thinning it, expose this ohmic contact layer that is not covered for this first photoresist layer;
Implement etching program for the third time, this ohmic contact layer that etching is not covered for this first photoresist layer and the semiconductor layer of below thereof; And
Remove this first photoresist layer, with this connection pad that forms semiconductor structure in this substrate and expose for this opening, wherein this semiconductor structure comprises this insulation course that is covered in substantially on this gate electrode, the semi-conductor layer of patterning and an ohmic contact layer of patterning.
4, the manufacture method of thin array base palte as claimed in claim 3, wherein this first thickness is between 15000～30000 dusts, and this second thickness is between the 3000-20000 dust.
5, the manufacture method of array base palte as claimed in claim 1, wherein this insulation course comprises silicon nitride or silicon oxynitride (SiO
XN
Y).
6, the manufacture method of array base palte as claimed in claim 1, wherein this semiconductor layer comprises α-Si:H material.
7, the manufacture method of array base palte as claimed in claim 1, wherein this ohmic contact layer comprises n
+α-Si:H material.
8, the manufacture method of array base palte as claimed in claim 3, wherein this first etching program is dry ecthing, uses to comprise sulfur hexafluoride (SF
6) or carbon tetrafluoride (CF
4) reacting gas.
9, the manufacture method of array base palte as claimed in claim 3, wherein this second etching program is dry ecthing, employed reacting gas comprises sulfur hexafluoride and oxygen (SF
6/ O
2) or oxygen (O
2).
10, the manufacture method of array base palte as claimed in claim 3, wherein the 3rd etching program is dry ecthing, employed reacting gas comprises chlorine (Cl
2), sulfur hexafluoride and chlorine (SF
6/ Cl
2), boron chloride and chlorine (BCl
3/ Cl
2) or carbon tetrafluoride (CF
4).
11, the manufacture method of array base palte as claimed in claim 3, wherein this part photic zone has the transmittance between 20～80%.
12, the manufacture method of array base palte as claimed in claim 3, wherein light tight district has and is roughly 0% transmittance and this photic zone has and is roughly 100% transmittance.
13, a kind of manufacture method of thin-film transistor display panel comprises the following steps:
Form a first metal layer on a substrate;
Implement one first photoetching process with this first metal layer of patterning, on this substrate, form and extend at least one grid lead continuously along first direction, and a plurality of data conductor fragments of extending along a second direction, wherein this first direction differs from this second direction and those data conductor fragments and those grid leads and is separation mutually in intersection;
Form an insulation course, semi-conductor layer and an ohmic contact layer on this substrate;
Implement one second photoetching process with this ohmic contact layer of patterning, this semiconductor layer and this insulation course, form a plurality of semiconductor structures and a plurality of stack architecture, those stack architectures across those data conductor fragments and those grid leads in intersection;
Form one second metal level on this substrate;
Implement one the 3rd photoetching process with this second conductive metal layer of patterning, in forming the many continuous data leads that a plurality of source/drain electrodes and formation extend on those bridging structures and is electrically connected those data conductor fragments on those semiconductor structures;
Form a protective seam on this substrate;
Implement one the 4th photoetching process with this protective seam of patterning, form a plurality of interlayer holes and exposed a plurality of connection pads of those data conductor and those grid leads and one of those source/drain electrodes; And
Form a transparency conducting layer on this substrate, and fill in those interlayer holes;
Implement one the 5th photoetching process with this transparency conducting layer of patterning, form a plurality of pixel electrodes and reservior capacitor, wherein those reservior capacitors partially overlap on those grid leads.
14, the manufacture method of thin-film transistor display panel as claimed in claim 13, wherein this second photoetching process comprises the following steps:
Form a photo anti-corrosion agent material on this ohmic contact layer;
Implement a lithographic procedures, use has a light tight district, one photomask of one photic zone and a part of photic zone is with this photo anti-corrosion agent material of patterning, in substantially to forming an opening in should the photoresist layer of photic zone and exposing this ohmic contact layer of a part, in this photoresist floor in this light tight district of aligned in general, form the first photoresist floor of one first thickness, in this this semi-transparent photoresist layer of aligned in general, form the second photoresist layer of one second thickness, wherein this first thickness is greater than this second thickness, one connection pad of these those grid leads of photic zone aligned in general and data conductor, this light tight district this gate electrode of aligned in general, and other outer zone of this this connection pad of part photic zone aligned in general and this gate electrode;
Implement etching program for the first time, adopting this first photoresist layer and this second photoresist layer is etching mask, this ohmic contact layer that the etching removal is exposed for this opening, with and under this semiconductor layer and this insulation course, and stop at this connection pad;
Implement etching program for the second time, this first photoresist layer of etching and this second photoresist layer, only stay this first photoresist layer that is covered in this gate electrode top substantially and thinning it, expose this ohmic contact layer that is not covered for this first photoresist layer;
Implement etching program for the third time, this ohmic contact layer that etching is not covered for this first photoresist layer and the semiconductor layer of below thereof; And
Remove this first photoresist layer, with this connection pad that forms semiconductor structure in this substrate and expose for this opening, wherein this semiconductor structure comprises this insulation course that is covered in substantially on this gate electrode, the semi-conductor layer of patterning and an ohmic contact layer of patterning.
15, the manufacture method of thin-film transistor display panel as claimed in claim 14, wherein this first thickness is between 15000～30000 dusts, and this second thickness is between 3000～20000 dusts.
16, the manufacture method of thin-film transistor display panel as claimed in claim 13, wherein this insulation course comprises silicon nitride or silicon oxynitride (SiO
XN
Y).
17, the manufacture method of thin-film transistor display panel as claimed in claim 13, wherein this semiconductor layer comprises α-Si:H material.
18, the manufacture method of thin-film transistor display panel as claimed in claim 13, wherein this ohmic contact layer comprises n
+α-Si:H material.
19, the manufacture method of thin-film transistor display panel as claimed in claim 14, wherein this first etching program is dry ecthing, employed reacting gas comprises sulfur hexafluoride (SF
6) or carbon tetrafluoride (CF
4).
20, the manufacture method of thin-film transistor display panel as claimed in claim 14, wherein this second etching program is dry ecthing, employed reacting gas comprises oxygen (O
2) or sulfur hexafluoride and oxygen (SF
6/ O
2).
21, the manufacture method of thin-film transistor display panel as claimed in claim 14, wherein the 3rd etching program is dry ecthing, employed reacting gas comprises chlorine (Cl
2), sulfur hexafluoride and chlorine (SF
6/ Cl
2) or boron chloride and chlorine (BCl
3/ Cl
2).
22, the manufacture method of thin-film transistor display panel as claimed in claim 14, wherein this part photic zone has the transmittance between 20～80%.
23, the manufacture method of thin-film transistor display panel as claimed in claim 14, wherein light tight district has and is roughly 0% transmittance and this photic zone has and is roughly 100% transmittance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100669346A CN100399134C (en) | 2005-04-22 | 2005-04-22 | Method of manufacturing array substrate and thin film transistor array panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100669346A CN100399134C (en) | 2005-04-22 | 2005-04-22 | Method of manufacturing array substrate and thin film transistor array panel |
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| Publication Number | Publication Date |
|---|---|
| CN1664685A true CN1664685A (en) | 2005-09-07 |
| CN100399134C CN100399134C (en) | 2008-07-02 |
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ID=35035837
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|---|---|---|---|
| CNB2005100669346A Active CN100399134C (en) | 2005-04-22 | 2005-04-22 | Method of manufacturing array substrate and thin film transistor array panel |
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| Country | Link |
|---|---|
| CN (1) | CN100399134C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446222C (en) * | 2007-03-28 | 2008-12-24 | 友达光电股份有限公司 | Production of thin-film transistor base plate |
| CN1988077B (en) * | 2005-12-25 | 2011-08-03 | 群康科技(深圳)有限公司 | Method for producing capacitor |
| WO2016008182A1 (en) * | 2014-07-18 | 2016-01-21 | 深圳市华星光电技术有限公司 | Mask, array substrate manufacturing method, and array substrate |
| CN106252357A (en) * | 2016-08-24 | 2016-12-21 | 武汉华星光电技术有限公司 | Low-temperature polysilicon film transistor array base palte and preparation method thereof, liquid crystal panel |
| CN107643657A (en) * | 2017-10-31 | 2018-01-30 | 武汉华星光电技术有限公司 | A kind of method and light shield for improving panel periphery TITO residuals |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6255130B1 (en) * | 1998-11-19 | 2001-07-03 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and a method for manufacturing the same |
| TW413949B (en) * | 1998-12-12 | 2000-12-01 | Samsung Electronics Co Ltd | Thin film transistor array panels for liquid crystal displays and methods of manufacturing the same |
| JP2002141512A (en) * | 2000-11-06 | 2002-05-17 | Advanced Display Inc | Patterning method of thin film, tft array substrate using the patterning method, and manufacturing method of the tft array substrate |
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2005
- 2005-04-22 CN CNB2005100669346A patent/CN100399134C/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1988077B (en) * | 2005-12-25 | 2011-08-03 | 群康科技(深圳)有限公司 | Method for producing capacitor |
| CN100446222C (en) * | 2007-03-28 | 2008-12-24 | 友达光电股份有限公司 | Production of thin-film transistor base plate |
| WO2016008182A1 (en) * | 2014-07-18 | 2016-01-21 | 深圳市华星光电技术有限公司 | Mask, array substrate manufacturing method, and array substrate |
| US9842865B2 (en) | 2014-07-18 | 2017-12-12 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Mask plate, method of manufacturing array substrate, and array substrate |
| CN106252357A (en) * | 2016-08-24 | 2016-12-21 | 武汉华星光电技术有限公司 | Low-temperature polysilicon film transistor array base palte and preparation method thereof, liquid crystal panel |
| CN106252357B (en) * | 2016-08-24 | 2019-05-21 | 武汉华星光电技术有限公司 | Low-temperature polysilicon film transistor array substrate and preparation method thereof, liquid crystal display panel |
| CN107643657A (en) * | 2017-10-31 | 2018-01-30 | 武汉华星光电技术有限公司 | A kind of method and light shield for improving panel periphery TITO residuals |
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| Publication number | Publication date |
|---|---|
| CN100399134C (en) | 2008-07-02 |
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