CN106252357A - Low-temperature polysilicon film transistor array base palte and preparation method thereof, liquid crystal panel - Google Patents
Low-temperature polysilicon film transistor array base palte and preparation method thereof, liquid crystal panel Download PDFInfo
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- CN106252357A CN106252357A CN201610717764.1A CN201610717764A CN106252357A CN 106252357 A CN106252357 A CN 106252357A CN 201610717764 A CN201610717764 A CN 201610717764A CN 106252357 A CN106252357 A CN 106252357A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The invention discloses a kind of low-temperature polysilicon film transistor array base palte, including: substrate, the display part being arranged on substrate and the non-display portion extended by the edge of display part, display part includes multiple low-temperature polysilicon film transistors of array arrangement, and non-display portion includes: the complex metal layer on substrate；The first metal layer on complex metal layer；The first metal layer is by oxide water soluble and has the metal material of low-resistance value and makes；Flatness layer on the first metal layer；Through hole in flatness layer；Part the first metal layer is exposed by through hole；Common electrode layer on flatness layer；Common electrode layer contacts with the first metal layer of exposure via through hole；Cover the passivation layer of common electrode layer.Owing to using oxide water soluble and easy removed metal material to make the first metal layer, therefore the contact condition of the holding wire (it is made up of) below flatness layer and common electrode layer can be effectively improved complex metal layer and the first metal layer, with improving product quality.
Description
Technical field
The invention belongs to technical field of liquid crystal display, specifically, relate to a kind of low-temperature polysilicon film transistor array
Substrate and preparation method thereof, liquid crystal panel.
Background technology
Along with the evolution of photoelectricity Yu semiconductor technology, also drive the fluffy of flat faced display (Flat Panel Display)
The exhibition of breaking out, and in many flat faced displays, liquid crystal display (Liquid Crystal Display is called for short LCD) is because having
Many advantageous characteristic such as high spatial utilization ratio, low consumpting power, radiationless and low EMI, it has also become the master in market
Stream.
At present, widely used as the switch element of LCD is amorphous silicon membrane audion (a-Si TFT), but a-Si
TFT LCD requires still to be restricted meeting slim, light weight, high-fineness, high brightness, high reliability, low-power consumption etc..Low temperature is many
Compared with crystal silicon (Lower Temperature Polycrystal Silicon, LTPS) TFT LCD and a-Si TFT LCD,
Meet above-mentioned requirements aspect, there is clear superiority.
But, in the manufacturing process of existing LTPS array base palte, public voltage signal is by LTPS array base palte
Viewing area (i.e. AA district) periphery flatness layer (PLN) in via be sent to public electrode, and below the flatness layer of periphery
Holding wire formed by composite metal structures (such as Ti/Al/Ti structure), but Ti (titanium) metal at processing environment and
Rear processing procedure (such as baking) environment easily aoxidizes, thus forms TiOx, and TiOxResistance value is higher and is difficult to remove, and easily causes
Public voltage signal input is abnormal, thus causes product display characteristic the best.
Summary of the invention
In order to solve above-mentioned technical problem, it is an object of the invention to provide a kind of low-temperature polysilicon film transistor battle array
Row substrate, including: substrate, arrange display part on the substrate and by the edge of described display part extend non-display
Portion, described display part includes multiple low-temperature polysilicon film transistors of array arrangement, and described non-display portion includes: on substrate
Complex metal layer；The first metal layer on described complex metal layer；Wherein, described the first metal layer is dissolved in by oxide
Water and there is the metal material of low-resistance value make；Flatness layer on described the first metal layer；Leading in described flatness layer
Hole；Wherein, described for part the first metal layer is exposed by described through hole；Common electrode layer on described flatness layer；Wherein, described
Common electrode layer contacts with the described the first metal layer of exposure via described through hole；Cover the passivation layer of described common electrode layer.
Further, described the first metal layer uses molybdenum to make.
Further, described complex metal layer includes: set gradually the second metal level on the substrate, the 3rd metal
Layer and the 4th metal level, described the first metal layer is arranged on described 4th metal level.
Further, described second metal level and described 4th metal level use titanium to make, and described 3rd metal level uses
Aluminum is made.
Further, the common electrode layer on described flatness layer extends to the bottom of described through hole, thus covers cruelly
On the described the first metal layer of dew.
Another object of the present invention also resides in the manufacture method providing a kind of low-temperature polysilicon film transistor array base palte,
Described manufacture method includes: form display part and the non-display portion extended by the edge of described display part on substrate；Described
The concrete manufacture method of display part includes: form multiple low-temperature polysilicon film transistors of array arrangement on substrate, described
The concrete manufacture method of non-display portion includes: form complex metal layer on substrate；Described complex metal layer is formed first
Metal level；Wherein, described the first metal layer by oxide water soluble and has the metal material of low-resistance value and makes；Described
Flatness layer is formed on the first metal layer；Through hole is formed in described flatness layer；Wherein, described through hole is by described for part the first metal
Layer exposes；Described flatness layer is formed common electrode layer；Wherein, described common electrode layer is via the institute of described through hole Yu exposure
State the first metal layer contact；Form the passivation layer covering described common electrode layer.
Further, described complex metal layer utilize Mo form described the first metal layer.
Further, the concrete grammar forming described complex metal layer on substrate includes: utilize titanium on the substrate
Material forms the second metal level；Described second metal level utilize aluminum form the 3rd metal level；At described 3rd metal
Titanium material is utilized to form the 4th metal level on Ceng；Wherein, described the first metal layer is formed on described 4th metal level.
Further, the concrete side that described common electrode layer contacts with the described the first metal layer of exposure via described through hole
Method is: make the common electrode layer on described flatness layer extend to the bottom of described through hole, thus covers described the exposed
On one metal level.
A further object of the present invention is again to provide a kind of liquid crystal panel, many including color membrane substrates and the low temperature arranging box
Polycrystal silicon film transistor (TFT) array substrate, described low-temperature polysilicon film transistor array base palte is above-mentioned low-temperature polysilicon film
Transistor (TFT) array substrate, or utilize above-mentioned manufacture method to make described low-temperature polysilicon film transistor array base palte.
Beneficial effects of the present invention: owing to using oxide water soluble and easy removed the first metal layer and common electrical
Pole layer contact, therefore can be effectively improved the holding wire (it is made up of) below flatness layer complex metal layer and the first metal layer with public
The contact condition of common electrode layer, thus improving product quality.
Accompanying drawing explanation
By combining the following description that accompanying drawing is carried out, above and other aspect, feature and the advantage of embodiments of the invention
Will become clearer from, in accompanying drawing:
Fig. 1 is the top view of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention；
Fig. 2 is that the A-A in Fig. 1 is to profile；
Fig. 3 shows the flow chart of the manufacture method of non-display portion according to an embodiment of the invention；
Fig. 4 is the structural representation of liquid crystal panel according to an embodiment of the invention.
Detailed description of the invention
Hereinafter, with reference to the accompanying drawings to describe embodiments of the invention in detail.However, it is possible to come real in many different forms
Execute the present invention, and the present invention should not be construed as limited to the specific embodiment that illustrates here.On the contrary, it is provided that these are implemented
Example is to explain the principle of the present invention and actual application thereof, so that others skilled in the art are it will be appreciated that the present invention
Various embodiments and be suitable for the various amendments of specific intended application.In the accompanying drawings, identical label will be used for table all the time
Show identical element.
Fig. 1 is the top view of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention.Fig. 2 is figure
A-A in 1 is to profile.
Seeing figures.1.and.2, low-temperature polysilicon film transistor array base palte includes according to an embodiment of the invention: base
Plate 100, arrange display part on the substrate 100 (or claiming viewing area) 200 and by the edge of display part 200 extend non-display
Portion's (or claiming non-display area) 300.
Specifically, substrate 100 can be transparent glass substrate or resin substrate.Display part 200 and non-display portion
300 are arranged on the same surface of substrate 100.During the processing procedure of low-temperature polysilicon film transistor array base palte, display
Portion 200 and non-display portion 300 are concurrently formed on the same surface of substrate 100.Generally, display part 200 includes array arrangement
Multiple low-temperature polysilicon film transistors 210.Certainly, it should be noted that display part 200 can also include be crisscross arranged
Data wire and gate line and the element of other necessity.
Hereinafter non-display portion 300 will be described in detail.With continued reference to Fig. 1 and Fig. 2, non-display portion 300 includes: multiple
Metal layer 310, the first metal layer 320, flatness layer 330, common electrode layer 340 and passivation layer 350.
Complex metal layer 310 is arranged on the substrate 100；Wherein, complex metal layer 310 is many with the low temperature in display part 200
The gate electrode of polycrystal silicon film transistor 210 concurrently forms.Further, complex metal layer 310 includes: be successively set on substrate
The second metal level the 311, the 3rd metal level 312 and the 4th metal level 313 on 100.In this embodiment, it is preferred that, the second gold medal
Belong to layer 311 and the 4th metal level 313 is made up of titanium (Ti), and the 3rd metal level 312 is made up of aluminum (Al).So, composition metal
Layer 310 has Ti/Al/Ti metal structure.
The first metal layer 320 is arranged on complex metal layer 310；Wherein, the first metal layer 320 is concurrently formed at display part
On the gate electrode of the low-temperature polysilicon film transistor 210 in 200.In other words, in display part 200, can be by the first gold medal
Belong to layer 320 and constitute gate electrode with complex metal layer 310 combination.In the present embodiment, the first metal layer 320 is dissolved in by oxide
Water and there is the metal material of low-resistance value make.Preferably, the first metal layer 320 is made up of Mo.
Flatness layer 330 is arranged on the first metal layer 320.Through hole 331, wherein, this through hole is formed in flatness layer 330
Part the first metal layer 320 is exposed by 331.
Common electrode layer 340 is arranged on flatness layer 330；Wherein, common electrode layer 340 is via through hole 331 and exposure
The first metal layer 320 contacts.Further, the common electrode layer 340 on flatness layer 330 extends to the bottom of through hole 330, from
And cover on the first metal layer 320 exposed, to contact with the first metal layer 320 exposed.
Passivation layer 350 is arranged in common electrode layer 340, so that common electrode layer 340 is completely covered.
Due to the oxide M oOx water soluble of molybdenum and easily it is removed, therefore can be effectively improved the holding wire below flatness layer
The contact condition of (it is made up of complex metal layer and the first metal layer) and common electrode layer, thus improving product quality.
The manufacture method of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention will be entered below
Row explanation.With reference to Fig. 1, first, it is provided that a substrate 100.Then, display part 200 is formed on the substrate 100 and by display part
The non-display portion (or claiming non-display area) 300 that the edge of 200 extends.
The concrete manufacture method of display part 200 is: form multiple low-temperature polysilicon films of array arrangement on the substrate 100
Transistor 210.The manufacture method of each low-temperature polysilicon film transistor 210 uses the low-temperature polysilicon film crystalline substance of prior art
The manufacture method of body pipe, does not repeats them here.
The manufacture method of non-display portion 300 according to an embodiment of the invention will be described in detail below.Fig. 3 illustrates
The flow chart of the manufacture method of non-display portion according to an embodiment of the invention.
With reference to Fig. 2 and Fig. 3, in step S310, form complex metal layer 310 on the substrate 100.Here compound golden
Genus layer 310 concurrently forms with the gate electrode of the low-temperature polysilicon film transistor 210 in display part 200.
Further, the manufacture method of complex metal layer 310 specifically includes: utilize titanium to form the second gold medal on the substrate 100
Belong to layer 311；Second metal level 311 utilize aluminum form the 3rd metal level 312；And utilize titanium on the 3rd metal level 312
Form the 4th metal level 313.So, complex metal layer 310 has Ti/Al/Ti metal structure.
In step s 320, complex metal layer 310 forms the first metal layer 320.Wherein, the first metal layer 320 is same
Time be formed on the gate electrode of the low-temperature polysilicon film transistor 210 in display part 200.In other words, at display part 200
In, gate electrode can be constituted by the first metal layer 320 with complex metal layer 310 combination.In the present embodiment, the first metal layer
320 by oxide water soluble and have the metal material of low-resistance value and make.Preferably, the first metal layer 320 is by Mo
Make.
In step S330, the first metal layer 320 forms flatness layer 330.Here, shape on the first metal layer 320
While becoming flatness layer 330, display part 200 also forms flatness layer 330.
In step S340, flatness layer 330 forms through hole 331；Wherein, this through hole 331 is by part the first metal layer
320 expose.
In step S350, flatness layer 330 forms common electrode layer 340；Wherein, common electrode layer 340 is via logical
Hole 331 contacts with the first metal layer 320 exposed.Here, while flatness layer 330 forms common electrode layer 340, aobvious
Show and portion 200 is also formed common electrode layer 340.
Further, the concrete grammar that common electrode layer 340 contacts with the first metal layer 320 exposed via through hole 331
For: make the common electrode layer 340 on flatness layer 330 extend to the bottom of through hole 330, thus cover at the first metal exposed
On layer 320, to contact with the first metal layer 320 exposed.
In step S360, forming passivation layer 350 in common electrode layer 340, described passivation layer 350 is completely covered public
Electrode layer 340.Here, while common electrode layer 340 forms passivation layer 350, display part 200 also forms passivation layer
350。
Fig. 4 is the structural representation of liquid crystal panel according to an embodiment of the invention.
With reference to Fig. 4, liquid crystal panel includes according to an embodiment of the invention: the low-temperature polysilicon film crystal arranging box
Pipe array base palte 1000 and color membrane substrates 2000, and it is located in low-temperature polysilicon film transistor array base palte 1000 and color film
Liquid crystal layer 3000 between substrate 2000, has some liquid crystal molecules, wherein, low-temperature polysilicon film crystal in liquid crystal layer 3000
Pipe array base palte 1000 is the low-temperature polysilicon film transistor array base palte shown in Fig. 1 and Fig. 2, or, low temperature polycrystalline silicon is thin
Film transistor array base palte 1000 is the low-temperature polysilicon film transistor array base palte using above-mentioned manufacture method to make.This
Outward, color membrane substrates 2000 generally include be made up of red (R) optical filter, green (G) optical filter, indigo plant (B) optical filter colored filter,
Black matrix", alignment film etc..The structure of color membrane substrates refer to the prior art being correlated with in further detail, repeats no more here.
Although illustrate and describing the present invention with reference to specific embodiment, but it should be appreciated by those skilled in the art that:
In the case of without departing from the spirit and scope of the present invention limited by claim and equivalent thereof, can carry out at this form and
Various changes in details.
Claims (10)
1. a low-temperature polysilicon film transistor array base palte, including: substrate, arrange display part on the substrate and
The non-display portion extended by the edge of described display part, described display part includes that multiple low-temperature polysilicon films of array arrangement are brilliant
Body pipe, it is characterised in that described non-display portion includes:
Complex metal layer on substrate；
The first metal layer on described complex metal layer；Wherein, described the first metal layer by oxide water soluble and has
The metal material of low-resistance value is made；
Flatness layer on described the first metal layer；
Through hole in described flatness layer；Wherein, described for part the first metal layer is exposed by described through hole；
Common electrode layer on described flatness layer；Wherein, described common electrode layer is via described the of described through hole and exposure
One metal level contact；
Cover the passivation layer of described common electrode layer.
Low-temperature polysilicon film transistor array base palte the most according to claim 1, it is characterised in that described first metal
Layer uses molybdenum to make.
Low-temperature polysilicon film transistor array base palte the most according to claim 1 and 2, it is characterised in that described compound
Metal level includes: set gradually the second metal level on the substrate, the 3rd metal level and the 4th metal level, described first gold medal
Belong to layer to be arranged on described 4th metal level.
Low-temperature polysilicon film transistor array base palte the most according to claim 3, it is characterised in that described second metal
Layer and described 4th metal level use titanium to make, and described 3rd metal level is adopted and is formed from aluminium.
Low-temperature polysilicon film transistor array base palte the most according to claim 1, it is characterised in that at described flatness layer
On common electrode layer extend to the bottom of described through hole, thus cover on the described the first metal layer exposed.
6. a manufacture method for low-temperature polysilicon film transistor array base palte, described manufacture method includes: shape on substrate
Become display part and the non-display portion extended by the edge of described display part；
The concrete manufacture method of described display part includes: form multiple low-temperature polysilicon film crystal of array arrangement on substrate
Pipe, it is characterised in that the concrete manufacture method of described non-display portion includes:
Substrate is formed complex metal layer；
Described complex metal layer is formed the first metal layer；Wherein, described the first metal layer is by oxide water soluble and tool
The metal material having low-resistance value is made；
Described the first metal layer is formed flatness layer；
Through hole is formed in described flatness layer；Wherein, described for part the first metal layer is exposed by described through hole；
Described flatness layer is formed common electrode layer；Wherein, described common electrode layer is via described in described through hole and exposure
The first metal layer contacts；
Form the passivation layer covering described common electrode layer.
The manufacture method of low-temperature polysilicon film transistor array base palte the most according to claim 6, it is characterised in that
Mo is utilized to form described the first metal layer on described complex metal layer.
8., according to the manufacture method of the low-temperature polysilicon film transistor array base palte described in claim 6 or 7, its feature exists
In, the concrete grammar forming described complex metal layer on substrate includes:
Titanium material is utilized to form the second metal level on the substrate；
Described second metal level utilize aluminum form the 3rd metal level；
Described 3rd metal level utilize titanium material form the 4th metal level；Wherein, described the first metal layer is formed at described
On 4th metal level.
The manufacture method of low-temperature polysilicon film transistor array base palte the most according to claim 6, it is characterised in that institute
State what common electrode layer contacted with the described the first metal layer of exposure via described through hole method particularly includes: make at described flatness layer
On common electrode layer extend to the bottom of described through hole, thus cover on the described the first metal layer exposed.
10. a liquid crystal panel, including the color membrane substrates arranging box and low-temperature polysilicon film transistor array base palte, it is special
Levying and be, described low-temperature polysilicon film transistor array base palte is that the low temperature polycrystalline silicon described in any one of claim 1 to 5 is thin
Film transistor array base palte, or it is thin to utilize the manufacture method described in any one of claim 6 to 9 to make described low temperature polycrystalline silicon
Film transistor array base palte.
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| CN1664685A (en) * | 2005-04-22 | 2005-09-07 | 友达光电股份有限公司 | Method of manufacturing array substrate and thin film transistor array panel |
| CN101728421A (en) * | 2008-10-29 | 2010-06-09 | 索尼株式会社 | Organic el display and method of manufacturing the same |
| CN102147549A (en) * | 2010-02-10 | 2011-08-10 | 索尼公司 | Liquid crystal display panel and electronic apparatus |
| CN103258968A (en) * | 2013-04-28 | 2013-08-21 | 昆山工研院新型平板显示技术中心有限公司 | Active organic light-emitting diode (OLED) display device and manufacturing method thereof |
| CN104143563A (en) * | 2013-05-10 | 2014-11-12 | 三星显示有限公司 | Manufacturing method of metal wire and thin transistor array panel, and organic light emitting display |
| CN105097825A (en) * | 2014-05-07 | 2015-11-25 | 群创光电股份有限公司 | Display device |
| CN104752439A (en) * | 2015-01-05 | 2015-07-01 | 上海天马有机发光显示技术有限公司 | Array substrate, display device and array substrate manufacturing method |
| CN104867904A (en) * | 2015-04-03 | 2015-08-26 | 京东方科技集团股份有限公司 | Conductive structure and manufacturing method thereof, array substrate and display device |
| CN105629613A (en) * | 2016-03-17 | 2016-06-01 | 深圳市华星光电技术有限公司 | Manufacturing method for signal line of display panel |
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