CN1661727A - Multi level flash memory device and program method - Google Patents
Multi level flash memory device and program method Download PDFInfo
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- CN1661727A CN1661727A CN 200510052527 CN200510052527A CN1661727A CN 1661727 A CN1661727 A CN 1661727A CN 200510052527 CN200510052527 CN 200510052527 CN 200510052527 A CN200510052527 A CN 200510052527A CN 1661727 A CN1661727 A CN 1661727A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
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Abstract
Provided is a multi level flash memory device and a program method. This device is the flash memory device provided with a plurality of memory cells in which each cell stores an amount of charges indicating two possible states or more and a control circuit coupled to the memory cells. In the control circuit, programming voltage and verification voltage are applied alternately to the memory cells until all memory cells reach a desired state. Also, the method is provided with a step in which at least one programming pulse is applied to the memory cell, a step in which it is verified whether each memory cell reaches the desired state or not, a step in which the memory cell programmed at the highest state is selected. and a step in which at least one additional programming pulse is applied to the selected memory cell without further verifying a state of the selected memory cell. The program method characterized by providing above steps.
Description
Technical field
The present invention relates to a kind of memory device and programmed method, especially relate to a kind of multi level flash memory device and programmed method.
Background technology
Modem computer systems often comprises the Nonvolatile semiconductor memory device that is used for data storage.Popular Nonvolatile semiconductor memory device type is a flash memory device.With reference to figure 1, flash memory device comprises the array 100 of flash cell 10.Each flash cell can be, for example field effect transistor (FET).Described flash cell 10 has grid 11, floating grid 21, source electrode 31 and drain electrode drain electrode 41.Grid 11 is in response to word line, for example word line W/L0, W/L1 ..., W/L1023 and operating.Source electrode 31 is connected to sense wire S/L.Drain electrode is 41 in response to corresponding bit lines, for example bit line B/L0, B/L1 ..., B/L511 and operating.
By via for example W/L0, W/L1 ..., W/L102 word line to grid 11 apply variation voltage and with threshold voltage vt, drain current Id and/or be stored in electric charge in the floating grid 21 and reference memory unit compare to described flash cell 10 programme, verification and reading.Programming relates to by change and is stored in the electric charge in the floating grid 21 and program voltage is applied to grid 11 with data programing or store in the cell array 100, and the change of described electric charge causes the respective change of threshold voltage vt, drain current Id and/or stored charge.Verification determines that 100 programmings of successful array are also usually after programming.Read and relate to sense data from programming unit array 100.
Flash cell can be stored single or multiple data bit.With reference to figure 2A, the unit flash cell can have state 1 and state 0, indicates logic high and low respectively.State 1 is the bell deltoid by threshold voltage V1 and V2 definition, and wherein most of storage unit that are programmed into state 1 will demonstrate the threshold voltage between V1 and V2.Similarly, state 0 is the bell deltoid by threshold voltage V3 and V4 definition, and wherein most of storage unit that are programmed into state 0 will demonstrate the threshold voltage between V3 and V4.Zone between state 1 and 0 is called as separate domains (separation range).Reference voltage Vref is usually located in the separate domains between state 0 and the state 1.Separate domains is unwanted in theory, but is used for distinguishing between the state of for example state 1 and 0.
With reference to figure 2B, different with single position storage unit, multi-bit memory cell comprises a plurality of states, and for example state 11,10,01 and 00.The flash cell of storage multidata position is expected, because they have reduced position cost (bit cost) in large quantities.For example, if realize 4 data states or level on individual unit, then density of memory cells can double and not have subsidiary attenuation to increase.
Multi-bit memory cell requires accurate threshold voltage control.Usually, higher calibration voltage causes in the narrow relatively distributions at calibration voltage place and wide separate domains.But when with after-applied low read-out voltage, the result that the gm that changes as storage unit distributes, distributions is widened, the separate domains constriction.This will increase the possibility of readout error, that is, the unit of programming, verification goes out it and is in correct state, reads it subsequently and draws the conclusion that it is in a different state.
Therefore, need a kind of improved multi level flash memory device and programmed method.
Summary of the invention
The objective of the invention is to overcome the shortcoming relevant with programmed method with the prior art multi level flash memory device.
One embodiment of the present of invention are a kind of non-volatile memory devices, comprise a plurality of storage unit, and each storage indication is more than the quantity of electric charge of two kinds of possibility states; With the control circuit that is connected to storage unit.Control circuit alternately is applied to storage unit with programming pulse and calibration voltage, is in the state of expectation up to all unit.And control circuit program pulse application that at least one is extra is to the unit that is in the high state, and do not apply calibration voltage.
Control circuit can also be applied to the unit with the read-out voltage that equates with calibration voltage.
This equipment can comprise in response to extra programming pulse and increases, reads tolerance limit between the highest location mode and the highest next location mode.
This control circuit can alternately apply programming pulse and calibration voltage, till this control circuit applies at least one extra programming pulse.
An alternative embodiment of the invention is a kind of method that is used for a plurality of storage unit are programmed into expectation state, and each unit has the possible state more than two.This method comprises and applies at least one programming pulse and reached expectation state to described unit and each unit of verification.And this method comprises the unit of selecting to be programmed into high state and applies at least one extra programming pulse to selected unit, and the further state of these unit of verification not.
This method can comprise and apply calibration voltage to the unit, and applies the read-out voltage that equals calibration voltage with sense data from programmed cells.
This method can comprise and apply at least one extra programming pulse to selected unit, and the further state of these unit of verification not, thereby enlarged the tolerance limit of reading between high state and next high state.
This method can comprise that applying at least one programming pulse reached expectation to unit and each unit of verification state hockets, up to applying extra programming pulse.
Description of drawings
From below in conjunction with accompanying drawing to the invention detailed description, it is more obvious that above and other objects of the present invention, feature and advantage will become.
Fig. 1 is the synoptic diagram of memory cell array 100.
Fig. 2 A-B is the state of memory cells figure of unit and multi-bit memory cell.
Fig. 3 is the process flow diagram of the programmed method relevant with multi-bit memory cell.
Fig. 4 is used for and the W/L voltage of relevant various verification with multi-bit memory cell shown in Fig. 2 B and the programming operation synoptic diagram to the time.
Fig. 5 is the synoptic diagram of the cell current pair threshold voltage relevant with Fig. 4.
Fig. 6 is the state of memory cells figure of multi-bit memory cell.
Fig. 7 is the synoptic diagram of the cell current pair threshold voltage relevant with Fig. 6.
Fig. 8 is the state of memory cells figure of multi-bit memory cell
Fig. 9 is the synoptic diagram of multistage memory device according to an embodiment of the invention.
Figure 10 is the state of memory cells figure of multi-bit memory cell according to an embodiment of the invention.
Figure 11 is the state of memory cells figure of multi-bit memory cell according to an embodiment of the invention.
Figure 12 is the process flow diagram of method according to an embodiment of the invention.
Figure 13 is used for the synoptic diagram of the W/L voltage of various verification relevant with multi-bit memory cell shown in Figure 10 and programming operation to the time.
Embodiment
Fig. 3 is the process flow diagram of the programmed method 300 relevant with multi-bit memory cell.With reference to figure 1 and Fig. 3, method 300 is included in 302 and receives program command and data, and the indication memory device is with data programing or store memory cell array 100 into.In response to this program command programmed word line voltage W/L is applied to grid 11, it has changed the electric charge that is stored in the floating grid 21 according to described data.304, by on grid 11, applying fixing calibration voltage and threshold voltage vt, drain current Id and/or the electric charge and the reference memory unit that are stored in the floating grid 21 being compared the programming of method 300 verification succeeds.
If in the failure of 306 verification operation, then method 300 improves programmed word line voltage W/L 308, receives program command and data 310, and in the 304 unit programmings that verification is correct once more.The electric charge that is stored in the floating grid 21 increases along with applying of programming W/L voltage at every turn.That is to say that the electric charge that is stored in the floating grid 21 is proportional with amplitude, duration and the number of programming W/L voltage application.Method is in 304,306,308 and 310 cocycles, up to method 300 after the device programming in verification succeeds 312 finish till.In method 300, verification (304) in programming (302 and 310) afterwards.
Fig. 4 is the synoptic diagram of W/L voltage to the time.With reference to figure 1 and Fig. 4, use programming W/L voltage that storage unit 10 is programmed, programming W/L uses verification W/L voltage to carry out verification then.Programming W/L voltage increases along with state.That is to say that when programming unit 10 during to state 00, programming W/L voltage is minimum, and programming unit 10 is to state 10,01 with progressively increased at 00 o'clock.On the other hand, verification W/L voltage keeps identical level for example to come verification state 11,10,01 and 00 by the electric current of unit with basis.Please note necessary each state of verification, comprise 00.
Fig. 5 is unit or the drain current synoptic diagram to threshold voltage.With reference to figure 1 and Fig. 3 to 5, method 300 is by alternately applying progressively the programming W/L voltage that increases and verification W/L voltage to the unit of selecting and concomitantly to a plurality of unit verification W/L voltage of programming.After the unit is by verification, i.e. this unit programming is identified, and it is cancelled selected.Verification W/L voltage must be higher than read-out voltage, because must verification high state 00.This requirement is higher than the verification W/L voltage of the high threshold voltage in 00 state.
Fig. 6 is the synoptic diagram of distributions to cell current, comprises three unit A, the B and the C that all have cell current Ia.Fig. 7 is the synoptic diagram of the cell current of unit A, B and C to W/L voltage.Fig. 8 is the synoptic diagram of distributions to cell threshold voltage.With reference to figure 6 to 8, different units, for example unit A, B can have identical cell current Ia with C for same verification W/L voltage.But because reading W/L voltage is usually less than verification W/L voltage, so because the sensing element electric current of change unit A, B that unit gm distributes and C is lower.This difference causes of-state voltage territory (state voltage range) to be widened, the separate domains constriction between each of-state voltage territory, as shown in Figure 8.Therefore, the read W/L voltage lower with respect to verification W/L voltage has reduced the accuracy of reading usually.
Fig. 9 is the synoptic diagram of multistage memory device according to an embodiment of the invention.Multistage memory device 900 comprises the array 100 of flash cell 100.Each flash cell can be a field effect transistor (FET) for example.Flash cell 10 has grid 11, floating grid 21, source electrode 31 and drains 41.Source electrode 31 is connected to sense wire S/L.Drain electrode is 41 in response to corresponding bit line, for example bit line B/L0, B/L1 ..., B/L511 and operating.Grid 11 is in response to word line, for example word line W/L0, W/L1 ..., W/L1023 and operating.Word line W/L 0, W/L1 ..., W/L1023 is connected to control circuit 50.Control circuit 50 as explaining in detail in the back, produce and provide voltage signal or pulse to word line W/L0, W/L1 ..., W/L1023.Control circuit 50 can be realized by software, hardware or by any mode well known by persons skilled in the art.
Figure 10 and 11 is the synoptic diagram in of-state voltage territory according to an embodiment of the invention.Embodiments of the invention comprise making in fact to be read W/L voltage and equals verification W/L voltage, shown in Figure 10 and 11.The voltage status territory of having done constriction like this and having widened between state 11 and 00 and the separate domains between state 10 and 01 has been improved and has been read accuracy.But equate owing to read, if therefore not further operation then has very little read-out voltage tolerance limit (margin), as shown in figure 10 between state 01 and 00 with calibration voltage.
In Figure 11, when reading with verification W/L voltage when substantially the same, state 11,10,01 and 00 is shown as narrow bell deltoid at condition curve, between the corresponding condition curve wide separate domains is arranged.This equal state shaped form that shows with Fig. 8 in pairs than, different read and verification W/L voltage causes the condition curve of broad and between corresponding condition curve narrower separate domains arranged reduced and read accuracy among Fig. 8.
Equate to reduce read-out voltage tolerance limit between state 01 and 00 but make to read with verification W/L voltage, as shown in figure 10, because read/verification W/L is just on the required threshold voltage of the transistor in conducting state 00.Recalling state 00 is read out by inference.That is to say, be not at state 11,10 or 01 when the unit is read as when (therefore detecting does not have electric current to flow into correlation unit), infer state 00.
In order to improve the read-out voltage tolerance limit between state 01 and 00, keep the equal voltage of reading simultaneously with verification W/L, embodiments of the invention comprise memory cells, and stay out of verification operation, explain with reference to figure 12 as following.Do has like this increased the electric charge that is stored in the storage grid 21 proportionally, and stays out of verification operation.Increase the electric charge be stored in the storage grid 21 and state 00 curve is displaced to reads/the right of verification W/L voltage as shown in figure 11, with the verification that equates with read W/L voltage and increased and read tolerance limit and go out tolerance limit and improved simultaneously and read accuracy.
Figure 12 is the process flow diagram of the method according to this invention.With reference to Figure 12, method 1100 comprises by sign setting and circulation routine 1102 and 1104 method 300 (Fig. 3) routines of revising (routine).After 302 programmings, method 1100 execute flags are provided with routine 1102.Method determines whether storage unit comprises that state is 00 data (1106).If the unit is in state 00, then method 1100 is provided with sign 1108.If method 1100 goes out unit program in 306 verifications, then it carries out circulation routine 1104.Whether method 1100 is set to 1 at 1110 checkmarks.If be set to 1, then method 1100 finishes 312.If 1110 sign (for example, because the unit is not programmed at state 00) is not set, then it is set to 0 1112 with counter.Method 1100 improves the W/L voltages 1114, at 1116 programming units, and increases by 1 at 1120 pairs of countings, reaches predetermined (perhaps able to programme) boundary up to counting, and for example 10 (1118).In case counting reaches predetermined threshold 1118, then program finishes 312.By carrying out circulation routine 1104, method 1100 as shown in figure 11 and as explained above effectively with state 00 voltage domain right shift.Figure 13 is the synoptic diagram of W/L voltage to the time.With reference to Figure 13, method 1100 comprises a circulation routine 1104, and this circulation routine 1104 is at 1116 programming units, increases by 1 at 1120 pairs of countings, reaches predetermined (perhaps able to programme) boundary up to counting, for example 10 (1128).In case counting reaches predetermined threshold 1118, then program finishes 312.
Have illustrated and described principle of the present invention, very obvious to those skilled in the art, under the situation that does not break away from these principles, can carry out various modifications on form and the details to the present invention.And within the spirit and scope that all modifications all drops on appended claims and limited.
It is the right of priority of the korean patent application of 10-2004-0012984 at the application number that Korean Patent office proposes that the application is required on February 26th, 2004, and its disclosure is incorporated into inferior by reference.
Claims (24)
1. method that is used for a plurality of storage unit are programmed into expectation state, each unit has the possible state more than two, and this method comprises:
Apply at least one programming pulse to described unit;
Each unit of verification has reached expectation state;
Selection is programmed into the unit of high state; And
Apply at least one extra programming pulse to selected unit, and the further state of these unit of verification not.
2. method according to claim 1, wherein, each unit of verification has reached expectation state and has comprised:
Apply calibration voltage to described unit; And
Apply the read-out voltage that equals this calibration voltage with sense data from programmed cells.
3. method according to claim 1, wherein, apply at least one extra programming pulse to selected unit and not further the state of these unit of verification increased the tolerance limit of reading between high state and the next high state.
4. method according to claim 1 wherein, applies at least one programming pulse reached expectation to unit and each unit of verification state and hockets, till applying extra programming pulse.
5. method that is used to operate memory device with a plurality of storage unit, each storage unit has the possible state more than two, and this method comprises:
Described unit is programmed into the state of expectation;
The voltage that applies selection is in the state of expectation with the described unit of verification;
The unit that will be in high state is programmed into higher level; And
The voltage that applies described selection is with from described unit sense data.
6. method according to claim 5, wherein, the unit that will be in high state is programmed into higher level and has increased the tolerance limit of reading between described high state and the higher level.
7. method according to claim 5 wherein, hockets described unit state that is programmed into expectation and the voltage that applies selection with the state that the described unit of verification is in expectation, till the unit that is in high state is programmed into higher level.
8. method according to claim 5, also comprise apply at least one extra selection voltage to described unit and not further the state of these unit of verification to increase the tolerance limit of reading between high state and the higher level.
9. the method for reading tolerance limit between the state that increases a plurality of storage unit, each storage unit has the possible state more than two, and this method comprises:
Apply programming pulse to described unit;
Each unit of verification has reached the state of expectation; And
Apply at least one extra programming pulse to the unit that is in high state, and the further state of these unit of verification not.
10. method according to claim 9, wherein, the state that each unit of verification has reached expectation comprises:
Apply calibration voltage to described unit; And
Come sense data from programming unit by applying the read-out voltage that equates with this calibration voltage.
11. method according to claim 9, wherein, apply at least one extra programming pulse to the unit that is in high state and not further the state of these unit of verification increased the tolerance limit of reading between the state.
12. method according to claim 9 wherein, applies programming pulse and has reached expectation state to described unit and each unit of verification and hocket, till applying extra programming pulse.
13. a non-volatile memory device comprises:
A plurality of storage unit, each unit storage indication is more than the quantity of electric charge of two possibility states; With
Be connected to the control circuit of described storage unit, this control circuit alternately is applied to described storage unit with programming pulse and calibration voltage, be in the state of expectation up to all unit, and this control circuit applies at least one extra programming pulse to the unit that is in high state, and does not apply calibration voltage.
14. non-volatile memory device according to claim 13, wherein, the read-out voltage that described control circuit will equal described calibration voltage is applied to described unit.
15. non-volatile memory device according to claim 13, wherein, described equipment comprises in response to described extra programming pulse and increases, reads tolerance limit between the highest location mode and the highest next location mode.
16. non-volatile memory device according to claim 13, wherein, described control circuit alternately applies programming pulse and calibration voltage, till this control circuit applies described at least one extra programming pulse.
17. a non-volatile memory device comprises:
Be used to apply the device of at least one programming pulse to the unit;
Be used for the device that each unit of verification has reached expectation state;
Be used to select be programmed into the device of the unit of high state; With
Be used to apply to selected unit and the not further device of the state of these unit of verification of at least one extra programming pulse.
18. non-volatile memory device according to claim 17 wherein, describedly is used for the device that each unit of verification reached expectation state and comprises:
Be used to apply the device of calibration voltage to described unit; With
Be used to apply the read-out voltage that equals this calibration voltage with from the device of programming unit sense data.
19. non-volatile memory device according to claim 17, wherein, described be used to apply at least one extra programming pulse to selected unit and not further the device of the state of these unit of verification comprise the device of reading tolerance limit that is used to increase between high state and next high state.
20. non-volatile memory device according to claim 17, wherein, describedly be used to apply at least one programming pulse to the device of unit be used for the device that each unit of verification reached expectation state and hocket, till the described device that is used to apply extra programming pulse applies extra programming pulse.
21. a non-volatile memory device comprises:
Memory unit, the storage indication of each unit more than two may states the quantity of electric charge and
Be connected to the control device of described memory unit, this control device alternately is applied to described memory unit with programming pulse and calibration voltage, be in the state of expectation up to all memory units, and this control device applies at least one extra programming pulse to the memory unit that is in high state, and does not apply calibration voltage.
22. non-volatile memory device according to claim 21, wherein, the read-out voltage that described control device will equal calibration voltage is applied to described memory unit.
23. non-volatile memory device according to claim 21, wherein, described equipment comprises in response to described extra programming pulse and increases, reads the tolerance limit device between the highest location mode and the highest next location mode.
24. non-volatile memory device according to claim 21, wherein, described control device alternately applies programming pulse and calibration voltage, till this control device applies described at least one extra programming pulse.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2004-0012984A KR100525004B1 (en) | 2004-02-26 | 2004-02-26 | Multi-level cell flash memory device and program method thereof |
| KR12984/2004 | 2004-02-26 | ||
| KR12984/04 | 2004-02-26 | ||
| US11/021,181 | 2004-12-22 | ||
| US11/021,181 US7054199B2 (en) | 2004-02-26 | 2004-12-22 | Multi level flash memory device and program method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1661727A true CN1661727A (en) | 2005-08-31 |
| CN100505100C CN100505100C (en) | 2009-06-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200510052527XA Expired - Fee Related CN100505100C (en) | 2004-02-26 | 2005-02-28 | Multi level flash memory device and program method |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2005243230A (en) |
| CN (1) | CN100505100C (en) |
| DE (1) | DE102005009700B4 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102779554A (en) * | 2006-05-15 | 2012-11-14 | 苹果公司 | Maintenance operations for multi-level data storage cells |
| CN101261879B (en) * | 2007-01-10 | 2013-05-01 | 三星电子株式会社 | Program method of multi bit flash memory device for reducing a program error |
| CN101404182B (en) * | 2007-05-25 | 2014-05-07 | 三星电子株式会社 | Program and erase methods for nonvolatile memory |
| CN104094354A (en) * | 2011-12-16 | 2014-10-08 | 桑迪士克科技股份有限公司 | Non-volatile memory and method with improved first pass programming |
| CN104332178A (en) * | 2013-07-16 | 2015-02-04 | 希捷科技有限公司 | Partial reprogramming of solid-state non-volatile memory cells |
| US9431126B2 (en) | 2013-03-14 | 2016-08-30 | Silicon Storage Technology, Inc. | Non-volatile memory program algorithm device and method |
| CN106920569A (en) * | 2010-05-31 | 2017-07-04 | 三星电子株式会社 | The method for operating non-volatile memory devices |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101634363B1 (en) | 2009-10-05 | 2016-06-29 | 삼성전자주식회사 | Nonvolitile memory device and program method thereof |
| KR101633018B1 (en) * | 2009-12-28 | 2016-06-24 | 삼성전자주식회사 | Flash memory device and program method thereof |
| KR102603916B1 (en) * | 2018-04-25 | 2023-11-21 | 삼성전자주식회사 | Storage device comprising nonvolatile memory device and controller |
| CN110036446A (en) * | 2019-02-20 | 2019-07-19 | 长江存储科技有限责任公司 | Method for being programmed to storage system |
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| JPS63171499A (en) * | 1987-01-08 | 1988-07-15 | Mitsubishi Electric Corp | Eprom programming device |
| JPH03125399A (en) * | 1989-10-09 | 1991-05-28 | Hitachi Ltd | Semiconductor storage device |
| JP3740212B2 (en) * | 1996-05-01 | 2006-02-01 | 株式会社ルネサステクノロジ | Nonvolatile semiconductor memory device |
| JP2002184190A (en) * | 2000-12-11 | 2002-06-28 | Toshiba Corp | Non-volatile semiconductor memory |
-
2005
- 2005-02-24 DE DE200510009700 patent/DE102005009700B4/en not_active Expired - Fee Related
- 2005-02-28 JP JP2005054625A patent/JP2005243230A/en active Pending
- 2005-02-28 CN CNB200510052527XA patent/CN100505100C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102779554A (en) * | 2006-05-15 | 2012-11-14 | 苹果公司 | Maintenance operations for multi-level data storage cells |
| CN102779554B (en) * | 2006-05-15 | 2015-12-16 | 苹果公司 | The attended operation of multi-level data storage cells |
| CN101261879B (en) * | 2007-01-10 | 2013-05-01 | 三星电子株式会社 | Program method of multi bit flash memory device for reducing a program error |
| CN101404182B (en) * | 2007-05-25 | 2014-05-07 | 三星电子株式会社 | Program and erase methods for nonvolatile memory |
| CN106920569A (en) * | 2010-05-31 | 2017-07-04 | 三星电子株式会社 | The method for operating non-volatile memory devices |
| CN104094354A (en) * | 2011-12-16 | 2014-10-08 | 桑迪士克科技股份有限公司 | Non-volatile memory and method with improved first pass programming |
| US9431126B2 (en) | 2013-03-14 | 2016-08-30 | Silicon Storage Technology, Inc. | Non-volatile memory program algorithm device and method |
| CN104332178A (en) * | 2013-07-16 | 2015-02-04 | 希捷科技有限公司 | Partial reprogramming of solid-state non-volatile memory cells |
| CN104332178B (en) * | 2013-07-16 | 2018-10-19 | 希捷科技有限公司 | The part of solid state nonvolatile storage unit reprograms |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100505100C (en) | 2009-06-24 |
| JP2005243230A (en) | 2005-09-08 |
| DE102005009700B4 (en) | 2009-02-05 |
| DE102005009700A1 (en) | 2005-09-22 |
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