CN1658507A - Double correction software phase-lock loop implementation method - Google Patents

Double correction software phase-lock loop implementation method Download PDF

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CN1658507A
CN1658507A CN 200510024277 CN200510024277A CN1658507A CN 1658507 A CN1658507 A CN 1658507A CN 200510024277 CN200510024277 CN 200510024277 CN 200510024277 A CN200510024277 A CN 200510024277A CN 1658507 A CN1658507 A CN 1658507A
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omega
theta
low pass
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pass filter
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CN100382431C (en
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纪飞峰
曼苏乐
陈陈
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Shanghai Jiaotong University
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Abstract

A double correcting software PLL in the field of signal processing technology. The processes are as follows: base on the standard signal, utilize the output of parallel double low pass filter to get resection tangent function to correct frequency; base on the output signal of the frequency correcting tache, use he output of parallel double low pass filter to get resection tangent function to correct phase; design low pass filter to assure PLL's tracking speed and precision; adopt TM320C2407DSP to program and speed up the calculation. This invention adopts simple loop control, has high stability and fast tracking speed. The temporary state response time is less than 20ms. It precisely and quickly measures the voltage, base wave frequency and phase of the current of the electric system. It supplies the synchronous signals to the non-power compensator, the filter and micro-computer protective device.

Description

The double correction software phase-lock loop implementation method
Technical field
What the present invention relates to is a kind of implementation method of phase-locked loop, specifically, is a kind of implementation method of double correction software phase-lock loop.Belong to the signal processing technology field.
Background technology
Acquisition system first-harmonic first phase and frequency are used analog phase-locked look, digital phase-locked loop technology always at present.Problems such as analog phase-locked look and digital phase-locked loop all adopt hardware to realize, analog phase-locked look exists that direct current null offset, device are saturated, losing lock, shake, reliability are low.Digital phase-locked loop is equally to the having relatively high expectations of device, and adopts relatively difficulty of Design of Digital Circuit low-pass filtering, and precision is difficult to improve.And even more importantly be, these two kinds of methods all depend on zero crossing detection constantly, but the harmonic wave that the electric current and voltage in the practical power systems exists makes that signal zero and first-harmonic are inconsistent zero point, and may repeatedly zero passage occur at actual zero crossing place, thereby make testing result bigger error occur.
Find by prior art documents, at " high Precision Detection of fundamental phase and frequency and the application in Active Power Filter-APF " (Proceedings of the CSEE that Zhou Weiping, Wu Guozheng and Xia Li showed, 2004,24 (4): the 91-96 page or leaf), the concrete steps of this phase-locked loop implementation method are as follows: 1) phase-detection: based on the principles of construction of trigonometric function orthogonality and adaptive-filtering the close loop control circuit of Phase Tracking, and in closed loop, combine time-delay feedback and variable parameters PI control technology.2) measure fundamental frequency: follow the tracks of based on first phase on the basis of detecting control system, the time rate of change of first phase correction when asking for stable state promptly can be used as the feedback of frequency-tracking.Its weak point is: adopting increases time-delay feedback and variable parameters PI control in the closed loop, make dynamic responding speed reduce when having improved tracking accuracy, and the response time is 50ms, require response speed faster occasion can't use.
Summary of the invention
The objective of the invention is to overcome deficiency of the prior art; a kind of implementation method of double correction software phase-lock loop is proposed; make it avoid the interference of harmonic wave; adopt simple open loop control; stability is high, and tracking velocity is fast, and transient response time is less than 20ms; accurately measure the fundamental frequency and the phase place of voltage in the electric power system, electric current apace, for devices such as the reactive-load compensator in the electric power system, active power filter and Microcomputer Protection provide the system synchronization signal.
The present invention is achieved by the following technical solutions, and the present invention adopts open loop to realize, design frequency correction link at first, and secondly designed phase correction link designs low pass filter again, adopts DSP (digital signal processor) programming at last.
Concrete steps of the present invention are as follows:
1, with the standard signal is benchmark, utilizes the output of the parallel two low pass filters tan of negating to carry out frequency correction.
The method of its correction is: f (t) is an input signal, ω 1Be system's fundamental frequency, ω 0=100 π are standard 50HZ angular frequency.Contain harmonic wave and flip-flop among the f (t), its function expression is
f ( t ) = A 0 + A 1 sin ( ω 1 t + θ 1 ) + Σ n = 2 ∞ A n sin ( n ω n t + θ n ) - - - ( 1 )
A in the formula (1) 0Be DC component; θ 1Be the fundametal compoment initial phase angle; N is a harmonic number; θ nInitial phase angle for each harmonic.Input signal f (t) multiplies each other with the standard cosine signal and obtains:
f ( t ) · cos ( ω 0 t ) = A 0 cos ( ω 0 t ) + A 1 2 sin ( ( ω 1 - ω 0 ) t + θ 1 ) + A 1 2 sin ( ( ω 1 + ω 0 ) t + θ 1 ) - - - ( 2 )
+ Σ n = 2 ∞ { A n 2 sin ( ( n ω 1 + ω 0 ) t + θ n ) + A n 2 sin ( ( n ω 1 - ω 0 ) t + θ n ) }
The fundamental frequency that electric power system allows is 50 ± 0.5HZ, in the formula (2) A 1 2 sin ( ( ω 1 - ω 0 ) t + θ 1 ) Frequency range between ± 0.5HZ, and other frequency is all above the fundamental frequency ω of system 1, can adopt low pass filter (LPF) with angular frequency more than or equal to ω 1The composition filtering.Promptly can obtain by LPF:
k 1 A 1 2 sin ( ( ω 1 - ω 0 ) t + θ 1 + θ x ) u 1 ( t ) = LPF [ f ( t ) · cos ( ω 0 t ) ] - - - ( 3 )
Because u 1(t) be the alternating current component of a low frequency, so this component is through producing phase shift, θ in the formula (3) behind the low pass filter xThe expression signal is through the phase shift behind the low pass filter, K 1The multiplication factor of expression low pass filter.Can obtain equally with input signal f (t) and standard sine signal multiplication, and through behind the low pass filter:
u 2 ( t ) = LPF [ f ( t ) · sin ( ω 0 t ) ] = k 1 A 1 2 cos ( ( ω 1 - ω 0 ) t + θ 1 + θ x ) - - - ( 4 )
Formula (3) and formula (4) are divided by and can be obtained:
u 1(t)/u 2(t)=tan((ω 10)t+θ 1x) (5)
To formula (5) negate tangent and and ω 0The t addition can get:
φ 1(t)=arctan(u 1(t)/u 2(t))+ω 0t=(ω 10)t+θ 1x0t=ω 1t+θ 1x (6)
By after the frequency correction link, the harmonic components among the input signal f (t) has been avoided the interference of harmonic wave, output signal φ by filtering thus 1(t) with f (t) in the phase place of fundametal compoment also differ a fixing angle θ x
2, be benchmark with frequency correction link output signal, utilize the output of the parallel two low pass filters tan of negating to carry out phasing.
The method of its correction is: at first by the output signal φ of frequency correction link 1(t) generation cosine function signal and input signal f (t) multiply each other and obtain:
f ( t ) · cos ( φ 1 ( t ) ) = A 0 cos ( φ 1 ( t ) ) + A 1 2 sin ( ω 1 t + θ 1 + φ 1 ( t ) ) + A 1 2 sin ( ( ω 1 t + θ 1 - φ 1 ( t ) ) - - - ( 7 )
+ Σ n = 2 ∞ { A n 2 sin ( ( n ω 1 + θ n + φ 1 ( t ) ) + A n 2 sin ( ( nω 1 + θ n - φ 1 ( t ) ) }
In the formula (7) A 1 2 sin ( ω 1 t + θ 1 - φ 1 ( t ) ) = A 1 2 sin ( ω 1 t + θ 1 - ω 1 t - θ 1 - θ x ) = A 1 2 sin ( - θ x ) This Xiang Weiyi DC component, and other are frequency and are higher than ω 1Alternating current component.So can obtain this DC component by low pass filter, that is:
u 3 ( t ) = LPF [ f ( t ) · cos ( φ 1 ( t ) ) ] = k 2 A 1 2 sin ( - θ x ) - - - ( 8 )
K in the formula (8) 2Be the multiplication factor of low pass filter, in order to programme conveniently, the cut-off frequency of this low pass filter is identical with frequency correction link low pass filter.Equally can be by the output signal φ of frequency correction link 1(t) produce sinusoidal signal and input signal f (t) and multiply each other, and can obtain through behind the low pass filter:
u 4 ( t ) = LPF [ f ( t ) · sin ( φ ( t ) ) ] = k 2 A 1 2 cos ( - θ x ) - - - ( 9 )
Formula (8) and formula (9) are divided by and can be obtained:
u 3(t)/u 4(t)=tan(-θ x) (10)
To formula (10) negate tangent and and φ 1(t) addition can get:
φ 2(t)=arctan(u 3(t)/u 4(t))+φ 1(t)=ω 1t+θ 1xx=ω 1t+θ 1 (11)
By formula (11) φ as can be known 2(t)=ω 1T+ θ 1, the phase place of fundametal compoment current time among the input signal f (t) that obtains after the process phasing link that Here it is.Obtain φ 2(t) can obtain the middle synchronous sinusoidal signal of fundametal compoment by look-up table again after with input signal f (t).If need M frequency multiplication or Fractional-N frequency, can be respectively with φ 2(t) multiply by M or divided by N, tabling look-up then obtains corresponding frequency multiplication of fundametal compoment or fractional frequency signal.
The frequency correction link is identical with the structure of phasing link, and used low pass filter also can be identical, so two links can adopt identical program, simplified programming.Whole phase-locked loop adopts simple open loop control, and stability is high.Low pass filter in the phase-locked loop is a time delay process, but compares with closed-loop control, and tracking velocity is fast, and emulation shows that with experiment the transient response time of this phase-locked loop is less than 20ms.
3, design low pass filter, the tracking velocity and the precision of assurance phase-locked loop
In two correction power frequency software phase-lock loops, filter is low pass filter, and low pass filter is very big to the precision and the speed influence of phase-locked loop.Realize that for ease of software filter must be selected digital filter, the selection of the type of digital filter, cut-off frequency and exponent number directly has very big influence to the stable state accuracy and the dynamic responding speed of phase-locked loop.
1) selects IIR (infinite impulse response) digital filter
Digital filter can be divided into finite impulse response FIR (Finite ImpulseResponse) filter and infinite impulse response IIR (Infinite Impulse Response) filter according to the width of impulse response.Iir filter can obtain very high selectivity characteristic with less exponent number, and used memory cell is few, operation times is few, has economy, characteristics of high efficiency.But its phase place is non-linear, makes testing result can produce phase distortion, requires the low occasion of sensitiveness so be applicable to phase place.The FIR filter has good phase characteristic and stability, but compare with iir filter, the unit that needs more storage, and computational efficiency lower (realize identical filtering characteristic, use the realization of FIR filter) than realizing exponent number with iir filter even high last 10 times.In software phase-lock loop, the macrooperation amount that higher order filter brings will certainly influence the DSP real-time of signal processing.The two paths of signals that obtains after considering input signal and standard sine, cosine function multiplying each other has identical frequency characteristic, is identical through the phase shift that produces after the frequency correction link, so the calculating of arctan function is not influenced.And enter in the signal of phasing link, amount to be separated is a DC component, does not have phase problem during stable state.Take all factors into consideration, select the IIR low pass filter to be easy to software and realize, and can obtain higher detection precision and less time-delay with lower exponent number.
2) select Butterworth LPF
Low pass filter commonly used has Bezier (Bessel), Butterworth (Butterworth), Chebyshev (Chebychev) and oval (Elliptic) filter etc.The Bezier low pass filter has best dynamic responding speed, has linear phase in the certain frequency scope, and its shortcoming is that the decay in stopband is slow.Utilize the MATALAB simulation software that other four kinds of wave digital lowpass filters have been carried out emulation relatively, the filter sample frequency is made as 10KHZ (consistent with the sample frequency of DSP), and exponent number is made as 2, and cut-off frequency is made as 10HZ.Butterworth filter (Butterworth) low pass filter does not have DC quantity and successively decreases, and the amplitude characteristic of maximally-flat is arranged in passband.Chebyshev I mode filter has ripple in passband, Chebyshev II type all has certain ripple in passband and stopband, compares with Butterworth filter, and its exponent number was lower when Chebyshev filter was realized, but its dynamic responding speed is slow.Elliptic function type low pass filter such as all is in passband and stopband at a ripple.Low pass filter requires undampedly to DC quantity in two correction power frequency software phase-lock loops, and ripple is little, has advantages of higher stability and dynamic responding speed, requires low to phase accuracy.Butterworth LPF, have DC component undamped, the characteristics of ripple-free in passband and stopband.Though dynamic responding speed is not the fastest, to take all factors into consideration, this low pass filter relatively is fit to be applied to two power frequency software phase-lock loops of proofreading and correct.
3) selecting the low pass filter exponent number is 2
According to digital signal processing theory as can be known, under all identical situation of filter type, cut-off frequency, the low pass filter exponent number will influence the effect of filter.When filter order increased, the accuracy of detection of filter increased, but response speed descends.Consider that will consider the signal frequency of removing in the signal of the actual input of low pass filter in the phase-locked loop is higher than power frequency, 2 rank filters can meet the demands, and exponent number is high more, and program realizes that difficulty will increase, increase computing time.To have selected exponent number be 2 Butterworth LPF so take all factors into consideration.
4) selecting low pass filter cutoff frequency is 20HZ
In the signal by phase locked loop filter, the component frequency that needs to keep is usually less than 1HZ, and needs the component frequency of filtering to be higher than 50HZ, so the cut-off frequency scope of low pass filter is 1HZ~50HZ.When cut-off frequency was higher than 20HZ, the amplitude at 50HZ frequency place was not 0, so can cause certain error.And when the cut-off frequency of low pass filter was lower than 10HZ, the amplitude at 50HZ frequency place was 0, because cut-off frequency is high more, response speed is fast more, the easy more processing of filter coefficient again.So taking all factors into consideration the cut-off frequency that low pass filter is set is 20HZ.Utilize the digital filter design instrument in the MATLAB/SIMULINK simulation software, can obtain 2 rank IIR wave digital lowpass filters.
4, adopt dsp program, accelerate arithmetic speed.
Adopt 16 fixed point TMS320C2407DSP to realize two correction power frequency software phase-lock loop functions.Because the required precision of parameter is higher in the low pass filter, it is very fast that phase-locked loop requires the software program speed of service simultaneously, so this program has adopted 32 fixed-point computation and trigonometric function look-up table.This program running is respond well, and the phase-locked loop response time is less than 20ms.
The invention has the beneficial effects as follows: 1, adopt open loop control, improve the tracking velocity and the stability of phase-locked loop; 2, low pass filter is carried out appropriate design, guarantee the tracking accuracy of phase-locked loop; 3, this phase-locked loop is realized by software programming, strong interference immunity; 4, this novel phase-locked loop can calculate in the input signal fundametal compoment respectively in the error of standard signal, thereby realizes the tracking to input signal, and frequency correction link and phasing link structure are identical, is easy to the programming realization; 5, controller adopts 16 fixed DSPs (TMS320C2407) at a high speed, and arithmetic speed is very fast.
Description of drawings
Fig. 1 is two power frequency software phase-lock loop matlab analogous diagram of proofreading and correct
Fig. 2 is the tracking oscillogram of phase-locked loop to SPA sudden phase anomalies
Fig. 3 is the tracking oscillogram of phase-locked loop to the frequency plot simultaneous mutation
Embodiment
Be further described below in conjunction with accompanying drawing and specific embodiment, concrete steps are as follows:
1) the discrete sampling frequency is 10KHZ in MATLAB emulation.
2) design the phase-locked loop model structure as shown in Figure 1, module source is a signal source, and port f output needs phase-locked signal f (t), and port V output signal V (t) is the fundametal compoment among the f (t).The waveform of fundametal compoment V (t) and pll output signal s (t) waveform are shown by the scope1 module.
At first the input signal f (t) that formula (1) is expressed through the A/D sampling after, become digital signal, then respectively with reference signal sin (ω 0T), cos (ω 0T) multiply each other.The gained result passes through wave digital lowpass filter 1 and wave digital lowpass filter 2 respectively, the u as a result of low pass filter 1 output 1(t) with the u as a result of low pass filter 2 output 2(t) be divided by after, to the gained result tangent of negating, arc-tangent value and reference signal ω 0The t addition just obtains signal psi 1(t), φ 1(t) be exactly by the frequency correction link that obtain with signal input signal fundametal compoment same frequency.According to signal psi 1(t) obtain function sin (φ 1T) and cos (φ 1T) with after input signal f (t) multiplies each other, pass through the filtering of low pass filter 3 and low pass filter 4 respectively, obtain signal u 3(t) and u 4(t) get along, then to merchant's tan of negating, arc-tangent value again with φ 1(t) addition obtains signal psi 2(t), signal psi 2(t) be exactly after the phasing link, obtain with input signal f (t) in the identical real-time phase signal of fundametal compoment, just can obtain by Sine Function Generator again and input signal f (t) in the fundametal compoment same frequency with the SIN function sin (φ of unit of first phase 2), the phase-locked loop tracking signal that need obtain just.
3) tracking effect of phase-locked loop is worked as under the phase of input signals sudden change situation in emulation testing.
Input signal f (t) also contains 20% 3 order harmonic components and 10% noise component(s) except that fundametal compoment.The tracking transient process of phase-locked loop when having shown input signal f (t) SPA sudden phase anomalies among Fig. 2, the phase shift of about π/4 takes place suddenly in the moment of 1S fundametal compoment in f (t), pll output signal is followed the tracks of the variation of input signal behind 18ms, the output waveform aberration rate of phase-locked loop is lower than 10 -4
4) tracking effect of phase-locked loop is worked as under the phase frequency simultaneous mutation situation in emulation testing.
As shown in Figure 3, the frequency of the fundametal compoment V (t) in 1S moment input signal f (t) sports 51HZ by 50HZ, also produces the phase shift of about π/6 simultaneously.The variation of input signal on phase-locked loop is followed the tracks of in 20ms, after transient process finished, the frequency of pll output signal s (t) and phase place and V (t) signal all were consistent.

Claims (5)

1, a kind of implementation method of double correction software phase-lock loop is characterized in that, concrete steps are as follows:
1) with the standard signal is benchmark, utilizes the output of the parallel two low pass filters tan of negating to carry out frequency correction;
2) be benchmark with frequency correction link output signal, utilize the output of the parallel two low pass filters tan of negating to carry out phasing;
3) design low pass filter, the tracking velocity and the precision of assurance phase-locked loop;
4) adopt 16 fixed point TMS320C2407DSP programming, accelerate arithmetic speed.
As the implementation method of the said double correction software phase-lock loop of claim 1, it is characterized in that 2, the output of the parallel two low pass filters of the described utilization tan of negating carries out frequency correction, the method for its correction is: f (t) is an input signal, ω 1Be system's fundamental frequency, ω 0=100 π are standard 50HZ angular frequency, contain harmonic wave and flip-flop among the f (t), and expression formula is: f ( t ) = A 0 + A 1 sin ( ω 1 t + θ 1 ) + Σ n = 2 ∞ A n sin ( n ω n t + θ n ) - - - ( 1 ) , A in the formula (1) 0Be DC component; θ 1Be the fundametal compoment initial phase angle; N is a harmonic number; θ nBe the initial phase angle of each harmonic, input signal f (t) multiplies each other with the standard cosine signal and obtains:
f ( t ) · cos ( ω 0 t ) = A 0 cos ( ω 0 t ) + A 1 2 sin ( ( ω 1 - ω 0 ) t + θ 1 ) + A 1 2 sin ( ( ω 1 + ω 0 ) t + θ 1 )
+ Σ n = 2 ∞ { A n 2 sin ( ( n ω 1 + ω 0 ) t + θ n ) + A n 2 sin ( ( n ω 1 - ω 0 ) t + θ n ) } - - - ( 2 )
Adopt low pass filter with angular frequency more than or equal to ω 1The composition filtering, obtain: k 1 A 1 2 sin ( ( ω 1 - ω 0 ) t + θ 1 + θ x ) u 1 ( t ) = LPF [ f ( t ) · cos ( ω 0 t ) ] - - - ( 3 ) , Wherein: u 1(t) be the alternating current component of a low frequency, θ xThe expression signal is through the phase shift behind the low pass filter, K 1The multiplication factor of expression low pass filter with input signal f (t) and standard sine signal multiplication, and can obtain behind the process low pass filter: u 2 ( t ) = LPF [ f ( t ) · sin ( ω 0 t ) ] = k 1 A 1 2 cos ( ( ω 1 - ω 0 ) t + θ 1 + θ x ) - - - ( 4 ) , Formula (3) and formula (4) be divided by obtain u 1 ( t ) / u 2 ( t ) = tan ( ( ω 1 - ω 0 ) t + θ 1 + θ x ) - - - ( 5 ) , To formula (5) negate tangent and and ω 0The t addition obtains: φ 1 ( t ) = arctan ( u 1 ( t ) / u 2 ( t ) ) + ω 0 t = ( ω 1 - ω 0 ) t + θ 1 + θ x + ω 0 t = ω 1 t + θ 1 + θ x - - - ( 6 ) .
As the implementation method of the said double correction software phase-lock loop of claim 1, it is characterized in that 3, the output of the parallel two low pass filters of the described utilization tan of negating carries out phasing, the method for its correction is: at first by the output signal φ of frequency correction link 1(t) generation cosine function signal and input signal f (t) multiply each other and obtain:
f ( t ) · cos ( φ 1 ( t ) ) = A 0 cos ( φ 1 ( t ) ) + A 1 2 sin ( ω 1 t + θ 1 + φ 1 ( t ) ) + A 1 2 sin ( ( ω 1 t + θ 1 - φ 1 ( t ) )
+ Σ n = 2 ∞ { A n 2 sin ( ( n ω 1 + θ n + φ 1 ( t ) ) + A n 2 sin ( ( n ω 1 + θ n - φ 1 ( t ) ) } - - - ( 7 ) ,
In the formula (7) A 1 2 sin ( ω 1 t + θ 1 - φ 1 ( t ) ) = A 1 2 sin ( ω 1 t + θ 1 - ω 1 t - θ 1 - θ x ) = A 1 2 sin ( - θ x ) This Xiang Weiyi DC component, and other are frequency and are higher than ω 1Alternating current component, obtain by low pass filter:
u 3 ( t ) = LPF [ f ( t ) · cos ( φ 1 ( t ) ) ] = k 2 A 1 2 sin ( - θ x ) - - - ( 8 ) , K in the formula (8) 2Be the multiplication factor of low pass filter, by the output signal φ of frequency correction link 1(t) produce sinusoidal signal and input signal f (t) and multiply each other, and obtain through behind the low pass filter: u 4 ( t ) = LPF [ f ( t ) · sin ( φ ( t ) ) ] = k 2 A 1 2 cos ( - θ x ) - - - ( 9 ) , Formula (8) and formula (9) are divided by, obtain u 3 ( t ) / u 4 ( t ) = tan ( - θ x ) - - - ( 10 ) , To formula (10) negate tangent and and φ 1(t) addition obtains: φ 2 ( t ) = arctan ( u 3 ( t ) / u 4 ( t ) ) + φ 1 ( t ) = ω 1 t + θ 1 + θ x = ω 1 t + θ 1 - - - ( 11 ) , By formula (11) φ as can be known 2(t)=ω 1T+ θ 1, the phase place of fundametal compoment current time among the input signal f (t) that obtains after the process phasing link that Here it is.
4, as the implementation method of the said double correction software phase-lock loop of claim 1, it is characterized in that, described design low pass filter is meant: at first select iir digital filter, next selects Butterworth LPF, selecting the low pass filter exponent number once more is 2, and selecting low pass filter cutoff frequency at last is 20HZ.
5, as the implementation method of the said double correction software phase-lock loop of claim 1, it is characterized in that low pass filter and step 2 in the described step 1)) in the cut-off frequency of low pass filter identical.
CNB2005100242779A 2005-03-10 2005-03-10 Double correction software phase-lock loop implementation method Expired - Fee Related CN100382431C (en)

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CN101604172B (en) * 2009-04-23 2012-08-22 上海交通大学 Voltage control method based on phase-lock loop of decoupling multi-coordinate system
CN102832931A (en) * 2012-09-18 2012-12-19 浙江昱能光伏科技集成有限公司 Phase demodulation method, phase demodulation device and phase-locked loop based on incomplete period grid voltage signal
CN103425516A (en) * 2013-07-10 2013-12-04 电子科技大学 Phase-locked loop implementation method
CN104617946A (en) * 2015-02-11 2015-05-13 国网上海市电力公司 Single-period double-correction power-frequency software phase-locked loop method
CN115021625A (en) * 2022-06-15 2022-09-06 杭州士腾科技有限公司 Position analysis circuit and method of permanent magnet synchronous motor, and control circuit and system thereof

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JPS5850827A (en) * 1981-09-08 1983-03-25 Fujitsu Ltd Pll circuit
JP2944607B2 (en) * 1998-02-12 1999-09-06 日本電気アイシーマイコンシステム株式会社 Digital PLL circuit and clock generation method
FR2840469A1 (en) * 2002-05-28 2003-12-05 Koninkl Philips Electronics Nv PHASE LOCK LOOP

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101604172B (en) * 2009-04-23 2012-08-22 上海交通大学 Voltage control method based on phase-lock loop of decoupling multi-coordinate system
CN102832931A (en) * 2012-09-18 2012-12-19 浙江昱能光伏科技集成有限公司 Phase demodulation method, phase demodulation device and phase-locked loop based on incomplete period grid voltage signal
CN103425516A (en) * 2013-07-10 2013-12-04 电子科技大学 Phase-locked loop implementation method
CN103425516B (en) * 2013-07-10 2016-02-17 电子科技大学 A kind of phaselocked loop implementation method
CN104617946A (en) * 2015-02-11 2015-05-13 国网上海市电力公司 Single-period double-correction power-frequency software phase-locked loop method
CN115021625A (en) * 2022-06-15 2022-09-06 杭州士腾科技有限公司 Position analysis circuit and method of permanent magnet synchronous motor, and control circuit and system thereof

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