CN1655343A - Pre-soldering arrangement for semiconductor packaging substrate and method for making same - Google Patents
Pre-soldering arrangement for semiconductor packaging substrate and method for making same Download PDFInfo
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- CN1655343A CN1655343A CNA2004100042049A CN200410004204A CN1655343A CN 1655343 A CN1655343 A CN 1655343A CN A2004100042049 A CNA2004100042049 A CN A2004100042049A CN 200410004204 A CN200410004204 A CN 200410004204A CN 1655343 A CN1655343 A CN 1655343A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
This invention relates to semi-conductor sealed baseboard pre-solder structure and its process method. The structure comprises electrical connection pad, conductive column and solder materials. The method comprises the following steps: providing at least one semi-conductor sealed base board with several connection pads on surface; forming insulation protective layer on the sealed base board with multiple openings and exposed connection pads; finally forming conductive column and solder materials in the plating openings.
Description
Technical field
The invention relates to a kind of pre-scolding tin structure and method for making thereof of conductor package substrate, particularly about a kind of on the electric connection pad of base plate for packaging, utilize to electroplate the manufacture method that forms pre-scolding tin structure with etching mode.
Background technology
For making packaging part more compact, thin space (Fine-pitch) product that production line width and weld pad size are dwindled becomes the target of this field ongoing effort, such as BGA, Flip Chip, chip size packages (CSP, Chip Size Package) with multi-chip module (MCM, Multi ChipModule) etc., can dwindle the IC area and have high density and the packaging part of multitube pin characteristic day by day becomes the main flow of encapsulation on the market.With the flip chip technology (fct) is example, existing flip chip technology (fct) is a configured electrodes electric connection pad (ElectrodePads) on the surface of semiconductor integrated circuit (IC) chip, and on organic circuit board, form corresponding electric connection pad, by solder bump (Solder Bump) or other conductive adhesive material are set between this chip and circuit board, be arranged on this circuit board in the ventricumbent mode of electrical contact for this chip.
The formed pre-scolding tin structure of this solder bump or conductive adhesive material provides electrical I/O (I/O) and mechanical connection the between this chip and circuit board, pre-scolding tin structure such as Fig. 1, Fig. 2 and shown in Figure 3 of existing flip chip technology (fct).
As shown in Figure 1, a plurality of metal couplings 11 are formed on the electrode pad 12 of chip 13, and a plurality of pre-solder bumps of being made by scolder 14 then are formed on the electric connection pad 15 of circuit board 16.Be enough to make under the reflow temperature condition of these pre-solder bump 14 fusions, by pre-solder bump 14 reflows to corresponding metal coupling 11 being formed scolding tin knot (Joint) 17.With regard to solder bump scolding tin knot, can be further in the gap of 16 of this chip 13 and this circuit boards, insert primer material 18, with thermal expansion difference that suppresses 16 of this chip 13 and this circuit boards and the stress that reduces this scolding tin knot 17.
As shown in Figure 2, be formed with a plurality of contact pad 21a and many conductive trace 21b on the surface insulation protective layer 22 of organic circuit board 2, this contact pad 21a and conductive trace 21b are made by metal material (for example copper) typically.Afterwards, on the surface of this circuit board 2, form organic insulating protective layer 24, for example green lacquer etc.; be formed at these circuit board 2 lip-deep circuit layers and insulation characterisitic is provided so as to protection; wherein, be formed with a plurality of perforates in this insulating protective layer 24, manifest the contact pad 21a on these circuit board 2 surfaces.At last, being formed with pre-solder bump 25 on this contact pad 21a ties for follow-up formation flip-chip scolding tin.
As shown in Figure 3, what base plate for packaging 30 surfaces were formed with green lacquer for example refuses layer 31, and has a plurality of electric connection pads 32 of formation position of the soldering tin material (figure is mark) of definition such as tin cream (Solder paste).On this base plate for packaging 30, be provided with earlier and have the template 33 of a plurality of grid 33a, after being placed with soldering tin material on this template 33, use for example roller 34 rollback on this template 33 to move, or make the grid 33a of this soldering tin material by this template 33 with spray pattern (Spraying), after removing this template 33, promptly on this electric connection pad 32, form scolding tin (figure is mark).Afterwards, make under the reflow temperature condition of this scolding tin fusion being enough to, carry out reflow (Reflow-soldering) operation, make this scolding tin after reflow, on the electric connection pad 32 of this substrate 30, form solder bump.So, just, can pass through mould printing technology (Stencil Printing Technology) and on conductor package substrate, form pre-scolding tin structure.As United States Patent (USP) the 5th, 672, cases such as 542,6,047,637,6,551,917 promptly are about mould printing technology and the pre-solder bump operation of using this mould printing technology.
But, the demand that increases for the miniaturization that reaches electronic product and function, the line design of circuit board/base plate for packaging is more and more intensive, and also more and more thinner little between layer and the layer, the package structure that therefore has high density and multitube pin characteristic also must dwindle line width and weld pad size.Under this trend; when the gap such as circuits such as weld pads continues reduction; insulating protective layer will cover the contact pad area of part between this weld pad; the weld pad size that exposes outside this insulating protective layer is dwindled more; cause the contraposition of follow-up formation solder bump to have problems; and make that scolding tin is difficult for causing mould printing technology acceptance rate low excessively attached on this electric connection pad, and the soldering tin material of melted by heating also has the phenomenon of overflow during reflow.
Simultaneously, soldering tin material has certain viscosity (Viscosity), and print pass the more remains in the interior soldering tin material of template hole wall also just relatively the more, causes printing next time employed soldering tin material quantity and shape and design specification and does not conform to.And; because of this insulating protective layer shared space and its formation influence highly; template bore size in the mould printing technology certainly will be reduced thereupon; not only, the template die sinking improves because of being difficult for causing the manufacturing cost of this template; more be difficult to make soldering tin material to pass, cause the technical bottleneck of operation because of the perforate pitch-row of this template is trickle.
Therefore, when using above-mentioned prior art and forming the pre-scolding tin structure of conductor package substrate, except the reduction that will cause the Master Cost increase in the operation, the inconvenience that causes operation and reliability, more because of thin space (Fine Pitch) required between each electric connection pad can't be provided, when causing the copper particle migration with reflow, runny soldering tin material overflow is bound up after the melted by heating, and generation is built bridge (Bridge) phenomenon and caused line short, has limited the development on the operation.
In addition, United States Patent (USP) the 5th, 926, No. 731 cases are to form non-soldering tin material floor on base plate for packaging, on this non-soldering tin material layer, then be formed with the column of making by soldering tin material (Pillar), this column upper surface accommodates the solder bump of being made by soldering tin material, defines the shape of solder bump and the height of standing by this column after the reflow.But, United States Patent (USP) the 5th, 926, must use a large amount of soldering tin materials to guarantee the scolding tin knot of solder bump in No. 731 cases, except the cost raising of soldering tin material, more, make the operation required time prolong, cause the operation difficulty to improve because the plating soldering tin material need spend the long time and be difficult for definition (Define) position.Simultaneously, use a large amount of soldering tin materials mean need be higher material cost, cause process cost significantly to improve.
And, owing to be subjected to electroplating the restriction of resistance layer, can't on this electric connection pad, produce uniform plated solder material, if will on electric connection pad, electroplate the soldering tin material that forms enough components, the characteristic of then formed plating resistance layer and thickness requirement are very loaded down with trivial details, can increase the complexity of operation.Simultaneously, this method is also restricted because of the contact area that soldering tin material is formed on the weld pad, and formed pre-scolding tin adhesion intensity is not good enough, fails reliability test by pre-scolding tin.
Therefore, in view of the above problems, problems such as the reliability that how to avoid low excessively such as mould printing operation acceptance rate in the prior art, Master Cost is expensive, operation is difficult, the operation required time prolongs, can't provide thin space, is produced when producing arch formation and plated solder material is not good, can effectively form the pre-scolding tin structure of conductor package substrate, become the problem that needs to be resolved hurrily at present.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is providing a kind of pre-scolding tin structure and method for making thereof that reduces the conductor package substrate of soldering tin material use amount.
Another object of the present invention is to provide a kind of pre-scolding tin structure and method for making thereof of avoiding the conductor package substrate of soldering tin material plating.
A further object of the present invention is to provide a kind of pre-scolding tin structure and method for making thereof of avoiding arch formation and allowing the conductor package substrate of thin space, makes the spacing of electric connection pad dwindle.
Another purpose of the present invention is to provide a kind of pre-scolding tin structure and method for making thereof that reduces the conductor package substrate of material cost.
Of the present invention again again a purpose be to provide a kind of pre-scolding tin structure and method for making thereof that shortens the conductor package substrate of activity time.
For reaching above-mentioned and other purpose, the method for making of the pre-scolding tin structure of conductor package substrate of the present invention comprises: the conductor package substrate that provides at least one surface to be formed with a plurality of electric connection pads, and wherein this conductor package substrate is a substrate of finishing leading portion line pattern chemical industry preface; Be formed with insulating protective layer on this substrate surface, this insulating protective layer has a plurality of perforates to expose outside this electric connection pad; Then, form conductive layer at this insulating protective layer and open surface, and on this conductive layer, form the patterning resistance layer, will electroplate perforate to cover the partially conductive layer and to define; At last, to electroplate in the perforate to electroplate successively at this and form conductive pole and soldering tin material.
The above-mentioned operation of process is made the pre-scolding tin structure of conductor package substrate of the present invention, and this pre-scolding tin structure comprises at least: electric connection pad, conductive layer, conductive pole and soldering tin material.This electric connection pad is formed at the surface of conductor package substrate, and is formed with insulating protective layer around this electric connection pad, and this insulating protective layer has a plurality of perforates to expose outside this electric connection pad.This conductive layer is formed at this electric connection pad upper surface, this conductive stud is formed on this conductive layer, this soldering tin material is formed on this conductive pole, so that this soldering tin material is carried out forming pre-solder bump after the reflow, and this pre-solder bump complete packet is covered the upper surface of this conductive pole.
The method for making of the pre-scolding tin structure of conductor package substrate of the present invention mainly is to be pre-formed conductive layer and conductive pole on the base plate for packaging surface earlier, electroplates to form soldering tin material on this conductive pole.Like this, just can be earlier by material cost lower and rate of deposition faster copper plated material electroplate out copper conductive pole, therefore the and then soldering tin material that electroplating cost is higher and rate of deposition is slower only need use a spot of soldering tin material.
In addition, the distance of center circle that electric connection pad spacing (Pad Pitch) is defined as continuous two electric connection pads from, electric connection pad at interval (Pad Distance) be defined as the circumferential distance of continuous two electric connection pads.
Can be by this conductive layer of etching with each conductive pole lateral erosion, can be under the constant prerequisite of electric connection pad spacing (Pitch), make the interval (Distance) between each conductive pole enlarge, can avoid these conductive pole hypotelorisms and the copper ion migration phenomenon takes place, allow to electrically connect and be lined with less spacing, and more can effectively avoid existing mould printing operation when electric connection pad size and spacing are dwindled, process cost raising and technical bottleneck that the perforate of template must diminish thereupon and be caused, and need confirm the shortcomings such as operation inconvenience that mould printing number of times and cleaning problems cause.
Simultaneously, electric connection pad of the present invention does not directly contact with soldering tin material, can effectively prevent existing the plating when forming soldering tin material, electroplating the plating resistance layer influence that is subjected to being covered in when generating soldering tin material on this conductive layer as the conductive layer of current conduction path, the pollution that causes in electroplating process electric connection pad, conductive layer and formed soldering tin material to be subjected to this plating resistance layer causes problems such as reliability reduction.
Therefore, the pre-scolding tin structure of using method for making gained of the present invention can solve the various shortcoming of prior art, not only can reduce required soldering tin material use amount, and can avoid having now plating and the arch formation that causes because of the plated solder material in the operation, so that the electric connection pad of thin space to be provided, more can to reduce material cost and shorten the operation required time by reducing the soldering tin material use amount.
Description of drawings
Fig. 1 shows a kind of generalized section of existing flip-chip assembly;
Fig. 2 shows existing circuit board generalized section with insulating protective layer and pre-solder bump;
Fig. 3 shows the existing generalized section that deposits soldering tin material by the mould printing technology on the electric connection pad of substrate; And
Fig. 4 A to Fig. 4 I shows the pre-scolding tin structure and the method for making generalized section thereof of conductor package substrate of the present invention.
Embodiment
Embodiment
Following examples further describe viewpoint of the present invention, but are not to limit category of the present invention anyways.
The generalized section of the method for making preferred embodiment of the pre-scolding tin structure of Fig. 4 A to Fig. 4 I detailed description conductor package substrate of the present invention.Must note herein, these all are the schematic diagrames of simplifying, basic structure of the present invention only is described in a schematic way, therefore only show the formation relevant with the present invention, and shown formation is not, and number, shape and dimension scale when implementing with reality drawn, number, shape and dimension scale during actual enforcement can be selected according to actual conditions, and it constitutes arrangement form complexity more.
See also Fig. 4 A, conductor package substrate 41 at first is provided, this conductor package substrate 41 is substrates of finishing leading portion line pattern chemical industry preface, and the surface of this base plate for packaging 41 has been formed with a plurality of conducting wire layers 42 that comprise electric connection pad 421.The operation technology that forms conducting wire and electric connection pad about base plate for packaging is various, and this is the operation technology that the present technique personnel know, and is not the technical characterictic of this case, so no longer narration.
See also Fig. 4 B, then on this is formed with base plate for packaging 4 surfaces of electric connection pad 421, form insulating protective layer 43.In the present embodiment; utilize arbitrary mode of printing, spin coating and applying; this insulating protective layer 43 is coated on this substrate 4 surfaces, makes this insulating protective layer 43 cover this conducting wire layer 42 by the patterning operation again, and make this electric connection pad 421 be revealed in the surface of this substrate 4.
This insulating protective layer 43 can be for example to be green lacquer of base material etc. with epoxy resin, and have the standard cubic feet per day that contracts to refuse welding layer material made, and make this insulating protective layer 43 be formed with a plurality of perforates 431, expose outside this electric connection pad 421.The distance of center circle that these electric connection pad 42 spacings (Pad Pitch) are defined as continuous two electric connection pads 42 from, this electric connection pad 42 definition of (PadDistance) at interval then is the circumferential distance of continuous two electric connection pads 42.Wherein, this insulating protective layer 43 also can be to be made by the organic and inorganic oxidation-resistant film and the welding layer material of refusing with the standard cubic feet per day that contracts, but not exceeds with green lacquer.
See also Fig. 4 C, be formed with conductive layer (Seed layer) 44 at this insulating protective layer 43 and perforate 431 surfaces.This conductive layer 44 is mainly as the required current conduction path of aftermentioned plated solder material, it can be made of metal, alloy or precipitation number layer metal level, as be selected from copper, tin, nickel, chromium, titanium, copper-evanohm or tin-lead alloy etc. the material in the formation group form.And, this conductive layer 44 can form by modes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating or chemical depositions, and for example methods such as the chemical vapour deposition (CVD) that promotes of sputter (Sputtering), evaporation (Evaporation), electric arc steam deposition (Arc vapor deposition), ion beam sputter (Ion beam sputtering), the molten deposition (Laser ablation deposition) of loosing of laser, electricity slurry or electroless plating form.But according to the experience of practical operation, this conductive layer 44 is relatively good with electroless copper particle formation.
See also Fig. 4 D, then on this base plate for packaging 41, form patterning resistance layer 45, make this resistance layer 45 cover the conductive layer 44 on these insulating protective layer 43 tops.This resistance layer 45 can be a photoresist layer such as dry film or liquid photoresistance (Photoresist) for example; it utilizes modes such as printing, spin coating or applying to be formed at this conductive layer 44 surfaces; again by modes such as exposure, development patterning in addition; make this resistance layer 45 only cover the conductive layer 44 on these insulating protective layer 43 tops; and expose outside and a plurality ofly will electroplate perforate 451, and respectively this to be electroplated perforate 451 and is formed on position that should electric connection pad 421.
See also Fig. 4 E, again this base plate for packaging 41 is electroplated (Electroplating) operation,, form conductive pole 46 will electroplate at this to electroplate in perforate 451 because these conductive layer 44 tool conductive characteristics can be used as current conduction path when electroplating.Wherein the material of this conductive pole 46 can be a kind of such as in the metals such as lead, tin, silver, copper, gold, bismuth, antimony, zinc, nickel, zirconium, magnesium, indium, tellurium and gallium.But, according to the experience of practical operation and since copper be the maturation plated material and cost lower, therefore, this conductive pole 46 is preferable with what be made of electro-coppering, but is not limited to this.In addition; these conductive pole 46 apical margins can be higher than the height of this insulating protective layer perforate 431; the height that also can not be higher than this insulating protective layer perforate 431, it is that example describes that the accompanying drawing of present embodiment protrudes in this insulating protective layer perforate 431 with these conductive pole 46 apical margins, but is not as limit.
See also Fig. 4 F, then can be in these conductive pole 46 enterprising electroplating (Electroplating) operations, because this conductive pole 46 has conductive characteristic,, form soldering tin material 47 on this conductive pole 46, to electroplate still with the current conduction path of this conductive layer 44 when electroplating.Wherein, this soldering tin material 47 can be the alloy that mixture constituted of the element that is selected from the cohort that lead, tin, silver, copper, gold, bismuth, antimony, zinc, nickel, zirconium, magnesium, indium, tellurium and gallium constitute.
See also Fig. 4 G, also this resistance layer 45 can be removed.Wherein, belong to prior art, so no longer narration owing to remove the operation of this resistance layer 45.
See also Fig. 4 H, then can remove not by the conductive layer 44 of this conductive pole 46 and 47 coverings of this soldering tin material, retain the conductive pole 46 and this soldering tin material 47 parts that cover on this electric connection pad 421 by operations such as for example etchings.In etching work procedure, because etching solution except removable this conductive layer 44, also can produce etching action to this conductive pole 46, and this conductive pole 46 of order produces side etching phenomenon.Therefore, the conductive pole behind etching work procedure 46 forms section poor (Step) with soldering tin material 47.
This conductive layer 44 also can be selected rete as thin as a wafer, and is long and destroy established circuit to avoid required etching period.Also can select to form thicker conductive layer 44 among the present invention, pass through, be shortened electroplating time and preferable electroplating effect is arranged to quicken electric current.And, even produce side etching phenomenon, also be unlikely and destroy established circuit.Simultaneously, owing to form thicker conductive layer 44 among the present invention, and be formed with conductive pole 46 with certain altitude, can quicken electric current passes through, more reduce the use amount of this soldering tin material 47, and such as having preferable reliability, preferable electroplating effect can be provided and prevent the soldering tin material plating, solve the shortcoming of prior art for the made conductive pole 46 of copper metal.
As shown in the figure, the pre-scolding tin structure of using the conductor package substrate of method for making gained of the present invention comprises a plurality of electric connection pads 421, conductive layer 44, conductive pole 46 and this soldering tin material 47.This electric connection pad 421 is formed at the surface of this substrate 41, and is formed with this insulating protective layer 43 around this electric connection pad 421, and this insulating protective layer 43 has a plurality of perforates to expose outside this electric connection pad 421.This conductive layer 44 is complete to be covered in this electric connection pad 421 upper surfaces, and this conductive pole 46 is to form and be covered on this conductive layer 44 through electroplating, and 47 of this soldering tin materials are formed on this conductive pole 46.Wherein, this conductive layer 44 can be selected the metal level such as the copper layer, and this conductive pole 46 then can be selected the metal column such as the copper post, but all non-as limit.
See also Fig. 4 I, afterwards, also can under the temperature conditions of soldering tin material 47 fusions that are enough to make this electroplating deposition, carry out reflow (Reflow-soldering) operation, make this soldering tin material 47 form on this conductive pole 46 through reflow pre-solder bump 47 '.As shown in the figure, this pre-solder bump 47 ' can pass through this conductive pole 46 and these electric connection pad 421 conductings, and the upper surface of this pre-solder bump 47 ' this conductive pole 46 of complete coating.Wherein, can be according to these soldering tin material 47 melting degrees of required pre-solder bump 47 ' Height Adjustment, to adjust the error on the height thus.
The pre-scolding tin structure and the method for making thereof of conductor package substrate of the present invention mainly are by twice plating, on the substrate electric connection pad, form conductive pole and soldering tin material successively, on this electric connection pad, to electroplate the lower conductive pole of material cost earlier, afterwards again with this conductive layer and this conductive pole as current conduction path, on this conductive pole, electroplate higher but the soldering tin material that use amount is less of material cost.After removing this resistance layer and the conductive layer that is not covered, this soldering tin material is carried out the reflow operation, to form the pre-solder bump of this conductive pole upper surface of complete coating by this conductive pole and soldering tin material.
Therefore, mainly be to utilize plating mode to form the lower conductive pole of material cost earlier in the operation of the present invention,, can effectively reduce required soldering tin material use amount to replace the part soldering tin material by this conductive pole, thereby reduce cost, and can as prior art, not destroy established circuit.Use the present invention, not only can avoid in the existing mould printing operation, when electric connection pad size and spacing were dwindled, the perforate of the template process cost that is caused that must thereupon diminish improved and technical bottleneck, and need confirm that mould printing number of times and cleaning problems cause shortcomings such as operation inconvenience.
Simultaneously, because the conductive pole 46 behind etching work procedure is subjected to lateral erosion, so the interval (Pad Distance) of this conductive pole 46 can be enlarged, not only can avoid the copper ion migration phenomenon between this conductive pole, allow to have less spacing (Pad Pitch) between electric connection pad, the pre-scolding tin structure of the conductor package substrate of thin space more can be provided by method for making of the present invention.And, because the 46 required times of conductive pole of electroplating such as the copper post are shorter than the required time of plated solder material, the conductive pole 46 that the present invention elder generation plated material cost is lower and rate of deposition is higher can more shorten required activity time when reducing material cost, quicken the process of operation.
In addition, on conductive layer, form this conductive pole re-plating soldering tin material earlier by utilizing in the operation of the present invention, can effectively prevent existing the plating when forming soldering tin material, because of electroplate liquid makes soldering tin material the plating resistance layer that is covered on this conductive layer is produced plating, and do not have prior art produces bridge formation when reflow phenomenon.
Accompanying drawing of the present invention is only represented with the part electric connection pad, in fact this electric connection pad and the number of scolding tin in advance, it is the surface of designing and be distributed in base plate for packaging according to the needs of actual operation, and this operation may be implemented on the one-sided or bilateral of base plate for packaging, certainly, the general circuit plate also can be implemented the illustrated technology of the present invention if any careful circuit and the wires design that forms pre-scolding tin demand.
Claims (27)
1. the pre-scolding tin structure of a conductor package substrate is characterized in that, this pre-scolding tin structure comprises at least:
Electric connection pad is formed at the surface of conductor package substrate;
Conductive pole is formed on this electric connection pad; And
Soldering tin material is formed on this conductive pole.
2. pre-scolding tin structure as claimed in claim 1 is characterized in that, this pre-scolding tin structure also comprises:
Conductive layer, between electric connection pad and conductive pole, and complete this electric connection pad upper surface that is covered in of this conductive layer.
3. pre-scolding tin structure as claimed in claim 1 or 2 is characterized in that, be formed with insulating protective layer around this electric connection pad, and this insulating protective layer has a plurality of perforates to expose outside this electric connection pad.
4. pre-scolding tin structure as claimed in claim 1 is characterized in that, this conductive pole apical margin is less than or equal to this insulating protective layer perforate height.
5. pre-scolding tin structure as claimed in claim 1 is characterized in that this conductive pole apical margin is higher than this insulating protective layer perforate.
6. pre-scolding tin structure as claimed in claim 1 or 2 is characterized in that, this conductive pole can be made of metal materials such as being selected from lead, tin, silver, copper, gold, bismuth, antimony, zinc, nickel, zirconium, magnesium, indium, tellurium and gallium.
7. pre-scolding tin structure as claimed in claim 2 is characterized in that this conductive layer can be made of a kind of material of copper, tin, nickel, chromium, titanium, copper-evanohm or group that tin-lead alloy constitutes.
8. pre-scolding tin structure as claimed in claim 1 is characterized in that, this soldering tin material can be selected from the alloy that lead, tin, silver, copper, gold, bismuth, antimony, zinc, nickel, zirconium, magnesium, indium, tellurium and gallium constitute the mixture formation of the element in the group.
9. pre-scolding tin structure as claimed in claim 1 is characterized in that, this soldering tin material carries out forming pre-scolding tin after the reflow operation.
10. pre-scolding tin structure as claimed in claim 5 is characterized in that the section of being formed with is poor between this conductive pole and this soldering tin material.
11. pre-scolding tin structure as claimed in claim 9 is characterized in that this pre-scolding tin complete packet is covered the upper surface of this conductive pole.
12. the method for making of the pre-scolding tin structure of a conductor package substrate is characterized in that, this method for making comprises:
Provide at least one surface to be formed with the base plate for packaging of a plurality of electric connection pads;
On this base plate for packaging surface, form insulating protective layer, and this insulating protective layer have a plurality of perforates to expose outside this electric connection pad;
In this insulating protective layer perforate, form conductive pole and soldering tin material successively.
13. the method for making of pre-scolding tin structure as claimed in claim 12 is characterized in that, this method for making also comprises:
Form conductive layer at this insulating protective layer and open surface, and on this conductive layer, form the patterning resistance layer, will electroplate perforate to define; And
To electroplate in the perforate to electroplate successively at this and form conductive pole and soldering tin material.
14. the method for making as claim 12 or 13 described pre-scolding tin structures is characterized in that, the apical margin of this conductive pole is not higher than this insulating protective layer perforate height.
15. the method for making as claim 12 or 13 described pre-scolding tin structures is characterized in that, the apical margin of this conductive pole is higher than this insulating protective layer perforate.
16. the method for making of pre-scolding tin structure as claimed in claim 13 is characterized in that, this method for making also comprises the step that removes this resistance layer and the conductive layer that is not covered by this conductive pole and this soldering tin material.
17. the method for making of pre-scolding tin structure as claimed in claim 13 is characterized in that, this method for making removes not by the conductive layer of this conductive pole and the covering of this soldering tin material by etching work procedure.
18. the method for making as claim 16 or 17 described pre-scolding tin structures is characterized in that, the section of being formed with is poor between this conductive pole and this soldering tin material.
19. the method for making as claim 16 or 17 described pre-scolding tin structures is characterized in that, this method for making also comprises carries out the reflow operation to form the step of pre-scolding tin to this soldering tin material.
20. method for making as claim 12 or 13 described pre-scolding tin structures; it is characterized in that; arbitrary mode of this method for making utilization printing, spin coating and applying; this insulating protective layer is coated on this substrate surface; relend by the patterning operation and make this insulating protective layer cover this conducting wire, make this electric connection pad be revealed in the surface of this substrate.
21. the method for making of pre-scolding tin structure as claimed in claim 13 is characterized in that, this conductive layer is as electroplating the required current conduction path of this conductive pole.
22. the method for making of pre-scolding tin structure as claimed in claim 13 is characterized in that, this resistance layer is that the photoresist layer of dry film and liquid photoresistance constitutes a kind of in the cohort.
23. the method for making of pre-scolding tin structure as claimed in claim 13 is characterized in that, arbitrary mode of this resistance layer utilization printing, spin coating or applying is formed at this conductive layer surface, and carries out patterning by exposure, development.
24., it is characterized in that this conductive pole can be made of metals such as being selected from lead, tin, silver, copper, gold, bismuth, antimony, zinc, nickel, zirconium, magnesium, indium, tellurium and gallium as claim 12 or 13 described pre-scolding tin structures.
25. pre-scolding tin structure as claimed in claim 13 is characterized in that this conductive layer can be made up of a kind of material that is selected from copper, tin, nickel, chromium, titanium, copper-evanohm or group that tin-lead alloy constitutes.
26., it is characterized in that this soldering tin material can be made of the alloy that mixture constituted of the element in the cohort lead, tin, silver, copper, gold, bismuth, antimony, zinc, nickel, zirconium, magnesium, indium, tellurium and gallium as claim 12 or 13 described pre-scolding tin structures.
27. pre-scolding tin structure method for making as claimed in claim 19 is characterized in that this pre-scolding tin complete packet is covered the upper surface of this conductive pole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100042049A CN100369242C (en) | 2004-02-10 | 2004-02-10 | Pre-soldering arrangement for semiconductor packaging substrate and method for making same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100042049A CN100369242C (en) | 2004-02-10 | 2004-02-10 | Pre-soldering arrangement for semiconductor packaging substrate and method for making same |
Publications (2)
| Publication Number | Publication Date |
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| CN1655343A true CN1655343A (en) | 2005-08-17 |
| CN100369242C CN100369242C (en) | 2008-02-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100042049A Expired - Fee Related CN100369242C (en) | 2004-02-10 | 2004-02-10 | Pre-soldering arrangement for semiconductor packaging substrate and method for making same |
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| CN (1) | CN100369242C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102202827A (en) * | 2010-07-20 | 2011-09-28 | 联发软件设计(深圳)有限公司 | A tin pre-coating method used for a multicolumn quad flat no-lead chip and a rework method |
| CN101567355B (en) * | 2008-04-22 | 2011-11-30 | 欣兴电子股份有限公司 | Semiconductor packaging base plate and manufacturing method thereof |
| CN103091912A (en) * | 2011-11-07 | 2013-05-08 | 瀚宇彩晶股份有限公司 | Array substrate, liquid crystal panel with array substrate and manufacturing method of liquid crystal panel |
| CN107919547A (en) * | 2017-10-17 | 2018-04-17 | 歌尔科技有限公司 | A kind of charging interface and smart machine |
| CN114717613A (en) * | 2022-04-13 | 2022-07-08 | 长电科技管理有限公司 | Processing method for realizing leadless electroplating by using conductive film and substrate structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2751912B2 (en) * | 1996-03-28 | 1998-05-18 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| KR100255476B1 (en) * | 1997-06-30 | 2000-05-01 | 김영환 | Ball grid array package |
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2004
- 2004-02-10 CN CNB2004100042049A patent/CN100369242C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101567355B (en) * | 2008-04-22 | 2011-11-30 | 欣兴电子股份有限公司 | Semiconductor packaging base plate and manufacturing method thereof |
| CN102202827A (en) * | 2010-07-20 | 2011-09-28 | 联发软件设计(深圳)有限公司 | A tin pre-coating method used for a multicolumn quad flat no-lead chip and a rework method |
| CN103091912A (en) * | 2011-11-07 | 2013-05-08 | 瀚宇彩晶股份有限公司 | Array substrate, liquid crystal panel with array substrate and manufacturing method of liquid crystal panel |
| CN103091912B (en) * | 2011-11-07 | 2017-03-01 | 瀚宇彩晶股份有限公司 | Array substrate, liquid crystal panel with array substrate and manufacturing method of liquid crystal panel |
| CN107919547A (en) * | 2017-10-17 | 2018-04-17 | 歌尔科技有限公司 | A kind of charging interface and smart machine |
| CN114717613A (en) * | 2022-04-13 | 2022-07-08 | 长电科技管理有限公司 | Processing method for realizing leadless electroplating by using conductive film and substrate structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100369242C (en) | 2008-02-13 |
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