CN1652334A - Chip stage package for integrated multi-chip - Google Patents
Chip stage package for integrated multi-chip Download PDFInfo
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- CN1652334A CN1652334A CN 200410002598 CN200410002598A CN1652334A CN 1652334 A CN1652334 A CN 1652334A CN 200410002598 CN200410002598 CN 200410002598 CN 200410002598 A CN200410002598 A CN 200410002598A CN 1652334 A CN1652334 A CN 1652334A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Wire Bonding (AREA)
Abstract
Integrated chip stage package (CSP) includes two or more single sub modules of CSP stacked in vertically. The bottommost CSP sub module in vertical stack includes array of solder ball and interconnected PCB. Vertical electrical connection is realized between CSP at previous stage and CSP at next stage through wires connection between joint bonding pad located at perimeter of extend part of substrate in previous stage and joint bonding pad located at relevant part in next stage. Stacked sub modules are stuck through thin binding material, and jointed perimeters are sealed through sealant. Height of stacked CSP is smaller than height of summarized from each single package. Array of solder ball in use for interconnection between CSPs is packed by itself.
Description
Technical field
Present invention relates in general to a kind of multilevel semiconductor wafer-level package integrated, that save the space, and more special, relate to a kind of mass storage semiconductor packages that is used for the interconnected welded ball array of plate level of using minimum number.
Background technology
For good electrical property and conserve space, in many high density dual-inline memory modules (DIMM), use wafer-level package (CSP) now, because package dimension is no more than 20% of bare chip size usually.Compare other semiconductor package types such as lead frame type thin-type small-size encapsulation (TSOP) or ball grid array (BGA) encapsulation, the CSP encapsulation is littler in fact in size, can place a large amount of memory package on the DIMM module like this and reach bigger memory capacity.
When the monolithic integrated circuit of common semiconductor packages is arranged all free spaces that occupy on the printed substrate (PWB) that uses in the DIMM module, the conventional method that increases memory density is by using the encapsulation of vertical stacking, such as the U.S. patent No.6 that is that on June 11st, 2002 authorized, 404, those that describe in 662 are wherein expressed the memory package of piling up that is used for the Rambus memory package.Be the U.S. patent No.6 that authorizes May 29 calendar year 2001, disclose a kind of extremely thin multicore sheet package assembling in 239,496.Be the U.S. patent No.6 that authorized on September 24th, 2002, described a kind of a plurality of microballoon grid array (FBGA) assembly that piles up in 455,928.But in this stack assemblies, usually by the identical FBGA encapsulation of vertical stacking being come at the top that an encapsulation is placed on another in mode as shown in Figure 1.
Comprise that at encapsulation 10-1 that piles up shown in the assembly of Fig. 1 and 10-2 many (for example, two) one are positioned at integrated circuit (IC) chip 1 above another.Join the IC chip 1 of each encapsulation 10-1 that piles up and 10-2 to substrate 3 by die attach adhesive 5.Each substrate 3 is positioned on the substrate metal circuit 7, and each metallization circuit 7 is supported by the array along the conductive weld 9 of the outer circumferential of encapsulation.The soldered ball 9 that is associated with top IC Chip Packaging 10-1 is electrically connected at respective electrical pad place that links together by next stage substrate 3 and the soldered ball 9 that is associated with following IC Chip Packaging 10-2.Like this, can understand that the upper level of the IC chip 1 that carries separately and next stage encapsulation 10-1 and 10-2 are separated each other by soldered ball 9.Gold bonding wire 11 is outstanding from the ventricumbent i/o pads 13 on each IC chip 1, so that be attached to substrate metal circuit 7 by the opening in the substrate 3 that is formed on upper level and next stage encapsulation 10-1 and 10-2.Gold bonding wire 11 is centered on by suitable protective sealant 15.
Therefore, the combined altitudes of the height of the package assembling that piles up of Fig. 1 and independent IC Chip Packaging 10-1 and 10-2 equates.In addition, by on each independent encapsulation 10-1 and 10-2, using the array of soldered ball 9 for the electrical interconnection that is encapsulated into encapsulation, usually on thickness greater than the ball height of semiconductor chip 1 and its support substrates, with above making in vertical stacking and below IC Chip Packaging 10-1 and 10-2 between form gap 16, unless between the encapsulation of adjacent stacked the usage space packing material.Do not use the words of this space packing material, the encapsulation 10-1 and the 10-2 that pile up can have the weak structure globality because the soldered ball 9 of only interconnected outer circumferential along assembly and between welded ball array cantilever or even part hang thin, flimsy IC chip.
Another interconnected deficiency of circumference soldered ball as shown in Figure 1 is that the overall size that must increase encapsulation is held the big relatively soldered ball that is positioned at along the circumference place.But the size of the package assembling that piles up of Fig. 1 is greater than suitable one chip CSP encapsulation 10-1 or 10-2 with the welded ball array that is located immediately under the IC chip.The validity that the package assembling that the increase of this size has reduced to pile up encapsulates as the small chip level.Therefore, need a kind of package assembling that piles up, it compares one chip encapsulation the not increasing plane domain (in the x-y dimension) with the assembly that directly appends to the soldered ball under the IC chip.In other words, need have a kind of multistage package assembling that piles up, it only increases the zone that is occupied by suitable one chip encapsulation slightly.The package assembling that piles up must also have and is used for handling the strong structural integrity and the long reliability of assembling.
In this identical consideration, the application in portable electric appts need to continue the IC Chip Packaging thinner, lighter, and structurally firmer.Therefore, need be provided for improved firm in structure, the low profile, high density of DRAM memory and other application, the CSP encapsulation of piling up.Compare common piled up CSP assembly, improved encapsulation should have lower total profile (highly) and better robustness and hardness, and the circumference soldered ball that wherein common piled up CSP assembly has between the one chip encapsulation that is in independent vertical stacking as shown in Figure 1 is interconnected.For the maximization of flexibility, before assembling, the one chip encapsulation should have the selection that independent usefulness acts on the free-standing one chip encapsulation of monolithic integrated circuit board component.Perhaps, when needs, free-standing one chip should be assembled together forms vertical integrated multistage wafer-level package, this multistage wafer-level package have with one chip package essences before encapsulation on the identical area of coverage.In addition, when the welded ball array that adheres to separately that uses independent encapsulation is stacked them, the total height of integrated package assembling should less than independent encapsulation and.
Summary of the invention
In general, by being stacked on, one of two or more one chip CSP sub-component assemble vertical integrated multicore sheet CSP encapsulation above another.With sealant material black box circumference, the package assembling of finishing like this that piles up has the outward appearance of single CSP encapsulation afterwards, and wherein single CSP encapsulates to have and is used for the identical array that the plate level is assembled to the interconnected soldered ball of printed substrate (PWB).By using existing chip adhesive bonding material that upper level and next stage CSP encapsulates subunits part are bonded together.Have among the embodiment that two Chip Packaging pile up at one, upper level and next stage encapsulates subunits part all are one chip memory ball grid array (mBGA), just, its characteristics for the configuration that faces down in conjunction with center bonding pads and be suitable for being used in CSP encapsulation in the DRAM memory module.
More special, identical in fact top and following one of free-standing CSP encapsulates subunits part is stacked on the assembly that forms the two integrated encapsulation stackings of saving the space above another.Above with following free-standing encapsulates subunits part in each all comprise the single integrated circuit (IC) chip that joins thin substrate to.The i/o pads that is positioned under the chip electrically is connected with line bond pad on substrate by the mode of gold thread.Line bond pad on substrate is sealed by protective sealant.The periphery bond pad is positioned at the top of substrate and the bottom that the soldered ball bond pad is positioned at substrate.Be positioned at the periphery bond pad of opposite side of substrate and soldered ball bond pad by electric the linking together of substrate.On bottom the soldered ball bond pad there of substrate, adhere to welded ball array.The upper level of the assembly of two encapsulation stackings and next stage CSP encapsulates subunits part differ from one another, and its difference is that the substrate of next stage sub-component and the periphery bond pad on the next stage substrate omit long than the substrate of upper level sub-component and the line bond pad above that.Difference on this length for line engage machine carry out upper level and above the next stage CSP encapsulates subunits part and below the line bond pad between vertical line to engage be necessary.
Upper level CSP encapsulates subunits part is installed in and adhesively is bonded on the next stage encapsulates subunits part, still, without any soldered ball between them.Therefore, integrated stacked package is formed with a top and following CSP encapsulates subunits part that directly is stacked on another.Come line to engage the CSP encapsulates subunits part that piles up by adhering to gold thread between the periphery bond pad on the substrate of superincumbent and following CSP encapsulates subunits part.Afterwards sealant is applied to the whole assembly that piles up and comes blockade line, thus the adhesive joint of reinforcement between upper level and next stage sub-component.In the assembly of finishing that piles up, only along the soldered ball of bottom attach list an array of the substrate of next stage CSP encapsulates subunits part.
Though the assembly that preferably piles up has the individual one to one CSP encapsulates subunits part that is stacked on another, also can the CSP encapsulates subunits part of any suitable number (for example, four) is integrated in vertical stacking with the alternate manner according to explanation of the present invention.Therefore, integrated package assembling can comprise a plurality of identical integrated circuit (IC) chip that are stacked on other now, does not occupy the other space on the PWB simultaneously, makes it be suitable for ideally being used in the big capacity DRAM memory module.
Description of drawings
Fig. 1 shows the existing CSP of the piling up package assembling with the interconnected a plurality of arrays of circumference soldered ball;
Fig. 2 shows free-standing one chip CSP encapsulates subunits part, and it is suitable for use as the upper level sub-component that is used for improved piled-up packing assembly of the present invention;
Fig. 3 shows free-standing one chip CSP encapsulates subunits part, and it is suitable for use as the next stage sub-component that is used for improved piled-up packing assembly of the present invention;
Fig. 4 shows improved integrated piled-up packing assembly of the present invention, and it installed soldered ball on the next stage CSP of Fig. 3 encapsulates subunits part before the upper level CSP encapsulates subunits part with soldered ball and Fig. 2 adheres to;
The line that Fig. 5 shows between the upper level of the integrated piled-up packing assembly of Fig. 4 and next stage CSP encapsulates subunits part engages interconnected and sealing, and wherein integrated piled-up packing assembly has the soldered ball of the single array that adheres to along the bottom of next stage encapsulates subunits part;
Fig. 6 is the partial cutaway view of perspective of the integrated piled-up packing assembly of Fig. 5, and wherein package assembling has one to one the one chip CSP encapsulates subunits part that is stacked on above another;
Fig. 7 A and 7B show the top view of substrate band and single underlay pattern, wherein have circuit layout thereon and are used for the perimeter bond pad of the one chip CSP encapsulates subunits part of pie graph 2 and 3;
Fig. 8 shows another free-standing one chip CSP encapsulates subunits part that is used for being used in piled-up packing assembly of the present invention;
The line that Fig. 9 A and 9B show between the upper level of integrated piled-up packing assembly and next stage CSP encapsulates subunits part engages interconnected and sealing, and wherein each CSP encapsulates subunits part is according to the other assembly manufacturing of Fig. 8; And
Figure 10 shows according to of the present invention has four one an integrated piled-up packing assembly that is stacked on the CSP encapsulates subunits part above other.
Embodiment
In the accompanying drawing of Fig. 2, show the cross section of self one chip CSP encapsulation 20.As will explaining with reference to figure 4 time, but CSP encapsulation 20 also is suitable for use as the upper level encapsulates subunits parts in improved, as to save space piled-up packing assembly.The mode of integrated circuit (IC) chip 22 by bonding die attach material layer 26 is assembled to thin substrate 24.Jointing material 26 can be a flexible material, alleviates between substrate 24 and IC chip 22 because the pressure that thermal expansion produces.By the mode of example, substrate 24 can be a polyimides flexibly, the glass epoxy resin printed substrate (PWB) of Bao Xin (thin-core) lamination, perhaps liquid crystal polymer (LCP) film.The mode line of ventricumbent IC i/o pads 28 by gold thread 32 that will be positioned on the central area of IC chip 22 joins substrate lines bond pad 30 to, and wherein gold thread extends through opening in substrate 24 to be attached to pad 30.Line 32 is sealed so that protection by sealant.
The substrate 24 of one chip encapsulation 20 comprises metallised conductors circuit trace 36, and it is used to arrange from the signal of telecommunication of substrate lines bond pad 30 path to soldered ball bond pad 38 and periphery bond pad 40.At last, the array that on soldered ball bond pad 38, adheres to soldered ball 42 along the bottom of substrate 24.In the one chip of Fig. 2 encapsulation 20, periphery bond pad 40 and soldered ball bond pad 38 are positioned at the opposite side of substrate 24 and interconnected each other by the mode of electroplating ventilating hole 41.
Forward Fig. 8 to, show and have substrate 24-1 and along the one chip encapsulation 20-1 of the single metallization circuit layer 46 of the bottom of substrate 24-1.In this embodiment, periphery bond pad 48 is positioned at the same side of soldered ball line bond pad 38.On periphery bond pad 48, form opening 49, can receive gold thread (shown in Fig. 9 A and 9B) by this opening by substrate 24-1.Can opening 49 be manufactured among the substrate 24-1 in advance by the mode of for example photoetching or laser lift-off.
But Fig. 3 of accompanying drawing shows the cross section of the free-standing one chip CSP encapsulation 50 of the next stage encapsulates subunits part that also is suitable for use as in the improved piled-up packing assembly of Fig. 4.The one chip next stage encapsulation 50 of Fig. 3 structurally encapsulates 20 much at one with one chip upper level shown in Figure 2.Except the periphery bond pad 40-1 of the side extension of substrate 24-2 and next stage CSP encapsulation 50 slightly longer than those of upper level CSP encapsulation 20.The additional marginal stretch of the line bond pad 40-1 of this substrate 24-2 and next stage CSP encapsulation 50 is need be used for line to engage machine and carry out the package assembling that piles up at Fig. 5, along the edge of upper level and next stage encapsulation 20 and 50 superincumbent and below line bond pad 40 and the vertical line between the 40-1 engage.Additional length may change according to line joint machine capillary tip (capillary tip) size and the linear diameter selected.The line bond pad 40-1 that estimates next stage CSP encapsulation 50 will only encapsulate 20 line bond pad 40 long a few tenths of microns (for example, 0.1-0.2 microns) than upper level CSP.In addition, each in one chip CSP encapsulation 20 that can shop drawings 2 and the one chip CSP encapsulation 50 of Fig. 3 makes it have substrate, and wherein this substrate has with as shown in Figure 8 the mode single metallization circuit layer 46 along its bottom.
In the independent process of using, Fig. 2 and 3 independent CSP encapsulation 20 and 50 can be worked independently of one another and the array that assembling handles by their soldered balls 42 separately can be installed with existing single circuit surface and be assembled to printed substrate.But, picture has just been described, the next stage encapsulation 50 that the upper level encapsulation 20 of Fig. 2 will be compared Fig. 3 has smaller perimeter bond zone, make when encapsulates subunits part above the vertical stacking and following, the perimeter bond pad of following encapsulation outwards outstanding so that provide enough spaces be used for line engage between the superincumbent and following bond pad of machine execution to the joint that rolls off the production line.
In the accompanying drawing of Fig. 4, the upper level CSP encapsulates subunits part 20 that Fig. 2 is shown is installed in the top of the next stage CSP encapsulates subunits part 50 of Fig. 3, but does not adhere to the soldered ball that takes up space between them.In other words, before integrated assembling as shown in Figure 4, do not need the array of soldered ball 42 is attached to the upper level encapsulation 20 of Fig. 2, if but encapsulating 20 will be used as freestanding one chip encapsulation, and this will need.Applying electronic level adhesive 57 directly joins upper level encapsulates subunits part 20 to next stage encapsulates subunits part 50 and forms integrated piled-up packing assembly 55.Joint adhesive 57 can be to be placed on the upper surface of the IC chip 22 that crosses next stage encapsulates subunits part 50 or to cross the thin slice of jointing material of lower surface of the substrate 24 of upper level encapsulates subunits part 20 in as shown in Figure 4 mode.In addition, and by best the illustrating of the piled-up packing assembly 55-1 of Fig. 5, many adhesives 59 can be assigned to next stage encapsulates subunits part 50 IC chip 22 above.Come two adjacent CSP encapsulates subunits parts 20 and 50 of lamination by suitable lamination and the processing of using predetermined temperature and pressure to use adhesive 57 or 59 with an effective stacked format on another.
After the lamination, by using the suitable microelectronics level gold thread 60 that is connected, or similarly mode is come the package assembling 55-1 that piles up of line index map 5, and wherein gold thread is connected between the periphery bond pad 40-1 of exposure of the periphery bond pad 40 of exposure of upper level encapsulation 20 and next stage encapsulation 50.The encapsulation 55-1 that piles up may be also by line bond pad 40 and 40-1 by using other mutual contact mode such as, ribbon conductor, coil type engages automatically, bandedly engages welding, perhaps conductive polymer vertical interconnect.Finish after line engages, use encapsulant 62 airtight lines 60 and protection on integrated package assembling 55-1 and below encapsulates subunits part 20 and 50 between lamination.
The accompanying drawing of Fig. 6 shows by sawing, and the sealing 62 of the mode of laser cutting or perforation after band is separated the package assembling 55-1 that (singulate) pile up, its middle punch are in mode that will more detailed discussion with reference to figure 7A the time.Can the fluid sealant distribution be finished sealing by the hole opening in the band of upper level substrate 24 or by the TRANSFER MODEL method of using suitable pressing mold processing by using.The single array that adheres to conductor soldered ball 64 along the bottom of the substrate 24 of the next stage of the package assembling 55-1 that piles up encapsulation 50.
Fig. 6 also shows along the line of the microelectronics level gold thread 60 of external margin between periphery bond pad 40 and 40-1 of the substrate 24 of the upper level of the assembly 55-1 that piles up and next stage CSP encapsulates subunits part 20 and 50 and engages.The sealing of the package assembling 55-1 that piles up may be only limited to the opposed edges circumference, its center line bond pad 40 and 40-1 and line interconnected 60 are positioned at there (as shown in Figure 6), perhaps sealing may also comprise the chip surface of the exposure of upper level sub-component 20, seals all four sides at the top of 62 covering assemblies 55-1 like this.By aforesaid advantage, may realize having the integrated package 55-1 of the increase capacity of a pair of identical IC chip 1 that piles up now, and only can not increase and be encapsulated in the space that normally occupies on the printed substrate by a single CSP.
Can use (just, the independent) encapsulation that separates to be used for the whole integrating process of the stack assemblies 55-1 of shop drawings 6.But in large-scale production, this process can also be carried out with the substrate tape format, and this form is used in usually to be made in the one chip CSP encapsulation.In tape format, the backing material band that is supported by framework location thing (framing fixture) is used for assembling a plurality of integrated circuits in a batch processing.According to its size, band may comprise 10 to 50 arrays of encapsulation separately.In each substrate of substrate band, form a plurality of circuit 72 and opening 75 (shown in Fig. 7 A).The width of opening 75 influences the width of substrate conversely.For example, for substrate band, can cut opening 75 in advance and make it more bigger than pre-cut opening in being used as the band of next stage encapsulates subunits part as upper level encapsulates subunits part.
The accompanying drawing of Fig. 7 A shows the substrate band 70 that comprises a plurality of identical one chip substrates 72.The distribution of schematic diagram arrange to(for) the circuit paths of each independent substrate 72 has been shown in Fig. 7 B, and its center line bond pad 30 is positioned near the of central opening 74 and soldered ball bond pad 38 is connected by independent conductive metal trace 36 with periphery bond pad 40.
Circuit on the substrate 72 of Fig. 7 b is to be used to change from the arrangement path of the signal I/O of integrated circuit and to be used to make the bond pad of formation to be used for line engage and adhere to and be used for ball attach.In manufacture process, independent integrated circuit (IC) chip is attached to and line joins the substrate band 70 of Fig. 7 A in the mode of describing with reference to figure 2 and 3 o'clock in the above.When assembling is piled up in execution, use suitable jointing material to stack (superimpose) or be laminated to following being with on the band that is intended to the top sub-component.Use the suitable temperature and pressure extruding and the band of processing lamination.
As disclosed previously with reference to figure 8 time, (for example, substrate 24-1 20-1) may comprise the single metallization circuit layer 46 that engages along the bottom acceptance line for each upper level and next stage CSP encapsulation.In this other situation, and accompanying drawing with reference now to Fig. 9 A and 9B, form the integrated CSP package assembling 80 that piles up, upper level and the next stage substrate 24-1 of wherein a pair of free-standing CSP encapsulation 20-1 comprise single metallization circuit layer 46 and separately periphery bond pad 48 and 48-1, but wherein pad has the metal coating (finish) of line joint such as nickel and gold.Usually electronickelling/gold plating still also can be by chemical deposit method deposition.Picture is disclosed with reference to figure 8 time, remove backing material by etching or laser lift-off, for example, bring the opening of creating by substrate 24-1 making substrate in advance, thereby allow the line of microelectronics level gold thread 82 to engage and be arranged in the process that contacts with 48-1 along the perimeter bond pad 48 of the exposure of the bottom of opening 49.
Although the integrated piled-up packing assembly 55 and 58 of Fig. 4 and Fig. 9 A shows a pair of CSP encapsulates subunits part of arranging in a mode that is vertically stacked on above another, should be appreciated that the CSP encapsulation stacking of any suitable number can be reached big capacity of the present invention together, save the advantage in space.For example, the accompanying drawing of Figure 10 shows to have with one of overlapped way and is stacked on four free-standing CSP encapsulation 20-1 altogether above other, 20-2, the multistage wafer-level package assembly 90 of 20-3 and 20-4.The bottom that only needs soldered ball 92 with single array to join nethermost CSP encapsulation 20-4 to minimizes the vertical height of encapsulation 90.In addition, just as when with reference to figure 2 and 3 first as described in, make the substrate 24-1 of stacked package, 24-2,24-3, gradually longer of the circumference of 24-4, thus can engage the line that machine finish between longer one by one periphery bond pad by line before finishing encapsulation 90 and engage using sealant 94.
Above-describedly integrated pile up CSP encapsulation 55,80 and all be relative little size with 90 characteristics.In other words, each encapsulation of piling up will have the outward appearance of seeing single encapsulation from the outside and less than with two independent encapsulation otherwise one be stacked on above another and between them, be placed with the interconnected height of soldered ball.The package assembling that piles up of the present invention is to be suitable for ideally being used in the large memories capacity DRAM memory module.In this situation, the upper level of assembly and next stage encapsulate preferably one chip memory ball grid array (mBGA), and this array has the center bonding pads that engages with the configuration that faces down shown in Fig. 2 and 3.
Claims (18)
1. an integrated wafer-level package assembly comprises at least the first and second wafer-level package that are placed on another, and first in wherein said first and second wafer-level package comprises:
Integrated circuit (IC) chip;
Substrate, described integrated circuit (IC) chip join on this substrate, and described substrate has top side and bottom side and outwards outstanding and exceed the extension of integrated circuit (IC) chip;
A plurality of soldered ball bond pads that are positioned at the bottom side of substrate;
A plurality of periphery bond pads that are positioned on the substrate extension;
In interconnected conductive signal trace on the described substrate and between described integrated circuit (IC) chip and described a plurality of periphery bond pad; And
Be attached to an interconnected array of soldered ball of described a plurality of respective solder ball bond pads in the soldered ball bond pad of described substrate bottom side, can be attached to printed substrate by its described first wafer-level package.
2. integrated wafer-level package assembly as claimed in claim 1, also comprise the ventricumbent signal i/o pads and a plurality of substrate lines bond pad that is installed in the bottom side of substrate that are installed on the described integrated circuit (IC) chip, wherein this pad is by described conductive signal trace and described a plurality of soldered ball bond pad and periphery bond pad electrical interconnection, and described output/o pads and described a plurality of substrate lines bond pad are electrically connected.
3. integrated wafer-level package assembly as claimed in claim 1, the top side that wherein said a plurality of periphery bond pads are positioned at substrate make that it is in substrate its be provided with the opposite side of described a plurality of soldered ball bond pads.
4. integrated wafer-level package assembly as claimed in claim 1, the bottom side that wherein said a plurality of periphery bond pads are positioned at substrate make itself and the same same side that is in substrate of described a plurality of soldered ball bond pads.
5. integrated wafer-level package assembly as claimed in claim 1, in wherein said a plurality of periphery bond pad, described a plurality of soldered ball bond pads and the described conductive signal trace each is positioned on the single side of substrate, and described single side is the bottom side of substrate.
6. integrated wafer-level package assembly as claimed in claim 1, second in wherein said first and second wafer-level package comprises:
Integrated circuit (IC) chip;
Substrate, described integrated circuit (IC) chip join on this substrate, and described substrate has top side and bottom side and outwards outstanding and exceed the extension of integrated circuit (IC) chip;
A plurality of soldered ball bond pads that are positioned at the bottom side of substrate;
A plurality of periphery bond pads that are positioned on the substrate extension; And
Interconnected conductive signal trace between on the described substrate and in described integrated circuit (IC) chip and described a plurality of soldered ball bond pad and periphery bond pad each,
Described second wafer-level package is positioned on described first wafer-level package, and, make with vertical stacking and do not exist the interconnected mode of soldered ball between them to arrange described first and second wafer-level package not with the interconnected described a plurality of soldered ball bond pads that are attached on the bottom side of the substrate of described second wafer-level package of soldered ball.
7. integrated wafer-level package assembly as claimed in claim 6, wherein said second wafer-level package directly adhesively joins described first wafer-level package to, and does not exist soldered ball interconnected between them.
8. integrated wafer-level package assembly as claimed in claim 7, wherein said second wafer-level package directly adhesively joins described first wafer-level package to by the mode of bonding material layer, and wherein bonding material layer is between the integrated circuit (IC) chip of the substrate of described second wafer-level package and described first wafer-level package.
9. integrated wafer-level package assembly as claimed in claim 7, wherein said second wafer-level package directly adhesively joins described first wafer-level package to by the mode of drops of adhesive, and wherein drops of adhesive is between the integrated circuit (IC) chip of the substrate of described second wafer-level package and described first wafer-level package.
10. integrated wafer-level package assembly as claimed in claim 6, the substrate of wherein said second wafer-level package is shorter than the substrate of described first wafer-level package.
11. integrated wafer-level package assembly as claimed in claim 10 also is included in the electric conductor that connects between a plurality of periphery bond pads on the substrate extension of described second wafer-level package and a plurality of periphery bond pads on the substrate extension in described first wafer-level package.
12. integrated wafer-level package assembly as claimed in claim 11, comprise that also wherein said electric conductor connects around vertical stacking that is formed by described first and second wafer-level package and the sealant that seals described electric conductor between a plurality of periphery bond pads separately on the substrate extension in described first and second wafer-level package.
13. integrated wafer-level package assembly as claimed in claim 11, wherein the described electric conductor that connects between a plurality of periphery bond pads separately in described first and second wafer-level package is a microelectronics level gold thread.
14. integrated wafer-level package assembly as claimed in claim 11, a plurality of periphery bond pads separately of wherein said electric conductor and described first and second wafer-level package are connected by the hole, and wherein the hole forms on the substrate extension of described first and second wafer-level package that are provided with described a plurality of periphery bond pads thereon.
15. integrated level package assembling, comprise a plurality of wafer-level package sub-components of arranging in a mode that is vertically stacked on another, each of described a plurality of wafer-level package sub-components has the integrated circuit (IC) chip that is installed on the substrate, thereby one substrate is directly installed on below described wafer-level package sub-component adjacent the top of one integrated circuit (IC) chip above the described wafer-level package sub-component in vertical stacking, and each substrate has a plurality of periphery bond pads and a plurality ofly is connected described a plurality of periphery bond pad and is installed in conductive signal trace between the integrated circuit (IC) chip on the described substrate;
A plurality of soldered ball bond pads are positioned on the substrate of one of bottom of described vertical stacking of wafer-level package sub-component, and
The interconnected array of soldered ball is attached to corresponding described a plurality of soldered ball bond pads of described nethermost wafer-level package sub-component, can be attached to printed substrate by its described vertical stacking.
16. integrated wafer-level package assembly as claimed in claim 15, the substrate of each of wherein said a plurality of wafer-level package sub-components has outwards outstanding and exceeds the extension that is installed in the integrated circuit (IC) chip on the described substrate, a plurality of line bond pads of each substrate are positioned on the extension of this substrate, and one substrate extension is shorter than one substrate extension below described wafer-level package sub-component adjacent above the described wafer-level package sub-component in vertical stacking.
17. integrated wafer-level package assembly as claimed in claim 16 further is included in above the described wafer-level package sub-component in vertical stacking the electric conductor that connects between a plurality of periphery bond pads on one the substrate extension and a plurality of periphery bond pads on one substrate extension below described wafer-level package sub-component adjacent.
18. integrated wafer-level package assembly as claimed in claim 17, further comprise and enclose vertical stacking that is formed by described wafer-level package sub-component and the sealant that seals electric conductor at least, wherein electric conductor connects between a plurality of periphery bond pads separately on the substrate extension at described a plurality of wafer-level package sub-components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410002598 CN100533728C (en) | 2004-02-02 | 2004-02-02 | Chip stage package for integrated multi-chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410002598 CN100533728C (en) | 2004-02-02 | 2004-02-02 | Chip stage package for integrated multi-chip |
Publications (2)
| Publication Number | Publication Date |
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| CN1652334A true CN1652334A (en) | 2005-08-10 |
| CN100533728C CN100533728C (en) | 2009-08-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410002598 Expired - Lifetime CN100533728C (en) | 2004-02-02 | 2004-02-02 | Chip stage package for integrated multi-chip |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236959B (en) * | 2007-02-02 | 2010-05-19 | 南茂科技股份有限公司 | Encapsulation structure for multi-chip interleaving stack |
| CN101770439A (en) * | 2009-01-05 | 2010-07-07 | 台湾积体电路制造股份有限公司 | Electronic system and operation method thereof |
| CN101752268B (en) * | 2008-12-05 | 2011-08-03 | 台湾积体电路制造股份有限公司 | Method of making integrated circuits |
| CN101477980B (en) * | 2008-01-02 | 2012-08-08 | 海力士半导体有限公司 | Stacked wafer level package having a reduced size |
| US8847377B2 (en) | 2008-01-02 | 2014-09-30 | SK Hynix Inc. | Stacked wafer level package having a reduced size |
-
2004
- 2004-02-02 CN CN 200410002598 patent/CN100533728C/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236959B (en) * | 2007-02-02 | 2010-05-19 | 南茂科技股份有限公司 | Encapsulation structure for multi-chip interleaving stack |
| CN101477980B (en) * | 2008-01-02 | 2012-08-08 | 海力士半导体有限公司 | Stacked wafer level package having a reduced size |
| US8847377B2 (en) | 2008-01-02 | 2014-09-30 | SK Hynix Inc. | Stacked wafer level package having a reduced size |
| CN101752268B (en) * | 2008-12-05 | 2011-08-03 | 台湾积体电路制造股份有限公司 | Method of making integrated circuits |
| CN101770439A (en) * | 2009-01-05 | 2010-07-07 | 台湾积体电路制造股份有限公司 | Electronic system and operation method thereof |
| CN101770439B (en) * | 2009-01-05 | 2015-09-16 | 台湾积体电路制造股份有限公司 | Electronic system and its method of operating |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100533728C (en) | 2009-08-26 |
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