CN1632942B - Technique for porous filling damascene using light sensitive material - Google Patents
Technique for porous filling damascene using light sensitive material Download PDFInfo
- Publication number
- CN1632942B CN1632942B CN 200410093457 CN200410093457A CN1632942B CN 1632942 B CN1632942 B CN 1632942B CN 200410093457 CN200410093457 CN 200410093457 CN 200410093457 A CN200410093457 A CN 200410093457A CN 1632942 B CN1632942 B CN 1632942B
- Authority
- CN
- China
- Prior art keywords
- light sensitive
- sensitive material
- filling
- damascus
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
This invention belongs to integration circuit process technique field and in detail is a process by use light sensitive hole to fill the Damascus. The Damascus is a new metal distribution technique. This invention uses light sensitive hole to fill the Damascus to improve the filling process greatly.
Description
Technical field
The invention belongs to the integrated circuit processing technique field, be specifically related to use the technology of light sensitive material porous filling damascene.
Background technology
Follow the continuous progress of integrated circuit fabrication process, it is more and more littler that the volume of semiconductor device is just becoming, and they be coupled together also difficult more.In in the past 30 years, semi-conductor industry circle all is with the material of aluminium as interface unit, but along with the dwindling of chip, industrial quarters needs thinner, thinner connection, and the high-ohmic of aluminium also more and more is difficult to meet demand.And under the situation of high density ultra large scale integrated circuit, high resistance cause easily electronics take place " wire jumper ", near the device causing produces wrong on off state.That is to say, with aluminium as the chip of lead may produce can't with the function situation of prediction, stability is also relatively poor simultaneously.On so trickle circuit, the transmission signals speed of copper is faster and more stable than aluminium.
The metal connecting line of tradition integrated circuit is to make plain conductor in the etching mode of metal level, carries out the filling of dielectric layer, the chemico-mechanical polishing of dielectric layer then, repeats above-mentioned operation, and then successfully carries out the multiple layer metal stack.But when the material of plain conductor converts the lower copper of resistance aluminium to by aluminium since the dried quarter of copper difficulty comparatively, therefore new embedding technique is just very necessary concerning the processing procedure of copper.
Embedding technique is called Damascus technics again, and the word source is from the well-known Damascus, Syria city of embedding technique, and the daggers and swords of being cast there before 2,500 years just use this technology to forge.Embedding technique is the figure that at first the etching plain conductor is used on dielectric layer, and then fills metal, again metal is carried out metal mechanical polishing, repeats above-mentioned operation, and then successfully carries out the multiple layer metal stack.The main characteristics of embedding technique are the etching technics that does not need to carry out metal level, and these promotion and application to process for copper are very important.
Ic manufacturing technology has striden into the epoch of 130nm.Present most copper wirings are in the 180-130nm operation stage, and about 40% logical circuit production line can be used the copper Wiring technique.Arrived the 90nm operation stage, 90% semiconductor production line employing copper Wiring technique has then been arranged.Damascus mosaic technology that adopts Cu-CMP is present unique maturation and the copper graphical technology of successful Application in the IC manufacturing.General common two kinds of mosaic texture (damascene structure): single inlay structure and dual-damascene structure.Single inlay structure (single damascene structure) (Fig. 1) and dual-damascene structure (double damask structure) (Fig. 2).Single inlay structure only is that the production method of single-layer metal lead is changed into mosaic mode (dielectric layer etching+metal filled) by traditional (metal etch+dielectric layers fills) mode as previously mentioned, and is comparatively simple.Dual-damascene structure then is that through hole and plain conductor are combined, and so only needs metal filled step together, can simplify processing procedure, but the also corresponding complexity of the making of mosaic texture, difficulty.The common method of making dual-damascene structure generally has: 1, all-pass hole precedence method (Full VIA First) 2, half via-first method (Partial VIA First) 3, plain conductor precedence method (Full Trench First) 4, self aligned approachs (Self-alignment method) etc. are several.But above-mentioned several method all exists advantage and deficiency separately, assessed improve after,------all-pass hole precedence method (Full VIA First) is most widely used in industrial quarters at present.The technology of all-pass hole precedence method (Full VIA First) is as follows: first dielectric layer deposited, and photoetching, etching through hole clean, and through hole is filled, and photoetching, etching plain conductor clean, and finally form dual-damascene structure.This technology does not have alignment issues, there are not through hole Problem of Failure and process window bigger, but problem mainly concentrates on the step of through hole filling, the through hole of failure is filled the bad reaction that must cause later process, even lost efficacy, and conventional filling reagent and subsequent optical carving technology use the number of different types chemical substance, and technology is loaded down with trivial details.Along with constantly advancing of technology, these problems are also all the more responsive.
Summary of the invention
The objective of the invention is to propose a kind of technology of using novel light sensitive material porous filling damascene, can under the situation that reduces chemical reagent use kind, utilize novel porose filling technique, improve the fill process in Damascus, and surface preferably is provided, simplifies, shorten road, back etching, cleaning process greatly.
The Damascus technics of all-pass hole precedence method (Full VIA First), this manufacture method does not have alignment issues, does not have through hole Problem of Failure and process window bigger, is widely used.Its problem mainly concentrates on the step of through hole filling, the through hole of failure is filled the bad reaction that must cause later process, even loses efficacy, and conventional filling reagent and subsequent optical carving technology use number of different types chemical substance, technology is loaded down with trivial details, and road, back etching technics complexity.Along with constantly advancing of technology, these problems are also all the more responsive.At the problems referred to above, the present invention uses the technology of light sensitive material porous filling damascene, can under the situation that reduces chemical reagent use kind, utilize novel porose filling technique, by adjusting filling, baking process, control rests on air bubble volume, size, the position in the through hole of Damascus, improve the fill process in Damascus, and surface preferably is provided, simplify, shorten road, back etching, cleaning process greatly.
Among the present invention, by adjusting filling, baking process, control rests on air bubble volume, the size in the through hole of Damascus, and the position is shown in (Fig. 3).
The technology of the use light sensitive material porous filling damascene that the present invention proposes is to follow baking after adopting multiple full-filling and each full-filling, and described multiple full-filling and baking can be 2-5 time.Described light sensitive material is made of multiple organic material, mainly by ketone, and organic solvent and photosensitive cross-linking resin formations such as ethers or alkanes, molecular weight is between 85,000～150,000.
Each full-filling dosage of above-mentioned light sensitive material is 1.5ml～5ml, and baking temperature is 60C～250C, and stoving time is 10s～120s.
The main technique step of above-mentioned semiconductor fabrication process is:
(1) deielectric-coating in deposition Damascus;
(2) photoetching, etching through hole, cleaning;
(3) light sensitive material is filled, is toasted for the first time;
(4) light sensitive material is filled, is toasted for the second time; Repeat 2-5 time;
(5) light sensitive material exterior view cloth, baking, photoetching, etching plain conductor path, cleaning rest on air bubble volume, size in the through hole of Damascus with control, and Damascus manufacture craft of porose filling is finished in the position.
Single light sensitive material replaces conventional filling reagent and the subsequent optical carving technology uses the number of different types chemical substance, and this light sensitive material (being comprised: ketone, ethers by organic solvent, materials such as alkanes) and the photosensitive cross-linking resin constitute, molecular weight is 85,000～150, between 000.
The present invention is by multiple full-filling, multiple baking process, utilization is to light sensitive material full-filling amount of reagent and the adjustment of baking temperature and time, obtain the photaesthesia reagent residual bubble cavity stable in the through hole of Damascus and the crosslinked ratio of light sensitive material, mobile, technology characteristics such as contraction ratio, and then form good Damascus figure, and the anti-etching performance of good light sensitive material.
Description of drawings
Fig. 1 single inlay structure (single damascene structure)
Fig. 2 dual-damascene structure (double damask structure)
The porose filling of Fig. 3 light sensitive material
Drawing reference numeral: 1 Damascus dielectric layer, 2 bottom etching barrier layers, 3 light-sensitive materials, 4 remain in the bubble in the through hole of Damascus
Embodiment
Implementation step of the present invention is as follows:
1, the deielectric-coating in deposit Damascus;
2, photoetching, etching through hole, cleaning;
3, a little light sensitive material is filled out (be coated with dosage and be respectively 1.5ml or 2ml), low-temperature bake (baking temperature is chosen as 60C, 80C or 120C respectively, and stoving time is chosen as 60s, 80s, 100s or 120s respectively) for the first time;
4, a small amount of for the second time light sensitive material is filled (be coated with dosage and be chosen as 2ml or 3ml respectively), high-temperature baking (baking temperature is chosen as 120C, 140C, 160C, 180C or 200C respectively, and stoving time is chosen as 60s, 80s, 100s or 120s respectively);
5, light sensitive material exterior view cloth (be coated with dosage and be chosen as 2ml, 3ml, 4ml or 5ml respectively), middle temperature baking (baking temperature is chosen as 90C, 100C, 120C or 140C respectively, and stoving time is chosen as 60s, 80s, 100s or 120s respectively) for the third time;
6, photoetching, etching plain conductor path, cleaning.
In the above-mentioned technology, under each selected different parameters condition, all obtain good result.
Claims (3)
1. technology of using the light sensitive material porous filling damascene is characterized in that concrete steps are as follows:
(1) deielectric-coating in deposition Damascus;
(2) photoetching, etching through hole, cleaning;
(3) light sensitive material is filled, is toasted for the first time;
(4) light sensitive material is filled, is toasted for the second time; Repeat 2-5 time;
(5) Damascus manufacture craft of porose filling is finished in light sensitive material exterior view cloth, baking, photoetching, etching plain conductor path, cleaning;
In the above-mentioned steps, by adjusting filling, the baking process of light sensitive material, rest on air bubble volume, size, position in the through hole of Damascus with control.
2. technology according to claim 1 is characterized in that, described light sensitive material is by ketone, and ethers or alkanes organic solvent and photosensitive cross-linking resin constitute, and molecular weight is 85,000～150, between 000.
3. technology according to claim 1 is characterized in that, each full-filling dosage of described light sensitive material is 1.5ml～5ml, and baking temperature is 60 ℃～250 ℃, and stoving time is 10s～120s.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410093457 CN1632942B (en) | 2004-12-23 | 2004-12-23 | Technique for porous filling damascene using light sensitive material |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410093457 CN1632942B (en) | 2004-12-23 | 2004-12-23 | Technique for porous filling damascene using light sensitive material |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1632942A CN1632942A (en) | 2005-06-29 |
| CN1632942B true CN1632942B (en) | 2010-10-06 |
Family
ID=34847736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410093457 Expired - Fee Related CN1632942B (en) | 2004-12-23 | 2004-12-23 | Technique for porous filling damascene using light sensitive material |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1632942B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1925131B (en) * | 2005-09-02 | 2011-04-06 | 上海集成电路研发中心有限公司 | Process for reducing surface reflection index in semiconductor Damascus copper |
| CN1925130B (en) * | 2005-09-02 | 2010-08-25 | 上海集成电路研发中心有限公司 | Process for reducing surface reflection index in semiconductor Damascus copper |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6319815B1 (en) * | 1998-10-21 | 2001-11-20 | Tokyo Ohka Kogyo Co., Ltd. | Electric wiring forming method with use of embedding material |
-
2004
- 2004-12-23 CN CN 200410093457 patent/CN1632942B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6319815B1 (en) * | 1998-10-21 | 2001-11-20 | Tokyo Ohka Kogyo Co., Ltd. | Electric wiring forming method with use of embedding material |
Non-Patent Citations (1)
| Title |
|---|
| US 2004/0005782 A1,全文. |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1632942A (en) | 2005-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100578679B1 (en) | Techniques for triple and quadruple damascene fabrication | |
| KR101137624B1 (en) | via structure and via etching process of forming the same | |
| US20020187627A1 (en) | Method of fabricating a dual damascene structure | |
| US6350674B1 (en) | Manufacturing method for semiconductor device having a multilayer interconnect | |
| JP4095941B2 (en) | Microelectronic method | |
| CN101573787B (en) | Method of making an interconnect structure | |
| CN1632942B (en) | Technique for porous filling damascene using light sensitive material | |
| JP2001085523A (en) | Integrated circuit having dual damascene structure and manufacture thereof | |
| CN100546015C (en) | A kind of manufacture by Dimashg process | |
| US6680248B2 (en) | Method of forming dual damascene structure | |
| US6573187B1 (en) | Method of forming dual damascene structure | |
| US6376367B1 (en) | Method for manufacturing multilayer interconnects by forming a trench with an underlying through-hole in a low dielectric constant insulator layer | |
| JP2000294633A (en) | Semiconductor device and its manufacture | |
| CN1855418B (en) | Use of Dimashg process in production of integrated circuits | |
| KR100387265B1 (en) | Method of manufacturing a metal wiring and a capacitor in a semiconductor device | |
| KR20100051211A (en) | Method for manufacturing a metal line of an image sensor | |
| KR101241410B1 (en) | Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stress and structures formed thereby | |
| KR100529673B1 (en) | A method for manufacturing a semiconductor device using dual-damascene pattern | |
| KR100322887B1 (en) | Method for forming multilayered metal-line of semiconductor device | |
| US6403470B1 (en) | Method for fabricating a dual damascene structure | |
| KR100458594B1 (en) | Fabrication method of semiconductor device | |
| KR20010046324A (en) | Method for forming contact hole of semiconductor devices | |
| KR100578223B1 (en) | Method of fabricating of dual damascene of semiconductor device | |
| KR100450241B1 (en) | Method for forming contact plug and semiconductor device has the plug | |
| CN1988131B (en) | Through hole processing method in copper interconnection technology Damascus manufacturing process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101006 Termination date: 20161223 |