CN1630092A - Novel power device having surface horizontal 3D-RESURF layer - Google Patents

Abstract

This invention provides a novel power device with surface transverse 3D-RESURF, which is made by introducing high-doped 3D-RESURF layer on power device surface. Said surface transverse 3D-RESURF layer structure is composed of alternatively arranged opposite conductive type semiconductor area whose boundary is parallel with the surface voltage drop direction of power device, a low resistance pass way for reducing the conduction loss of device. Comparing with normal power device, said invention can reduce conduction resistance by more than 50 % under same voltage withstanding and to be characteristic of having insensitive surface charge conduction resistance and compatible with VLSI technology.

Description

Has the laterally novel power device of 3D-RESURF layer of surface

Technical field

This invention belongs to the semiconductor power device technology field.

Background technology

The increasingly extensive application of modern integrated circuits has proposed requirements at the higher level to the performance of power device, for the semiconductor high voltage power device made from the Si material, when improving requirement of withstand voltage, will produce a bigger conduction loss, if will reduce this bigger conducting resistance then need increase size of devices, thereby manufacturing cost is increased.Fig. 1 is the conventional LDMOS structural representation that is produced on the body silicon.Wherein, the 1st, p (or n) substrate, the 2nd, n ^-(or p ^-) epitaxial loayer, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid, the 22nd, drift region.Be used to bear withstand voltage drift region 22 needs low concentration dopings in this device, but then, conducting resistance when reducing the device forward conduction requires to have high-dopant concentration as the drift region 22 of current channel again, and this has just formed puncture voltage BV and conducting resistance R _OnBetween contradiction.MOS (metal-oxide-semiconductor) memory (MOS) device with common ordinary construction is an example, the puncture voltage BV of its simplification and conducting resistance R _OnBetween relational expression as follows:

$R_{\mathrm{on}}=\frac{L_D}{q{\mathrm{\μ}}_n{N}_D}=5.39\×{10}^{-9}{\left(\mathrm{BV}\right)}^{2.5}$ (for N-channel MOS)

$R_{\mathrm{on}}=\frac{L_D}{q{\mathrm{\μ}}_p{N}_D}=1.63\×10^{-8}{\left(\mathrm{BV}\right)}^{2.5}$ (for the P channel MOS)

Wherein, L _DBe drift region length, N _DBe drift region concentration, μ _nAnd μ _pBe respectively the mobility in electronics and hole, q is an electron charge.This shows that the conducting resistance of device is directly proportional with drift region length, be inversely proportional to its concentration.Length is short more, and concentration is high more, and then conducting resistance is more little.But certain withstand voltage in order to guarantee, the length of drift region 22 can not be done too shortly; Its concentration can not be De Taigao, otherwise can puncture near the PN junction of P under the grid region (n) trap 8, makes withstand voltage reduction.So just cause high voltage power device when opening, to have a bigger conduction loss, make its application be subjected to certain restriction.

In order to improve the conducting resistance of device, researchers have proposed various measures.Document (1) MasakatsuHoshi, Yoshio Shimoida, etc, " Low On-resistance LDMOSFETs with DSS PatternLayout " (low on-resistance lateral double diffusion metal oxide field-effect transistor) with DSS figure domain, Proceedings of 1995 International Symposium on Power Semiconductor Device﹠amp; ICs, Yokohama, a kind of special layout design has been adopted in pp63～67, and as Fig. 2, it spreads all over source window 10 around ornamental perforated window mouth 9, and ornamental perforated window mouth 9 and source window 10 are surrounded by grid region 11 again.This structure reduces conducting resistance by increasing the source unit area, but when device area becomes big, contacting metal resistance will no longer be left in the basket, and its conducting resistance can be littler by 30% than ordinary construction.But above scheme generally is applied to tens volts low pressure range, and for horizontal high voltage power device, owing to be subjected to the restriction of puncture voltage, conducting resistance still can not be improved fully.

Document (2), Chen Xingbi, Chinese patent, 91101845.X, 91.3.19 has adopted a kind of withstand voltage zone---compound buffer layer 20 of new structure in vertical device, replace in the conventional vertically device epitaxial loayer as Withstand voltage layer.Show that as Fig. 3 it is at n ⁺(or p ⁺) make n district 4 and p district 5 compound buffer layer 20 alternately on the substrate 1 and replace epitaxial loayer in the conventional device, diffuse to form p district (or n district) 6 then, shelter again and spread or ion injection n ⁺(or p ⁺) 7, then open vertical channel and make grid oxygen 16, make drain electrode 9 at last, source electrode 10, gate electrode 11.This structure has effectively been alleviated the contradiction between conducting resistance and the device withstand voltage, but because it replaces whole epitaxial loayer with compound buffer layer, it is narrow and dark that n district 4 alternately and p district 5 must do, and must have a strong smell by neutron and unconventional technology such as become and make, thereby caused the incompatible of itself and very lagre scale integrated circuit (VLSIC) (VLSI) technology, limited its application.

Document (3) Nassif-Khalil, S.G.; Salama, C.A.T., " Super junction LDMOST insilicon-on-sapphire technology (SJ-LDMOST); Power Semiconductor Devices and ICs ", (super-junction bilateral diffusion metal oxide field-effect transistor on the sapphire, power semiconductor and integrated circuit) 2002.Proceedings of the 14th International Symposium on, 4-7 June, 2002 make Super-Junction (super knot) LDMOS on the SOS material.As Fig. 4, the 1st, p (or n) substrate, the 12nd, sapphire material, the 21st, Super-Junction layer, the 4th, n ⁺(or p ⁺) semiconductor region, the 5th, p ⁺(or n ⁺) semiconductor region, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid.This structure replaces original drift region by the heavily doped semiconductor region 4 of SJ structure 21 and heavily doped semiconductor region 5, be allowed to condition at exhaust fully before the puncture can obtain one higher withstand voltage, and when forward conduction, can reduce the size of conducting resistance.But this structure is made in the SJ drift region on the insulator, has limited the raising of puncture voltage, and the device heat dispersion is poor, and cost is too high.

Summary of the invention

The object of the present invention is to provide a kind of laterally novel power device of 3D-RESURF (the three-dimensional surface field 3-Dimensions Reduced Surface Field that reduces) layer of surface that has, compare with common lateral power, have under identical puncture voltage situation, make forward conduction resistance reduce more than 50%, reduce conducting resistance to the sensitiveness of surface charge and the characteristics of compatible VLSI technology.

The invention provides a kind of laterally novel power device of 3D-RESURF layer of surface that has, it comprises substrate 1 and epitaxial loayer 2, and epitaxial loayer 2 lower surfaces link to each other with substrate 1; It is characterized in that it also comprises laterally 3D-RESURF layer structure of surface, described surface horizontal 3D-RESURF layer structure is that semiconductor regions 4 and the semiconductor regions 5 by conductivity type opposite forms alternately, and the surface electrical pressure drop direction of the interface of semiconductor regions 4 and semiconductor regions 5 during with described power device work is parallel.It is arranged in as the upper surface of the drift region of epitaxial loayer 2 (as shown in Figure 5), and the doping content of described semiconductor regions 4 and semiconductor regions 5 is higher than the doping content of epitaxial loayer 2.

Need to prove:

(1) the above-mentioned horizontal 3D-RESURF layer structure in surface can directly be made on the substrate 1, and do not adopt traditional light dope epitaxial loayer 2 (as shown in Figure 6);

(2) concentration, width, length and the degree of depth of the semiconductor regions 4 of conductivity type opposite recited above and semiconductor regions 5 can be the same or different, its arrangement mode can be complete symmetric arrays, also can be incomplete symmetric arrays, but two regional total amount of electric charge relative differences be no more than 50%; Its shape can be a rectangle, also can be non-regular figures (shown in Fig. 7～11) such as trapezoidal, zigzag;

(3) the novel power device with the horizontal 3D-RESURF layer in surface of the present invention can adopt semi-conducting material manufacturings such as body silicon, SOI, carborundum, GaAs, indium phosphide or germanium silicon;

Operation principle of the present invention:

A kind of laterally novel power device of 3D-RESURF layer of surface that has provided by the invention can overcome the high shortcoming of common transversal device conducting resistance, obtains lower conduction loss.Here be example (as Fig. 5) with n type LDMOS, operation principle of the present invention is described.

When forward conduction, 3D-RESURF layer 3 effectively reduces conducting resistance for electric current provides a low-resistance channel, reaches the purpose of low conduction loss.Suppose the electronics semiconductor region 5 of 3D-RESURF layer 3 of not flowing through, and the depletion width when ignoring semiconductor region 4 forward conductions, can draw following conducting resistance R _OnComputing formula: R _On=R _Contact+ R _Source+ R _Channel+ R _Drain+ R _3D-resurfR _Drift/ (R _3D-resurf+ R _Drift).R wherein _ContactBe contact resistance, R _SourceBe source resistance, R _ChannelBe channel resistance, R _Drift=ρ _dL _DriftBe drift zone resistance, R _DrainBe drain region resistance, $R_{3D-\mathrm{resurf}}=\frac{L_{\mathrm{drift}}}{N_{3D-\mathrm{resurf}}q{\mathrm{\μ}}_{n}S}$ Be the resistance in 3D-RESURF floor district, ρ _dBe the epilayer resistance rate, L _DriftBe drift region length, N _3D-resurfBe the impurity concentration of the semiconductor region 4 in the 3D-RESURF layer 3, S is the cross-sectional area that electric current passes through, E _cIt is the silicon breakdown electric field.Because the doping content of 3D-RESURF layer 3 structure is far above epitaxial loayer 2, so its unit area resistance is littler.As shown in Figure 5, two resistance are in parallel connection, therefore, the electric current surperficial 3D-RESURF layer 3 of mainly flowing through, when requirement on devices semiconductor region 4 during as conduction region, semiconductor region is inoperative 5 this moments, otherwise when requirement on devices semiconductor region 5 during as conduction region, semiconductor region 4 is inoperative.Bear reverse when withstand voltage, different semiconductor regions 4 and the semiconductor regions 5 of conduction type reached the state that exhausts mutually in the 3D-RESURF layer 3 as thin as a wafer at this moment, the electric field that ionized impurity produces in two districts weakens mutually, and is minimum to the withstand voltage influence of entire device.As seen, structure provided by the invention can reduce conducting resistance significantly behind the 3D-RESURF layer 3 of introducing high concentration, the conduction loss of device is reduced, and do not influence the withstand voltage effect of device.According to structure provided by the invention, the reduction of the conventional LDMOS of the break-over of device resistance ratio in the time of can making forward conduction is more than 50%.

Structure of the present invention has also been improved its sensitiveness to surface charge to a certain extent except reducing significantly the conducting resistance.Conventional high tension apparatus is not owing to there is 3D-RESURF layer 3, and is to guarantee high withstand voltagely, and the concentration of epitaxial loayer 2 can not be too high, and influenced by surface charge bigger for surface accumulation layer resistance when making forward conduction, is unfavorable for the optimal design to conducting resistance.And structure of the present invention since epitaxial loayer 2 surface coverage the 3D-RESURF layer 3 of one deck high concentration, surface charge is had certain shielding action, thereby makes the optimizing process of conducting resistance obtain simplifying.

Another advantage of the present invention is to have overcome traditional 3D-RESURF layer structure and the incompatible drawback of very lagre scale integrated circuit (VLSIC) technology.Traditional 3D-RESURF layer structure, the requirement junction depth is dark, bar is wide little, so be difficult to obtain by the ion injection of routine and the method for knot, and semiconductor regions 4 in the 3D-RESURF layer 3 of the present invention and semiconductor regions 5 are positioned at device surface, and junction depth is very shallow, are easy to realize by the conventional means of VLSI technologies such as ion injection, knot, therefore realized the compatibility of technology, it can be used in SPIC preferably.

In sum, a kind of laterally novel power device of 3D-RESURF layer of surface that has provided by the invention, by introducing highly doped 3D-RESURF layer on the power device surface, to provide a low-resistance channel to reduce the conduction loss of device, compare with common power device, can reach equal withstand voltage conducting resistance down and reduce by 50% the above object, simultaneously, it have conducting resistance to surface charge insensitive and with the characteristics of VLSI process compatible.Therefore, adopt the present invention can make the high pressure of various function admirables, at a high speed, low conduction loss lateral power.

Description of drawings:

Fig. 1 is conventional LDMOS structural representation

Wherein, the 1st, p (or n) substrate, the 2nd, n ^-(or p ^-) epitaxial loayer, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid, the 22nd, drift region.

Fig. 2 is the cellular construction vertical view with low on-resistance lateral double diffusion metal oxide field-effect transistor of DSS figure domain

Wherein, the 9th, ornamental perforated window mouth, the 10th, source window, the 11st, grid region.

Fig. 3 is existing RMOS schematic diagram with composite buffering structure of voltage-sustaining layer

Wherein, the 1st, n ⁺(or p ⁺) substrate, the 20th, compound buffer layer, the 4th, n district (or p district), the 5th, p district (or n district), the 6th, p district (or n district), the 7th, n ⁺(or p ⁺) district, the 16th, grid oxygen, the 9th, drain electrode, the 10th, source electrode, the 11st, gate electrode.

Fig. 4 is the Super-Junction LDMOS structural representation on the existing SOS

Wherein, the 1st, p (or n) substrate, the 12nd, sapphire, the 3rd, Super-Junction layer, the 4th, n ⁺(or p ⁺) semiconductor region, the 5th, p ⁺(or n ⁺) semiconductor region, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid.

Fig. 5 is the LDMOS device architecture schematic diagram with the horizontal 3D-RESURF layer in surface that is made on the body silicon provided by the invention

Wherein, the 1st, p (or n) substrate, the 2nd, n ^-(or p ^-) epitaxial loayer, the 3rd, surperficial 3D-RESUEF layer, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid, the 4th, n ⁺(or p ⁺) semiconductor region, the 5th, p ⁺(or n ⁺) semiconductor region, at this moment, the junction depth in two districts, width, concentration, identical length are together.

Fig. 6 is that employing diffusion trap provided by the invention is as the horizontal 3D-RESUEF LDMOS device architecture schematic diagram in the surface of drift region

Wherein, the 1st, p (or n) substrate, the 18th, n ^-(or p ^-) trap, the 3rd, surperficial 3D-RESUEF layer, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid, the 4th, n ⁺(or p ⁺) semiconductor region, the 5th, p ⁺(or n ⁺) semiconductor region, at this moment, the junction depth in two districts, width, concentration, identical length are together.

The situation that Fig. 7 is semiconductor region 4,5 junction depth differences of the present invention, width difference, concentration difference, length is identical

Fig. 7 a is a structural representation, and Fig. 7 b is the profile along A-A '

Wherein, the 1st, p (or n) substrate, the 2nd, n ^-(or p ^-) epitaxial loayer, the 3rd, surperficial 3D-RESUEF layer, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid; The 4th, n ⁺(or p ⁺) semiconductor region, the 5th, p ⁺(or n ⁺) semiconductor region, at this moment, the junction depth difference in two districts, width difference, concentration difference.

Fig. 8 is semiconductor region 4,5 situation that junction depth is identical, width is different, concentration is different, length is identical of the present invention

Fig. 8 a is a structural representation, and Fig. 8 b is the profile along A-A '

Wherein, the 1st, p (or n) substrate, the 2nd, n ^-(or p ^-) epitaxial loayer, the 3rd, surperficial 3D-RESUEF layer, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid, the 4th, n ⁺(or p ⁺) semiconductor region, the 5th, p ⁺(or n ⁺) semiconductor region, at this moment, the junction depth in two districts is identical, width is different, concentration is different.

Fig. 9 is semiconductor region 4,5 situation that junction depth is identical, width is different, concentration is different, length is different of the present invention

Fig. 9 a is a structural representation, and Fig. 9 b is the profile along A-A '

Wherein, the 1st, p (or n) substrate, the 2nd, n ^-(or p ^-) epitaxial loayer, the 3rd, surperficial 3D-RESUEF layer,, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid; The 4th, n ⁺(or p ⁺) semiconductor region, the 5th, p ⁺(or n ⁺) semiconductor, two district's junction depths are identical at this moment, length is different, width is different, concentration is different.

Figure 10 is that semiconductor region 4,5 of the present invention is trapezoidal situation

Wherein, the 1st, p (or n) substrate, the 2nd, n ^-(or p ^-) epitaxial loayer, the 3rd, surperficial 3D-RESUEF layer, the 4th, n ⁺(or p ⁺) semiconductor region, the 5th, p ⁺(or n ⁺) semiconductor region, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid.

Figure 11 is that semiconductor region 4,5 of the present invention is zigzag situation

Wherein, the 1st, p (or n) substrate, the 2nd, n ^-(or p ^-) epitaxial loayer, the 3rd, surperficial 3D-RESUEF layer, the 4th, n ⁺(or p ⁺) semiconductor region, the 5th, p ⁺(or n ⁺) semiconductor region, the 6th, n ⁺(or p ⁺) drain region, the 7th, n ⁺(or p ⁺) source region, the 8th, p (or n) trap, the 9th, drain electrode, the 10th, source electrode, the 11st, grid.

Embodiment

Adopt surperficial 3D-RESURF layer structure of the present invention, can obtain high pressure, the low on-resistance power device of function admirable.Can be applied to common power devices such as horizontal dual pervasion field effect transistor, landscape insulation bar double-pole-type power transistor (LIGBT), electrostatic induction transistor (SIT), lateral thyristor, PN diode.Along with the development of semiconductor device art, adopt the present invention can also make more high pressure, low on-resistance power device.

Have the laterally novel LDMOS power device of 3D-ESURF of surface, as shown in Figure 5, comprise p (or n) substrate 1, n ^-(or p ^-) epitaxial loayer 2, n ⁺(or p ⁺) drain region 6, n ⁺(or p ⁺) source region 7, p (or n) trap 8, drain electrode 9, source electrode 10, grid 11.It is characterized in that it also comprises surperficial 3D-RESUEF layer 3, surperficial 3D-RESUEF layer 3 is by n ⁺(or p ⁺) semiconductor region 4 and p ⁺(or n ⁺) semiconductor region 5 forms alternately.

In implementation process, can be as the case may be, under the constant situation of basic structure, can carry out certain accommodation design, for example:

Fig. 6 directly adopts diffusion trap 18 to replace above-mentioned epitaxial loayer 2 on single crystalline substrate, makes 3D-RESURF layer 3 then on diffusion trap 18, can reduce production costs like this, and with processing line on requires to be complementary, be easy to realization.

3D-RESURF layer 3 among Fig. 7, with semiconductor region 4 (or 5) bar that participates in conduction do shallow and wide, with the semiconductor region 5 (or 4) that does not participate in conducting electricity do narrow and dark, the electric charge sum in assurance two districts is identical, can further reduce conducting resistance like this.

3D-RESURF layer 3 among Fig. 8, semiconductor region 4 is identical with 5 junction depth, but participate in conduction semiconductor region 4 (or 5) wider width and concentration is lower, the width that does not participate in the semiconductor region 5 (or 4) that conducts electricity is narrower and concentration is higher, forms comparatively complete current path in the time of can guaranteeing forward conduction like this.

3D-RESURF layer 3 among Fig. 9, semiconductor region 4 is identical with 5 junction depth, but the semiconductor region 4 (or 5) that will participate in conduction is done longlyer, makes current path longer.

The layer of 3D-RESURF shown in Figure 10 3, semiconductor region 4 is all identical with 5 junction depth, concentration, but it is shaped as trapezium structure, distributes to the influence of this structure at longitudinal field with compensation.

The layer of 3D-RESURF shown in Figure 11 3, semiconductor region 4 is all identical with 5 junction depth, concentration, but it is shaped as broached-tooth design, distributes to the influence of this structure at longitudinal field with compensation.

Claims (6)

1, a kind of novel power device with the horizontal 3D-RESURF layer in surface, it comprises substrate 1 and epitaxial loayer 2, epitaxial loayer 2 lower surfaces link to each other with substrate 1; It is characterized in that it also comprises laterally 3D-RESURF layer structure of surface, described surface horizontal 3D-RESURF layer structure is that semiconductor regions 4 and the semiconductor regions 5 by conductivity type opposite forms alternately, surface electrical pressure drop direction when the interface of semiconductor regions 4 and semiconductor regions 5 is worked with described power device is parallel, it is arranged in the upper surface as the drift region of epitaxial loayer 2, and the doping content of described semiconductor regions 4 and semiconductor regions 5 is higher than the doping content of epitaxial loayer 2.

2, according to the described a kind of laterally novel power device of 3D-RESURF layer of surface that has of claim 1, it is characterized in that the horizontal 3D-RESURF layer structure in surface can directly be made on the substrate 1, and do not adopt epitaxial layer structure.

3, according to claim 1 or 2 described a kind of laterally novel power devices of 3D-RESURF layer of surface that have, it is characterized in that the semiconductor regions 4 of described conductivity type opposite and concentration, width, length and the degree of depth of semiconductor regions 5 can be the same or different;

4, according to claim 1 or 2 described a kind of laterally novel power devices of 3D-RESURF layer of surface that have, the semiconductor regions 4 of electric type opposite and the total amount of electric charge relative difference of semiconductor regions 5 are no more than 50%.

5, according to claim 1 or 2 described a kind of laterally novel power devices of 3D-RESURF layer of surface that have, it is characterized in that the semiconductor regions 4 of described conductivity type opposite and the shape of semiconductor regions 5 can be rectangles, also can be non-regular figures such as trapezoidal, zigzag;

6,, it is characterized in that it can adopt semi-conducting material manufacturings such as body silicon, SOI, carborundum, GaAs, indium phosphide or germanium silicon according to claim 1 or 2 described a kind of laterally novel power devices of 3D-RESURF layer of surface that have.

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