CN1627268A - System and method for validating integrality of data - Google Patents
System and method for validating integrality of data Download PDFInfo
- Publication number
- CN1627268A CN1627268A CN 200310112592 CN200310112592A CN1627268A CN 1627268 A CN1627268 A CN 1627268A CN 200310112592 CN200310112592 CN 200310112592 CN 200310112592 A CN200310112592 A CN 200310112592A CN 1627268 A CN1627268 A CN 1627268A
- Authority
- CN
- China
- Prior art keywords
- data
- bit
- identification position
- processing unit
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
A system for confirming data completeness includes a non-volatile memory unit, a central processor and a program memory unit. The method comprises a data renewing method, a data delete method and a data fetching and judgment method, in which, the fetching and judgment method includes: a, providing a central processor, b, providing a non-volatile memory unit storing data, first and second bit cells, c, fetching said first bit cell, , fetching said second bit cell, e, comparing if the first bit cell is equal to the second, if so, it displays wrong information g, if not, it fetches the data.
Description
[technical field]
The present invention relates to a kind of affirmation data integrity system and method, especially relate to a kind of by the extra identification position information of storage, with the whether complete System and method for of auxiliary judgment data.
[background technology]
During computer system operation; in order to allow system can remember duty some settings or present fast, can allow computer system be equipped with non-volatility memorizer such as MRAM (magnetisable material random access memory), SRAM with Battery (carrying the static RAM of battery in the encapsulation), the flash memory etc. of some electronic types usually.Yet be stored in the data of this non-volatility memorizer, be under the undesired situation in computer system, for example Data Update loses power supply midway, and its data have ruined possibility.Therefore whether be necessary to provide a kind of mechanism so that when next computer system comes into operation, it is complete and correct to differentiate these data.
Once be exposed in the United States Patent (USP) the 6th of bulletin on February 6 calendar year 2001 about the supporting technology of confirming data integrity in the non-volatility memorizer, 185, No. 134, this patent name is " the employed control method of flash memory system and driver (Flash Memory Control Method, Flash Memory System Using The Control Method And Flash MemoryDevice Using The Control Method) ".This patent is to disclose a kind ofly can to check the method for carrying out data error check and correction in flash memory.This patent is to become data block (Flash Memory Cell) by flash memory being carried out logical division, so that carry out data integrity inspection and wrong the reparation.The existing deficiency of technology that this patent discloses is: the data block logical division that it proposed is comparatively complicated, does not also design exclusive inspection position; If better simply logical division and exclusive inspection position are provided, required time in the time of can effectively reducing computer system examination data.Whether therefore be necessary to propose a kind of new solution, this scheme can provide simple and rapid bug check system and method, to support the data in the computer system quick check nonvolatile memory complete.
[summary of the invention]
Affirmation data integrity system and method for the present invention can be after undesired situation appears in computing machine, causes that data are abnormal preserves thereby for example lose power supply during computer run suddenly, and whether the data in the quick check nonvolatile memory are complete.
The invention provides a kind of system that confirms data integrity, this system includes a non-volatility memorizer, wherein stores at least one logic data block, and each logic data block comprises a plurality of data bytes, one first identification position and one second identification position.Store data in the data byte, storage first bit in this first identification position, storage second bit in this second identification position.One central processing unit, it is renewable, delete and read logic data block.This reads, and need compare first bit and second bit judges whether this logic data block is complete.One program storage comprising a space requirement module, is used to indicate the address space of central processing unit to this non-volatility memorizer requirement Data Update; One data writing module is used for indicating central processing unit that data are write a plurality of data bytes of non-volatility memorizer, and writes first bit and second bit and judge so that carry out integrality; One data read judge module, the logic data block that is used to indicate central processing unit to find out data storage also reads in it to check its data integrity; One data deletion module is used for indicating central processing unit to delete a plurality of data of logic data block.
The present invention also provides a kind of method of confirming data integrity, and this method comprises Data Update, deletion and read method.Wherein data-updating method comprises: a central processing unit (a) is provided, and it can read desires to carry out data updated; (b) provide a non-volatility memorizer, comprising a plurality of data bytes, first an identification position and one second identification position, store data in this data byte, store one first bit in this first identification position, store one second bit in this second identification position; (c) central processing unit reads second bit; (d) central processing unit writes second bit to the first identification position to replace first bit; (e) central processing unit writes data in the data byte; (f) central processing unit writes 2 antiposition units to the first identification position of second bit to replace second bit.Data-erasure method comprises: a central processing unit (g) is provided; (h) provide a non-volatility memorizer, comprising a plurality of data bytes, one first identification position and one second identification position, store data in this data byte, store one first bit in this first identification position, store one second bit in this second identification position; (i) central processing unit reads this second bit; (j) central processing unit writes in this second bit to the first identification position to replace first bit.Data read and determination methods comprise: a central processing unit (k) is provided; (l) provide a non-volatility memorizer, comprising a plurality of data bytes, one first identification position and one second identification position, store data in this data byte, store one first bit in this first identification position, store one second bit in this second identification position; (m) central processing unit reads this first bit; (n) central processing unit reads this second bit; (o) relatively whether this first bit equals second bit; (p) if first bit equals second bit, then show error message; (q) if first bit is not equal to second bit, then reading of data.
The system and method for affirmation data integrity provided by the invention, whether after can helping computer system to lose power supply under abnormal conditions or decommissioning, it is complete and correct to differentiate the data that are stored in non-volatility memorizer when coming into operation next time.System provided by the present invention comprises the identification position, and provide method to comprise Data Update, delete and read based on the identification position, whether will effectively help computer system after undesired situation takes place, it is complete and correct to differentiate the data that are stored in non-volatility memorizer.
[description of drawings]
Fig. 1 is that the present invention confirms data integrity system hardware Organization Chart.
Fig. 2 is the non-volatility memorizer memory address synoptic diagram that the present invention confirms the data integrity system.
Fig. 3 is the data storage situation synoptic diagram that the present invention confirms the data integrity system.
Fig. 4 is the functional module group figure that the present invention confirms the data integrity system.
Fig. 5 A is that the present invention confirms data-updating method process flow diagram in the data integrity method.
Fig. 5 B is that the present invention confirms data-erasure method process flow diagram in the data integrity method.
Fig. 5 C is that the present invention confirms data read and determination methods process flow diagram in the data integrity method.
[embodiment]
As shown in Figure 1, be that the present invention confirms data integrity system hardware Organization Chart.This framework comprises a central processing unit 1, a non-volatility memorizer 2, a program storage 3, first bus 4 and second bus 5.This non-volatility memorizer 2 is meant can be because of not losing its stored memory of data after cutting off the power supply, it is made up of a plurality of bytes in logic, can be used for storing data.This program storage 3 is to be used for the stored programme module, and it can be supplementary storage such as hard disk, or general storer such as ROM or Flash ROM etc.This central processing unit 1 can upgrade, delete and read the data of being stored in the non-volatility memorizer 2 according to program stored module in the program storage 3.
As shown in Figure 2, be the non-volatility memorizer memory address synoptic diagram of affirmation data integrity of the present invention system.Non-volatility memorizer 2 is divided into a plurality of address spaces in logic, and each address is made up of a plurality of institutes, and it can be used for storing data.By the present invention, store a piece of data at random in a plurality of data bytes 20 of non-volatility memorizer 2 time, to before a plurality of data bytes 20, add one first identification position 21 in its data storage, and data finish the storage back and add one second identification position 22, to form a logic data block 23.There is one first bit in the first identification position 21, is digital " 0 " or " 1 ".There is one second bit in the second identification position 22, is digital " 0 " or " 1 ".Having data in the data byte 20, is to be made of digital " 0 " or " 1 ".
As shown in Figure 3, be the data storage situation synoptic diagram of affirmation data integrity of the present invention system.This logic data block 23 comprises a plurality of data bytes 20,21 and 1 second identification position 22, one first identification position, and its logic arrangement as shown in Figure 3.According to these 21 and second identification position, first identification position, 22 bit differences that write down, have four kinds of situations and comprise (0,0), (1,0), (0,1), (1,1).Situation two and situation three are the data integrity situation.Situation one and situation four are the imperfect situation of data in the present invention, and the data byte 20 in this moment logic data block 23 will be by as space bit.
As shown in Figure 4, be the functional block diagram that the present invention confirms the data integrity system.Storage one space requirement module 31, a data writing module 32, a data read judge module 33, a data deletion module 34 in this program storage 3.This space requirement module 31 is used for non-property storer 2 required the address space of data storage.This data writing module 32 writes the data of these data in a plurality of data bytes 20 in the non-volatility memorizer 2, and adds the 21 and second identification position 22, the first identification position in the front and back of data byte 20.Thereby this data read judge module 33 is used to find out the logic data block 23 of data storage and it is read in check its data integrity.This data deletion module 34 is used for deleting a plurality of data in the logic data block 23.
Shown in Fig. 5 A, be that the present invention confirms data-updating method process flow diagram in the data integrity method.Former first bit that definition is stored in the first identification position 21 originally is F, and first bit after the renewal is F '; Former second bit that originally is stored in the second identification position 22 is B, and the identification of second after renewal position is B ', and the data that originally are stored in the data byte 20 are D, and the data after the renewal are D '.
Central processing unit 1 judges that by program storage 3 included space requirement modules 31 non-volatility memorizer 2 possesses enough spaces with renewal D earlier, and carries out following flow process by data writing module 32:
(a) by reading the former second bit B (step S10) in the second identification position 22.
(b) the first bit F ' after the renewal equals former second bit, i.e. F '=B (step S11).
(c) second bit after upgrading equals the radix-minus-one complement of former second bit, promptly B '=! B (step S12).This radix-minus-one complement is 2 antiposition units of true form, and the radix-minus-one complement as 0 is that 1,1 radix-minus-one complement is 0.
(d) write the first bit F ' (step S13) in the first identification position 21 after the renewal.
(e) write data D ' (step S14) in data byte 20 after the renewal.
(f) write the second bit B ' (step S15) in the second identification position 22 after the renewal.
According to above-mentioned flow process, if (step S14) produces undesired interruption in Data Update, then the first bit F ' will be identical with the former second bit B, therefore can judge that it is the imperfect situations of data.
Shown in Fig. 5 B, be that the present invention confirms data-erasure method process flow diagram in the data integrity method.Central processing unit 1 carries out following flow process by program storage 3 included data writing module 32 and data deletion modules 34:
(g) by reading original second bit B (step S20) in the second identification position 22.
(h) the first bit F ' after the renewal equals original second bit, i.e. F '=B (step S21).
(I) the first bit F ' after will upgrading writes in the first identification position 21 (step S22).
According to above-mentioned flow process, the first bit F ' will be identical with original second bit B, and computer system will be used this data byte 20 as space bit.
Showing as Fig. 5 C, is that the present invention confirms data read and determination methods process flow diagram in the data integrity method.Based on above-mentioned described to Fig. 5 A and Fig. 5 B, central processing unit 1 can carry out following flow process by program storage 3 included data read judge modules 33:
(j) read original first bit F (step S30) by the first identification position 21.
(k) read original second bit B (step S31) by the second identification position 22.
(l) judge whether that the first bit F equals the second bit B (step S32).If yes, represent that this desire reading of data D content is imperfect, then enter the exception flow process so that fault processing; If, then do not connect down (m).
(m) by reading original data D (step S33) in the data byte 20.
Above-mentioned exception flow process is by the imperfect information of computer system video data, handles so that the operator of computer system carries out corresponding error.
Though the present invention discloses as above with embodiment, be not in order to limit the present invention.Any those who are familiar with this art without departing from the spirit and scope of the present invention, change and modify when doing, so protection scope of the present invention are as the criterion when looking accompanying the claim person of defining.
Claims (5)
1. confirm the data integrity system for one kind, it is characterized in that, include:
One non-volatility memorizer stores at least one logic data block, and each logic data block comprises:
A plurality of data bit tuples wherein store data;
One first identification position wherein stores first bit;
One second identification position wherein stores second bit;
One central processing unit, it is renewable, the logic data block in the above-mentioned non-volatility memorizer of deletion, and by reading and comparing first bit and second bit to judge whether this logic data block complete.
2. affirmation data integrity as claimed in claim 1 system is characterized in that also including a program storage, and this program storage comprises:
One space requirement module is used to indicate the address space of central processing unit to this non-volatility memorizer requirement Data Update;
One data writing module is used for indicating central processing unit that data are write a plurality of data bytes of non-volatility memorizer, and first bit is write in the first identification position, and second bit is write in the second identification position;
One data read judge module, the logic data block that is used to indicate central processing unit to find out data storage also reads in it to check its data integrity;
One data deletion module is used for indicating central processing unit to delete a plurality of data of logic data block.
3. the data-updating method that can confirm data integrity is characterized in that including:
One central processing unit is provided, and it can read desires to carry out data updated;
One non-volatility memorizer is provided,, stores data in this data byte, store one first bit in this first identification position, store one second bit in this second identification position comprising a plurality of data bytes, one first identification position and one second identification position;
Central processing unit reads second bit;
Central processing unit writes in second bit to the first identification position to replace first bit;
Central processing unit writes data in the data byte;
The 2 antiposition units to the first that central processing unit writes second bit are recognized in the position to replace second bit.
4. the data-erasure method that can confirm data integrity is characterized in that including:
One central processing unit is provided;
One non-volatility memorizer is provided,, stores data in this data byte, store one first bit in this first identification position, store one second bit in this second identification position comprising a plurality of data bytes, one first identification position and one second identification position;
Central processing unit reads this second bit;
Central processing unit writes in this second bit to the first identification position to replace first bit.
5. a data read and the determination methods that can confirm data integrity is characterized in that including:
One central processing unit is provided;
One non-volatility memorizer is provided,, stores one first bit in this first identification position, store one second bit in this second identification position comprising storing data in a plurality of data bytes, one first identification position and one second this data byte of identification position;
Central processing unit reads this first bit;
Central processing unit reads this second bit;
Relatively whether this first bit equals second bit;
If first bit equals second bit, then show error message;
If first bit is not equal to second bit, then reading of data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101125928A CN100370429C (en) | 2003-12-11 | 2003-12-11 | System and method for validating integrality of data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101125928A CN100370429C (en) | 2003-12-11 | 2003-12-11 | System and method for validating integrality of data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1627268A true CN1627268A (en) | 2005-06-15 |
| CN100370429C CN100370429C (en) | 2008-02-20 |
Family
ID=34759836
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101125928A Expired - Fee Related CN100370429C (en) | 2003-12-11 | 2003-12-11 | System and method for validating integrality of data |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100370429C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105468893A (en) * | 2014-09-26 | 2016-04-06 | 希森美康株式会社 | Computer system, program, and method for assisting recurrence risk diagnosis of colorectal cancer |
| US10900084B2 (en) | 2015-09-16 | 2021-01-26 | Sysmex Corporation | Method for supporting diagnosis of risk of colorectal cancer recurrence, treatment of colorectal cancer, and administration of anticancer drug |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5533190A (en) * | 1994-12-21 | 1996-07-02 | At&T Global Information Solutions Company | Method for maintaining parity-data consistency in a disk array |
| JPH10240629A (en) * | 1997-02-27 | 1998-09-11 | Mitsubishi Electric Corp | Intra-memory information updating method |
| US6745301B2 (en) * | 2000-08-07 | 2004-06-01 | Dallas Semiconductor | Microcontroller programmable method for accessing external memory in a page mode operation |
-
2003
- 2003-12-11 CN CNB2003101125928A patent/CN100370429C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105468893A (en) * | 2014-09-26 | 2016-04-06 | 希森美康株式会社 | Computer system, program, and method for assisting recurrence risk diagnosis of colorectal cancer |
| CN105468893B (en) * | 2014-09-26 | 2019-06-21 | 希森美康株式会社 | Assist the computer system, program and method for sending out diagnosis of risk again of colorectal cancer |
| US10900084B2 (en) | 2015-09-16 | 2021-01-26 | Sysmex Corporation | Method for supporting diagnosis of risk of colorectal cancer recurrence, treatment of colorectal cancer, and administration of anticancer drug |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100370429C (en) | 2008-02-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7639537B2 (en) | Method for writing data in a non volatile memory unit | |
| US7472331B2 (en) | Memory systems including defective block management and related methods | |
| EP0862762B1 (en) | Semiconductor memory device having error detection and correction | |
| US7802152B2 (en) | Method and apparatus for recording high-speed input data into a matrix of memory devices | |
| EP1403771A1 (en) | Non-volatile memory control method | |
| US20040103241A1 (en) | Method and apparatus for effectively enabling an out of sequence write process within a non-volatile memory system | |
| KR20060043818A (en) | Nonvolatile memory apparatus | |
| US20050036390A1 (en) | Non-volatile memory and non-volatile memory data rewriting method | |
| US8880778B2 (en) | Memory buffer having accessible information after a program-fail | |
| JP2006048893A (en) | Flash memory device with defective block managing function and defective block managing method of the same | |
| JP2000105694A (en) | Flash memory, microcomputer equipped with flash memory, and method for storing program in flash memory | |
| CN104516959A (en) | Method and device for managing database logs | |
| JP2008077221A (en) | Vehicular control device | |
| CN1180349C (en) | Quick flashing decument system | |
| US7487316B1 (en) | Archive and restore system and methodology for on-line edits utilizing non-volatile buffering | |
| JP2008225983A (en) | Parity error restoration circuit | |
| KR20040085422A (en) | Access apparatus and method using flash memory | |
| CN113220221B (en) | Memory controller and data processing method | |
| CN1627268A (en) | System and method for validating integrality of data | |
| US8468384B2 (en) | Method and apparatus for dealing with write errors when writing information data into memory devices | |
| JP2006202086A (en) | Updating method for firmware | |
| WO2013095998A1 (en) | Systems and methods for managing parallel access to multiple storage systems | |
| JP2003036209A (en) | Nonvolatile memory and data rewriting method thereof | |
| CN103389943A (en) | Control device, storage device, and storage control method | |
| CN104575605A (en) | Memory device and method using nonvolatile memory to start up system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080220 Termination date: 20141211 |
|
| EXPY | Termination of patent right or utility model |