CN1622301A - Method for preparing quasi dual gate field effect transistor - Google Patents

Abstract

The present invention is quasi-SOI-Fin FET device making process and belongs to the field of CMOS ULSI making technology. The making process includes first ion implantation doping source and drain on body silicon chip to form active areas; subsequent etching fin area to form I-shaped figure to the source arean and the drain area; depositing SiN to protect fin area, further etching silicon and oxidizing to form quasi-SOI structure in the fin area; preparing isolating area, grid dielectric and grid electrode; and final conventional CMOS technological process to complete the following steps until finishing the quasi-SOI-Fin FET device based on body silicon technology. The present invention has deposited SiN to protect fin arean and subsequent oxidation to form the quasi-SOI structure in the fin area, and has simple technological process and low cost.

Description

The preparation method of quasi dual gate field effect transistor

Technical field

The invention belongs to cmos vlsi manufacturing technology field, relate in particular to a kind of based on the accurate SOI-FinFET preparation of devices of the part on body silicon method.

Background technology

The demand for development device size of cmos vlsi technology constantly dwindles, and short channel effect (causing potential barrier such as leakage reduces) causes the subthreshold region leakage current of device to increase, and causes that the circuit quiescent dissipation increases, and on-off ratio reduces.

Problem at device subthreshold region leakage current increases has proposed some new construction devices and has been improved in the document.According to the prediction of ITRS2002, ultra-thin body SOI, FinFET, vertical channel device, planar double-gated devices is the alternative structure that solves short channel effect.From with the compatible degree of conventional cmos planar technique, the FinFET device is most possible at present device architecture (X.Huang, W.-C.Lee, the C.Kuo that realizes suitability for industrialized production, D.Hisamoto, L.Chang, J.Kedzierski, E.Anderson, H.Takeuchi, Y.-K.Choi, K.Asano, V.Subramanian, T.-J.King, J.Bokor, C.Hu, " Sub-50nm P-channel FinFET; " IEEE Trans.Electron Devices, vol.48, pp.880-886, May 2001).

The design feature of FinFET device is that the channel region of device is to obtain by etching, stands upright on the substrate.Such structure makes that the FinFET device is that a double-gate structure setting can be made three grid structures, can effectively suppress short channel effect like this.Therefore, the subthreshold region leakage current of FinFET device can access effective inhibition (Y.-K.Choi, N.Lindert, P.Xuan, S.Tang, D.Ha, E.Anderson, T.-J.King, J.Bokor, C.Hu, " Sub-20nm CMOS FinFETtechnologies; " in IEDM Tech.Dig., 2001, pp.421-424).But, the inferior position of FinFET device is that the electrology characteristic of its work on the SOI sheet is very good, if but when doing on the body silicon chip, owing to the leakage path that exists between leaking in the source, the subthreshold value characteristic of the FinFET on the very big body in other words of the leakage current therebetween silicon is undesirable.

At document [B.Yu, L.Chang, S.Ahmed, H.Wang, S.Bell, C.-Y.Yang, C.Tabery, C.Ho, Q.Xiang, T.-J.King, J.Bokor, C.Hu, M.-R.Lin, D.Kyser, " FinFET scaling to 10nm gate length, " in IEDM Tech.Dig., 2002, pp.251-254] in, FinFET preparation of devices method mainly is to utilize the SOI technology.

With reference to figure 1, its preparation scheme is as follows:

1, after utilizing groove isolation technique to be formed with the source region on the SOI sheet, utilizes electron beam lithography fin district;

2, the threshold value adjustment is injected, oxidation sacrifice layer then, and the etching surface of level and smooth fin is that raceway groove is prepared;

3, the growth oxide layer forms grid oxide layer;

4, deposit polysilicon, mixing forms polysilicon gate;

5, form polysilicon gate according to the channel length etch polysilicon;

6, the corrosion oxidation layer exposes monocrystalline silicon;

7, the selective epitaxy growth and the formation source-drain area that mixes are later on the same with conventional cmos technology;

Owing to adopted the SOI technology in this technology, and the cost of SOI sheet is than higher, and the radiating effect of device is very bad, and has used epitaxy technology.Therefore be applied to industrial integrated easy degree and production efficiency all poor.。

Summary of the invention

The invention provides a kind of method that realizes the FinFET device on body silicon, both utilized the good electric property of SOI-FinFET device architecture, reduce cost simultaneously, improve integrated level, heat dispersion has also obtained improving preferably.

The preparation method of quasi dual gate field effect transistor, step comprises:

(1) on the body silicon chip, ion injects the source leakage is mixed, and is formed with the source region;

(2) etching fin district and source-drain area form the figure of " worker " font;

(3) deposit silicon nitride protection fin district continues etch silicon simultaneously, carries out oxidation, forms the accurate soi structure in fin district;

(4) preparation isolated area, gate medium, gate electrode adopt conventional cmos technology to finish subsequent step, finish until the accurate SOI-FinFET element manufacturing based on the body silicon technology.

Further, can be not exclusively clean when oxidation forms accurate soi structure the whole oxidations of silicon below the fin district, keep one deck silicon between the silica, be used for the heat dispersion of enhance device.

Technique effect of the present invention: utilized deposit silicon nitride to protect the fin district accurate soi structure in oxidation formation fin district then, technology is easy, and is with low cost.Be embodied as following characteristics:

1, the present invention has reduced the requirement to the lithography alignment precision.General FinFET preparation method requires very high to alignment precision, this method is because this problem has been avoided in the ingenious design of processing step.

2, the present invention has realized the FinFET structure of the accurate SOI of part on body silicon.The processing step of not only avoiding the lifting source to leak, and thoroughly removed possible leak channel, make the short-channel effect of device obtain very big improvement.

3, the present invention's trapezoid of having overcome fin to a certain extent distributes, and makes it level off to desirable rectangle more, improves the short channel effect of device.

4, this technology has realized the stressed channels device of FinFET for the first time, has improved the performance of device greatly.Because for the technology of general FinFET, stressed channels can't be realized.

Description of drawings

Below in conjunction with accompanying drawing, describe the present invention in detail.

Fig. 1-a is the FinFET device architecture schematic diagram based on SOI, and Fig. 1-b is the generalized section based on the FinFET device of SOI; Among the figure: drain contact district, 1-source, the 2-channel region, the 3-gate medium, the 4-polysilicon gate, the 5-substrate, the 6-SOI sheet bury oxygen;

Fig. 2-a is the FinFET device architecture schematic diagram based on body silicon, and Fig. 2-b is the generalized section based on the FinFET device of body silicon; Among the figure: drain contact district, 01-source, 02-channel region, 03-gate medium, 04-polysilicon gate, 05-substrate, the oxide layer of the accurate SOI of 06-.

Embodiment

With reference to figure 2, according to technical scheme of the present invention, a specific embodiment is carried out on four inches body silicon chip, and domain is identical, as follows with common MOSFET domain:

1. dry-oxygen oxidation 300_, LPCVD 400_ silicon nitride;

2. photoetching: active area version;

3.RIE etch silicon nitride keeps 250_ silicon dioxide at least;

4. an injection: inject B ⁺, energy is 40keV, dosage is 5 * 10 ¹⁴/ cm ²

5. the cleaning of removing photoresist;

6.LOCOS oxidation 4000_;

7. deposit polysilicon 4000_;

8. deposit silicon nitride 700_;

9. electron beam lithography fin district;

10.RIE silicon nitride 700_;

11.ICP polysilicon 4000_;

12. silicon oxide deposition 500_;

13.RIE silica 500_ forms side wall;

14. inject As ⁺, energy is 60keV, dosage is 2 * 10 ¹⁵/ cm ²

15. it is clean to float silicon dioxide;

16. electron beam lithography;

17.RIE nitrogenize silicon/oxidative silicon;

18.ICP monocrystalline silicon, the cleaning of removing photoresist;

19. deposit silicon nitride 400_, etch silicon nitride 400_ forms side wall;

20.ICP monocrystalline silicon 2000_, oxidation 400_ forms accurate soi structure;

21. boil silicon nitride with phosphoric acid, go clean;

22. wet oxygen environmental oxidation 300_ floats silica 300_, accurately control precision;

23. long grid oxygen 50_;

24. deposit polysilicon gate 3000_ injects P ⁺, energy is 60keV, dosage is 1 * 10 ¹⁵/ cm ²Form control gate;

25. electron beam lithography definition polysilicon gate, the ICP polysilicon forms control gate;

26.LPCVD silicon dioxide 6000_ does passivation layer;

27. photoetching: the empty version of lead-in wire;

28.RIE etching silicon dioxide 6000_ uses the BHF wet etching clean again, forms fairlead;

The cleaning 29. remove photoresist;

30. sputter 50～700_ Ti, 1.0～1.2 μ m AlSi;

31. photoetching: metal lead wire version;

32.RIE etching Ti/AlSi;

The cleaning 33. remove photoresist;

34. alloying: N ₂+ H ₂In 430 ℃ of down annealing 30 minutes.

Promptly make based on the accurate SOI-FinFET device on the body silicon.

Claims (2)

1, a kind of preparation method of quasi dual gate field effect transistor, step comprises:

(1) on the body silicon chip, ion injects the source leakage is mixed, and is formed with the source region;

(2) etching fin district and source-drain area form the figure of " worker " font;

(3) deposit silicon nitride protection fin district continues etch silicon simultaneously, carries out oxidation, forms the accurate soi structure in fin district;

(4) preparation isolated area, gate medium, gate electrode adopt conventional cmos technology to finish subsequent step, finish until the accurate SOI-FinFET element manufacturing based on the body silicon technology.

2, the preparation method of quasi dual gate field effect transistor as claimed in claim 1 is characterized in that: unclean when oxidation forms accurate soi structure the whole oxidations of silicon below the fin district, keep one deck silicon between the silica.

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