CN1619807A - Substrate including integrated circuit chip and integrated circuit on said substrate - Google Patents
Substrate including integrated circuit chip and integrated circuit on said substrate Download PDFInfo
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- CN1619807A CN1619807A CN 200410100344 CN200410100344A CN1619807A CN 1619807 A CN1619807 A CN 1619807A CN 200410100344 CN200410100344 CN 200410100344 CN 200410100344 A CN200410100344 A CN 200410100344A CN 1619807 A CN1619807 A CN 1619807A
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- chip
- integrated circuit
- substrate
- insulated substrate
- metal coupling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- Wire Bonding (AREA)
- Liquid Crystal (AREA)
Abstract
A IC chip structure contains a chip, a insulation substrate and a rubber layer, the chip contains a chip unit and plurality of metal convex blocks which set on the first surface of chip unit, each metal convex block has a patterned pressing fixing face, insulation substrate has plurality of electrode pads matched respectively to metal convex blocks, each electrode pad has a second surface, rubber film layer is set between chip and insulation substrate and covering these metal convex blocks and electrode pads, plurality of conductor patterns are set on the pressing fixing face or relative second surface.
Description
Technical field
The present invention relates to a kind of integrated circuit (IC) chip, its assembling structure and flat display apparatus, relate in particular to and a kind ofly be suitable for joint on glass (COG) structure packing technique and need do not adopt the integrated circuit (IC) chip and the assembling structure thereof of anisotropy conducting film (ACF).
Background technology
Common flat display apparatus for example among LCD (LCD) or the plasma display (PDP), all adopts semiconductor subassemblies such as integrated circuit (IC) chip at present, in order to the demonstration of control image.In the structure dress of IC chip, and joint on glass (Chip-On-Glass, COG) assembling structure is a kind of mode commonly used at present, its structure is that the direct structure of driving IC chip is loaded on the insulated substrate of flat display apparatus.
See also Figure 1A and Figure 1B, existing IC chip COG assembling structure is described.Shown in Figure 1A, IC chip 20 is provided with a plurality of metal couplings 210, then is provided with the electronic pads 110 corresponding to metal coupling 210 on the insulated substrate 10.When carrying out the structure dress, be anisotropy conducting film (the Anisotropic Conductive Film that coating contains conducting particles 310 on insulated substrate 10, ACF) 30, again IC chip 20 is pressed on insulated substrate 10, shown in Figure 1B, and impose suitable pressure, temperature and time control, make insulated substrate 10 and IC chip 20 see through anisotropy conducting film 30 and bind, and produce by conducting particles 310 between corresponding metal coupling 210 and the electronic pads 110 and electrically conduct.Generally speaking, the protrusion length of each metal coupling 210 equates substantially, and its stitching surface all is arranged to the plane, the uniformity when so more easily guaranteeing pressing usually.
Yet, the conducting particles 310 that is contained in the anisotropy conducting film 30 might not scatter evenly, might be lower or higher in the density of some regional conducting particles 310 just, therefore when carrying out the structure dress, may have problems because conducting particles 310 scatters uneven.
For example, shown in Fig. 1 C, when IC chip 20 is pressed on insulated substrate 10, if do not contain conducting particles 310 just as anisotropy conducting film between metal coupling 210 and the electronic pads 110 30 as the regional A, then promptly can impedance between metal coupling 210 and the electronic pads 110 excessive, can't effective constitution electrically conduct.
In addition, shown in Fig. 1 D, when IC chip 20 is pressed on insulated substrate 10, if conducting particles 310 distributes comparatively intensive in certain zone of anisotropy conducting film 30, promptly may as area B, produce short circuit phenomenon, and then influence the transmission of control signal at adjacent metal projection 210.
In addition, anisotropy conducting film 30 is owing to add conducting particles 310, its material cost is not low, and the granular size (for example conducting particles can be the particle of 5 microns of diameters) that the size in the gap of circuits such as metal coupling 210 and electronic pads 110 is subjected to conducting particles 310 limits, and circuit can't be provided with more intensive.In addition, the phenomenon of above-mentioned conducting particles 310 skewness even can't effective constitution not electrically conduct, or produces short circuit phenomenon as Fig. 1 D as Fig. 1 C, but still may local produce impedance and increase or electrically conduct phenomenon such as bad.
Summary of the invention
In view of this, one object of the present invention promptly is to propose a kind of integrated circuit (IC) chip and assembling structure thereof, improved at existing COG structure packing technique, make it need not adopt the anisotropy conducting film can carry out the structure dress, the problem that so can avoid existing COG structure packing technique to be taken place.
The present invention discloses a kind of integrated circuit (IC) chip, comprises a chip body, a plurality of metal coupling and a plurality of conductor pattern.The chip body has a first surface, and metal coupling is arranged at the first surface of chip body, and each metal coupling has the stitching surface of a patterning.A plurality of conductor pattern are arranged on the stitching surface respectively.
In addition, the present invention also discloses a kind of IC package structure, comprises an integrated circuit (IC) chip, an insulated substrate and an adhesive film.Integrated circuit (IC) chip has a chip body and a plurality of metal coupling.Metal coupling is arranged at the first surface of chip body, and each metal coupling has a stitching surface.Insulated substrate has a plurality of electronic padses that correspond respectively to metal coupling, and each electronic pads has a second surface.Adhesive film is arranged between integrated circuit (IC) chip and the insulated substrate, and coats those metal couplings and those electronic padses.Wherein, on stitching surface or the second surface, be provided with a plurality of conductor pattern.
In addition, the present invention also discloses a kind of flat display apparatus, comprises a drive IC, a display floater and an adhesive film.Drive IC has a chip body and a plurality of metal coupling, and metal coupling is arranged at a surface of chip body, and each metal coupling has a stitching surface.Display floater has a plurality of electronic padses, corresponds respectively to metal coupling, and each electronic pads has a second surface.Adhesive film is arranged between drive integrated circult chip and the display floater, and coats those metal couplings and those electronic padses.Wherein, on stitching surface or the second surface, be provided with a plurality of conductor pattern.
In each form of the invention described above, conductor pattern can be shape hemispherical or that other is suitable for making, and the diameter of conductor pattern to be roughly the 3-15 micron preferable.
In addition, the present invention also discloses a kind of IC package structure, comprises an integrated circuit (IC) chip, an insulated substrate and an adhesive film.Integrated circuit (IC) chip has a chip body and a plurality of metal coupling.Metal coupling is arranged at the first surface of chip body, and each metal coupling has a stitching surface, and wherein, stitching surface is provided with a plurality of first conductor pattern.Insulated substrate has a plurality of electronic padses that correspond respectively to metal coupling, and each electronic pads has a second surface, and wherein, second surface is provided with a plurality of second conductor pattern.Adhesive film is arranged between integrated circuit (IC) chip and the insulated substrate, and coats those metal couplings and those electronic padses.
In addition, the present invention also discloses a kind of flat display apparatus, comprises a drive IC, a display floater and an adhesive film.Drive IC has a chip body and a plurality of metal coupling, and metal coupling is arranged at a surface of chip body, and each metal coupling has a stitching surface, and wherein, stitching surface is provided with a plurality of first conductor pattern.Display floater has a plurality of electronic padses, corresponds respectively to metal coupling, and each electronic pads has a second surface, and wherein, second surface is provided with a plurality of second conductor pattern.Adhesive film is arranged between drive integrated circult chip and the display floater, and coats those metal couplings and those electronic padses.
In each form of the invention described above; first conductor pattern and second conductor pattern can be metallic particles or the corresponding a plurality of grooves that are embedded in metallic particles; its shape can be shape hemispherical or that other is suitable for making, and its diameter to be roughly the 3-15 micron preferable.
For above-mentioned and other purpose of the present invention, feature and advantage can be become apparent, several concrete preferred embodiments cited below particularly, and conjunction with figs. elaborates.
Description of drawings
Figure 1A is the schematic diagram before existing joint on glass (COG) assembling structure engages;
Figure 1B is the schematic diagram after the COG assembling structure of Figure 1A engages;
Fig. 1 C is that the COG assembling structure of Figure 1A engages bad schematic diagram;
Fig. 1 D is the schematic diagram that the COG assembling structure of Figure 1A is short-circuited;
Fig. 2 is the schematic diagram of the integrated circuit chip structure of first embodiment of the invention;
Fig. 3 is the schematic diagram of the IC package structure of second embodiment of the invention;
Fig. 4 is the schematic diagram of the IC package structure of third embodiment of the invention;
Fig. 5 is the schematic diagram of the IC package structure of fourth embodiment of the invention;
Fig. 6 is the schematic diagram of the IC package structure of fifth embodiment of the invention;
Fig. 7 is the schematic diagram of the IC package structure of sixth embodiment of the invention;
Fig. 8 is the schematic diagram of the IC package structure of seventh embodiment of the invention.
Embodiment
First embodiment
Below see also Fig. 2, the structure of integrated circuit (IC) chip of the present invention is described with an embodiment.
As shown in Figure 2, the integrated circuit (IC) chip of present embodiment comprises a chip body 20, a plurality of metal coupling 210 and as a plurality of metallic particles 215 of a plurality of conductor pattern.Chip body 20 has a first surface, lower surface promptly shown in Figure 2.Metal coupling 210 is arranged at the first surface of chip body 20, and each metal coupling 210 has the stitching surface of a patterning.Metallic particles 215 is as conductor pattern, is arranged on the stitching surface respectively.The shape of metallic particles 215 can be hemispherical, and it is preferable that its diameter is roughly the 3-15 micron, also can be arranged to suitable size according to the circuit demand of integrated circuit (IC) chip.So, metallic particles 215 can replace the conducting particles in the existing COG assembling structure.
Second embodiment
Please again referring to Fig. 3, the structure the when integrated circuit (IC) chip that the second embodiment of the present invention is described is carried out the structure dress.The IC package structure of Fig. 3 comprises an integrated circuit (IC) chip 20, an insulated substrate 10 and an adhesive film 40.The structural similarity of integrated circuit (IC) chip 20 and Fig. 2, the first surface of its chip body is provided with a plurality of metal couplings 210, and each metal coupling 210 has the stitching surface of a patterning, is respectively arranged with the hemispheric metallic particles 215 as a plurality of conductor pattern on each stitching surface.Insulated substrate 10 is to comprise glass substrate or plastic base, and has a plurality of electronic padses 110 that correspond respectively to metal coupling 210, and each electronic pads 110 has a second surface (upper surface).When the stitching surface of metal coupling 210 is pressed on the second surface of corresponding electronic pads 110 respectively, because stitching surface is provided with hemispheric metallic particles 215, therefore, each metal coupling 210 of correspondence can produce by the metallic particles 215 as a plurality of conductor pattern with each electronic pads 110 and electrically conduct.In addition, electrically conduct owing to can produce by metallic particles 215 between metal coupling 210 and the electronic pads 110, therefore set adhesive film 40 need not contain conducting particles between integrated circuit (IC) chip 20 and the insulated substrate 10, can adopt the glued membrane that generally has tackness, clad metal projection 210 and electronic pads 110, make integrated circuit (IC) chip 20 and insulated substrate 10 fluid-tight engagement, do not need the higher anisotropy conducting film of use cost.
The 3rd embodiment
Please again referring to Fig. 4, the structure the when integrated circuit (IC) chip that the third embodiment of the present invention is described is carried out the structure dress.The IC package structure of Fig. 4 comprises an integrated circuit (IC) chip 20, an insulated substrate 10 and an adhesive film 40.The structural similarity of integrated circuit (IC) chip 20 and Fig. 2, the first surface of its chip body is provided with a plurality of metal couplings 210, and each metal coupling 210 has the stitching surface of a patterning, is respectively arranged with the hemispheric metallic particles 215 as a plurality of first conductor pattern on each stitching surface.Insulated substrate 10 comprises glass substrate or plastic base, and have a plurality of electronic padses 110 that correspond respectively to metal coupling 210, each electronic pads 110 has a second surface (upper surface), also be provided with a plurality of metallic particles 115 at second surface, and the metallic particles 115 of the metallic particles 215 of the stitching surface setting of metal coupling 210 and the second surface setting of electronic pads 110 is the positions that are positioned at pressing in correspondence with each other as a plurality of second conductor pattern.When the stitching surface of metal coupling 210 is pressed on the second surface of corresponding electronic pads 110 respectively, because the stitching surface of metal coupling 210 is provided with hemispheric metallic particles 215, and the second surface of electronic pads 110 also is provided with the metallic particles 115 of pressing in correspondence with each other, therefore, each metal coupling 210 of correspondence can produce by metallic particles 115 and 215 with each electronic pads 110 and electrically conduct.In addition, electrically conduct owing to can produce by metallic particles 115 and 215 between metal coupling 210 and the electronic pads 110, therefore set adhesive film 40 need not contain conducting particles between integrated circuit (IC) chip 20 and the insulated substrate 10, can adopt the glued membrane that generally has tackness, clad metal projection 210 and electronic pads 110, make integrated circuit (IC) chip 20 and insulated substrate 10 fluid-tight engagement, do not need the higher anisotropy conducting film of use cost.
The 4th embodiment
Please again referring to Fig. 5, the structure the when integrated circuit (IC) chip that the fourth embodiment of the present invention is described is carried out the structure dress.The IC package structure of Fig. 5 comprises an integrated circuit (IC) chip 20, an insulated substrate 10 and an adhesive film 40.The structural similarity of integrated circuit (IC) chip 20 and Fig. 2, the first surface of its chip body is provided with a plurality of metal couplings 210, and each metal coupling 210 has the stitching surface of a patterning, is respectively arranged with the hemispheric metallic particles 215 as a plurality of first conductor pattern on each stitching surface.Insulated substrate 10 comprises glass substrate or plastic base, and have a plurality of electronic padses 110 that correspond respectively to metal coupling 210, each electronic pads 110 has a second surface (upper surface), also be provided with a plurality of metallic particles 115 at second surface, and the metallic particles 215 of the stitching surface setting of metal coupling 210 is to be positioned at the position (interlacing) that mutual dislocation engages with the metallic particles 115 of the second surface setting of electronic pads 110 as a plurality of second conductor pattern.When the stitching surface of metal coupling 210 is pressed on the second surface of corresponding electronic pads 110 respectively, because the stitching surface of metal coupling 210 is provided with hemispheric metallic particles 215, and the second surface of electronic pads 110 also is provided with the metallic particles 115 of mutual dislocation engaging, therefore, Dui Ying each metal coupling 210 can engage to produce with 215 mutual dislocation with each electronic pads 110 and electrically conducts by metallic particles 115.In addition, electrically conduct owing to engage to produce by metallic particles 115 and 215 dislocation between metal coupling 210 and the electronic pads 110, therefore set adhesive film 40 need not contain conducting particles between integrated circuit (IC) chip 20 and the insulated substrate 10, therefore can adopt the glued membrane that generally has tackness, clad metal projection 210 and electronic pads 110, make integrated circuit (IC) chip 20 and insulated substrate 10 fluid-tight engagement, do not need the higher anisotropy conducting film of use cost.
The 5th embodiment
Please again referring to Fig. 6, the structure the when integrated circuit (IC) chip that the fifth embodiment of the present invention is described is carried out the structure dress.The IC package structure of Fig. 6 comprises an integrated circuit (IC) chip 20, an insulated substrate 10 and an adhesive film 40.Integrated circuit (IC) chip 20 among Fig. 6 does not adopt integrated circuit chip structure shown in Figure 2, but adopts general existing integrated circuits chip.Each metal coupling 210 of integrated circuit (IC) chip 20 has the stitching surface of a patterning, but metallic particles is not set on each stitching surface, and only is provided as a plurality of metallic particles 115 of a plurality of conductor pattern at the second surface of a plurality of electronic padses 110 of insulated substrate 10.When the stitching surface of metal coupling 210 is pressed on the second surface of corresponding electronic pads 110 respectively, because the second surface of electronic pads 110 is provided with the metallic particles 115 as a plurality of conductor pattern, therefore, each metal coupling 210 of correspondence can produce by metallic particles 115 with each electronic pads 110 and electrically conduct.In addition, electrically conduct owing to can produce by metallic particles 115 between metal coupling 210 and the electronic pads 110, therefore set adhesive film 40 need not contain conducting particles between integrated circuit (IC) chip 20 and the insulated substrate 10, therefore can adopt the glued membrane that generally has tackness, clad metal projection 210 and electronic pads 110, make integrated circuit (IC) chip 20 and insulated substrate 10 fluid-tight engagement, do not need the higher anisotropy conducting film of use cost.
The 6th embodiment
Please again referring to Fig. 7, the structure the when integrated circuit (IC) chip that the sixth embodiment of the present invention is described is carried out the structure dress.The IC package structure of Fig. 7 comprises an integrated circuit (IC) chip 20, an insulated substrate 10 and an adhesive film 40.The structural similarity of integrated circuit (IC) chip 20 and Fig. 2, the first surface of its chip body is provided with a plurality of metal couplings 210, and each metal coupling 210 has the stitching surface of a patterning, is respectively arranged with the hemispheric metallic particles 215 as a plurality of first conductor pattern on each stitching surface.Insulated substrate 10 comprises glass substrate or plastic base, and have a plurality of electronic padses 110 that correspond respectively to metal coupling 210, each electronic pads 110 has a second surface (upper surface), then is provided with a plurality of grooves 125 that correspondence is embedded in a plurality of second conductor pattern of conduct of metallic particles 215 at second surface.When the stitching surface of metal coupling 210 is pressed on the second surface of corresponding electronic pads 110 respectively, because the stitching surface of metal coupling 210 is provided with hemispheric metallic particles 215, and the second surface of electronic pads 110 is provided with corresponding groove 125, therefore, each corresponding metal coupling 210 can electrically conduct by chimeric generation of metallic particles 215 with groove 125 with each electronic pads 110.In addition, owing to electrically conduct by chimeric can the generation of metallic particles 215 between metal coupling 210 and the electronic pads 110 with groove 125, therefore set adhesive film 40 need not contain conducting particles between integrated circuit (IC) chip 20 and the insulated substrate 10, therefore can adopt the glued membrane that generally has tackness, clad metal projection 210 and electronic pads 110, make integrated circuit (IC) chip 20 and insulated substrate 10 fluid-tight engagement, do not need the higher anisotropy conducting film of use cost.
The 7th embodiment
Please again referring to Fig. 8, the structure the when integrated circuit (IC) chip that the seventh embodiment of the present invention is described is carried out the structure dress.The IC package structure of Fig. 8 comprises an integrated circuit (IC) chip 20, an insulated substrate 10 and an adhesive film 40.Integrated circuit (IC) chip 20 among Fig. 8 does not adopt integrated circuit (IC) chip shown in Figure 2, but adopts general existing integrated circuits chip 20.Each metal coupling 210 of integrated circuit (IC) chip 20 has the stitching surface of a patterning, but metallic particles is not set on each stitching surface, but only be provided as a plurality of metallic particles 115 of a plurality of second conductor pattern at the second surface of a plurality of electronic padses 110 of insulated substrate 10, then be provided with a plurality of grooves 225 that correspondence is embedded in a plurality of first conductor pattern of conduct of metallic particles 115 on the stitching surface of metal coupling 210.When the stitching surface of metal coupling 210 is pressed on the second surface of corresponding electronic pads 110 respectively, because the second surface of electronic pads 110 is provided with metallic particles 115, then be provided with corresponding groove 225 on the stitching surface of metal coupling 210, therefore, each corresponding metal coupling 210 can electrically conduct by chimeric generation of metallic particles 115 with groove 225 with each electronic pads 110.In addition, owing to electrically conduct by chimeric can the generation of metallic particles 115 between metal coupling 210 and the electronic pads 110 with groove 225, therefore set adhesive film 40 need not contain conducting particles between integrated circuit (IC) chip 20 and the insulated substrate 10, therefore can adopt the glued membrane that generally has tackness, clad metal projection 210 and electronic pads 110, make integrated circuit (IC) chip 20 and insulated substrate 10 fluid-tight engagement, do not need the higher anisotropy conducting film of use cost.
As mentioned above, in the IC package structure of various embodiments of the present invention, because at least one is provided with the metallic particles 115 and/or 215 as a plurality of conductor pattern between metal coupling 210 and the electronic pads 110, can produce by metallic particles 115 and/or 215 and to electrically conduct, therefore do not need the higher anisotropy conducting film of use cost as engaging the glued membrane of integrated circuit (IC) chip 20 with insulated substrate 10, only need to adopt generally have tackness glued membrane, escapable cost.But the foregoing description does not limit the material of adhesive film yet, still can use anisotropy conducting film or other glued membrane as adhesive film according to need.
In addition, in the IC package structure of the various embodiments described above, because adhesive film 40 does not contain conducting particles, therefore can be as existing COG assembling structure do not electrically conduct bad or phenomenon such as short circuit because of conducting particles scatters inhomogeneous the generation, and the gap of circuits such as metal coupling 210 and electronic pads 110 is not subjected to size restrictions yet, can be arranged to comparatively intensive circuit on demand.
In addition, metallic particles 215 as a plurality of conductor pattern is the stitching surfaces that directly are created on metal coupling 210, it can be made by semiconductor technology or other suitable technology, shape is not limited to hemispherical or graininess, can be made according to the shape of manufacturing that technology is allowed, and can conductor pattern evenly be distributed, so can control the current stability of assembling structure easily.
In each form of the invention described above; first conductor pattern and second conductor pattern can be metallic particles or the corresponding a plurality of grooves that are embedded in metallic particles; its shape can be shape hemispherical or that other is suitable for making, and its diameter to be roughly the 3-15 micron preferable.
The technology of various embodiments of the present invention can suitably be applied to the occasion of any IC package structure, for example, common flat display apparatus, for example LCD or plasma display etc., can use the IC package structure described in the foregoing description and carry out the encapsulation of its driving IC chip, with insulated substrate 10 as the display floater of flat display apparatus, integrated circuit (IC) chip 20 driving IC chip as flat display apparatus.
Though the present invention discloses as above with concrete preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; still can make various modifications and variations, so protection scope of the present invention is when looking appended being as the criterion that claim defined.
Claims (19)
1. integrated circuit comprises:
One chip body has a lower surface;
A plurality of metal couplings are arranged at this lower surface, and those metal couplings have the stitching surface of a patterning.
2. integrated circuit as claimed in claim 1, wherein the stitching surface of this patterning is shaped as hemisphere.
3. integrated circuit as claimed in claim 2, wherein this hemispheric diameter range is approximately 3 to 15 microns.
4. integrated circuit as claimed in claim 1 also comprises:
One insulated substrate;
A plurality of electronic padses be formed on this insulated substrate the position corresponding to those metal couplings, and the upper surface of those electronic padses have the pattern corresponding to the stitching surface of this patterning; And
One adhesive film is arranged between the lower surface and this insulated substrate of this chip body, and coats those metal couplings and those electronic padses.
5. integrated circuit as claimed in claim 4, wherein this insulated substrate comprises glass substrate or plastic base.
6. integrated circuit as claimed in claim 4, wherein the pattern of the upper surface of those electronic padses is a plurality of grooves or a plurality of metallic particles.
7. integrated circuit as claimed in claim 1 also comprises:
One insulated substrate;
A plurality of electronic padses are formed on this insulated substrate the position corresponding to those metal couplings, and the upper surface of those electronic padses has the pattern that interlaces in the stitching surface of this patterning; And
One adhesive film is arranged between the lower surface and this insulated substrate of this chip body, and coats those metal couplings and those electronic padses.
8. integrated circuit as claimed in claim 7, wherein this insulated substrate comprises glass substrate or plastic base.
9. integrated circuit as claimed in claim 7, wherein the pattern of the upper surface of those electronic padses is a plurality of metallic particles.
10. substrate that comprises integrated circuit (IC) chip comprises:
One chip body has a lower surface;
A plurality of metal couplings are arranged at this lower surface, and those metal couplings have the stitching surface of a patterning;
One insulated substrate;
A plurality of electronic padses be formed on this insulated substrate the position corresponding to those metal couplings, and the upper surface of those electronic padses have the pattern corresponding to the stitching surface of this patterning; And
One adhesive film is arranged between the lower surface and this insulated substrate of this chip body, and coats those metal couplings and those electronic padses.
11. the substrate that comprises integrated circuit (IC) chip as claimed in claim 10, wherein the stitching surface of this patterning is shaped as hemisphere.
12. the substrate that comprises integrated circuit (IC) chip as claimed in claim 11, wherein this hemispheric diameter range is approximately 3 to 15 microns.
13. the substrate that comprises integrated circuit (IC) chip as claimed in claim 10, wherein the pattern of the upper surface of those electronic padses is a plurality of grooves or a plurality of metallic particles.
14. the substrate that comprises integrated circuit (IC) chip as claimed in claim 10, wherein this insulated substrate comprises glass substrate or plastic base.
15. a substrate that comprises integrated circuit (IC) chip comprises:
One chip body has a lower surface;
A plurality of metal couplings are arranged at this lower surface, and those metal couplings have the stitching surface of a patterning;
One insulated substrate;
A plurality of electronic padses are formed on this insulated substrate the position corresponding to those metal couplings, and the upper surface of those electronic padses has the pattern that interlaces in the stitching surface of this patterning; And
One adhesive film is arranged between the lower surface and this insulated substrate of this chip body, and coats those metal couplings and those electronic padses.
16. the substrate that comprises integrated circuit (IC) chip as claimed in claim 15, wherein the stitching surface of this patterning is shaped as hemisphere.
17. the substrate that comprises integrated circuit (IC) chip as claimed in claim 16, wherein this hemispheric diameter range is approximately 3 to 15 microns.
18. the substrate that comprises integrated circuit (IC) chip as claimed in claim 15, wherein this insulated substrate comprises glass substrate or plastic base.
19. the substrate that comprises integrated circuit (IC) chip as claimed in claim 15, wherein the pattern of the upper surface of those electronic padses is a plurality of grooves or a plurality of metallic particles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410100344 CN1619807B (en) | 2004-12-06 | 2004-12-06 | Substrate including integrated circuit chip and integrated circuit on said substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410100344 CN1619807B (en) | 2004-12-06 | 2004-12-06 | Substrate including integrated circuit chip and integrated circuit on said substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1619807A true CN1619807A (en) | 2005-05-25 |
| CN1619807B CN1619807B (en) | 2011-03-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200410100344 Active CN1619807B (en) | 2004-12-06 | 2004-12-06 | Substrate including integrated circuit chip and integrated circuit on said substrate |
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| CN (1) | CN1619807B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416810C (en) * | 2006-03-09 | 2008-09-03 | 南茂科技股份有限公司 | Semiconductor component and its making method |
| CN104810297A (en) * | 2014-01-23 | 2015-07-29 | 罗伯特·博世有限公司 | Method for manufacturing a flip chip circuit device and the flip chip circuit device |
| CN106658988A (en) * | 2017-02-07 | 2017-05-10 | 武汉华星光电技术有限公司 | Display, circuit board, and pin structure of circuit board |
| CN111524465A (en) * | 2020-06-11 | 2020-08-11 | 厦门通富微电子有限公司 | Preparation method of display device |
| CN111524466A (en) * | 2020-06-11 | 2020-08-11 | 厦门通富微电子有限公司 | Preparation method of display device |
| CN111564107A (en) * | 2020-06-11 | 2020-08-21 | 厦门通富微电子有限公司 | Preparation method of display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3365367B2 (en) * | 1999-09-14 | 2003-01-08 | ソニーケミカル株式会社 | COG mounting products and connection materials |
| TW506103B (en) * | 2001-08-06 | 2002-10-11 | Au Optronics Corp | Bump layout on a chip |
-
2004
- 2004-12-06 CN CN 200410100344 patent/CN1619807B/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416810C (en) * | 2006-03-09 | 2008-09-03 | 南茂科技股份有限公司 | Semiconductor component and its making method |
| CN104810297A (en) * | 2014-01-23 | 2015-07-29 | 罗伯特·博世有限公司 | Method for manufacturing a flip chip circuit device and the flip chip circuit device |
| CN106658988A (en) * | 2017-02-07 | 2017-05-10 | 武汉华星光电技术有限公司 | Display, circuit board, and pin structure of circuit board |
| WO2018145341A1 (en) * | 2017-02-07 | 2018-08-16 | 武汉华星光电技术有限公司 | Display, wiring board and pin structure thereof |
| CN111524465A (en) * | 2020-06-11 | 2020-08-11 | 厦门通富微电子有限公司 | Preparation method of display device |
| CN111524466A (en) * | 2020-06-11 | 2020-08-11 | 厦门通富微电子有限公司 | Preparation method of display device |
| CN111564107A (en) * | 2020-06-11 | 2020-08-21 | 厦门通富微电子有限公司 | Preparation method of display device |
| CN111564107B (en) * | 2020-06-11 | 2022-06-21 | 厦门通富微电子有限公司 | Preparation method of display device |
| CN111524465B (en) * | 2020-06-11 | 2022-06-21 | 厦门通富微电子有限公司 | Preparation method of display device |
| CN111524466B (en) * | 2020-06-11 | 2022-06-21 | 厦门通富微电子有限公司 | Preparation method of display device |
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| CN1619807B (en) | 2011-03-16 |
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