CN1614559A - Switching equipment of memory analog device - Google Patents
Switching equipment of memory analog device Download PDFInfo
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- CN1614559A CN1614559A CN 200410083723 CN200410083723A CN1614559A CN 1614559 A CN1614559 A CN 1614559A CN 200410083723 CN200410083723 CN 200410083723 CN 200410083723 A CN200410083723 A CN 200410083723A CN 1614559 A CN1614559 A CN 1614559A
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Abstract
A switching device is featured as having two connectors for connecting two ROM slots, operating the first mode by control to read program code sent to the first ROM slot by the first connector at time of the first connector connected to the first ROM slot to start hostboard, operating the second mode by controller to read program code sent to the second ROM slot by the second connector for execution at time of the second connector connected to the second ROM slot to start hostboard.
Description
Technical field
The invention relates to a kind of switching device,, allow the motherboard memory bank that is different from the memory analog transmission interface, can use memory analog through the transmission interface conversion particularly about a kind of switching device that is used for memory analog.
Background technology
Computer system performance is thorough now, bring the common people considerable facility, the common people can utilize the general document affairs of computer system processor, seeing through world-wide web looks for data and video signal amusement etc. is provided, but along with using common people's demand to improve day by day, the computer system performance now that makes needs constantly to promote, the most common computer system hardware interfacing equipment that is, whenever hardware interface device transmission interface or CPU (central processing unit) promote when changing to some extent, motherboard specification and Basic Input or Output System (BIOS) (BIOS), also need along with change, Basic Input or Output System (BIOS) is a firmware (Firmware), store in ROM (read-only memory) (ROM), BIOS research staff mostly transfers to bios program code one memory analog when test b IOS program code, memory analog is the ROM (read-only memory) on the emulating host computer plate, with test b IOS program code, with can be in test process, the repetition burning BIOS program code that need not expend time in be in ROM (read-only memory), and can revise bios program code at any time.
(Industry Standard Architecture, ISA) the ROM (read-only memory) slot (Socket) of transmission interface is so memory analog now all is an ISA transmission interface specification on the early stage motherboard Industry Standard Architecture only.See also Fig. 1, it is the embodiment calcspar of known memory analog, BIOS research staff is when test b IOS program code, can see through a personal computer 10, bios program code is transferred to an ISA memory analog 12, and ISA memory analog 12 needs to make signal damping through a switching device 20, could do signal and bios program code transmission with a motherboard 15, switching device 20 is provided with two ISA Memory connectors 22,24, to be connected with an ISA memory bank 17 of ISA memory analog 12 and motherboard 15 respectively.
When motherboard 15 starts, can send control signal through ISA memory bank 17 and be sent to a buffer cell 26 through ISA Memory connector 24, make signal damping, see through ISA Memory connector 22 afterwards again and be sent to ISA memory analog 12, read bios program code, it is relative when ISA memory analog 12 sees through ISA Memory connector 22 and transmits bios program codes, also must be through buffer cell 26, make signal damping, see through ISA Memory connector 24 afterwards again and be sent to ISA memory bank 17, carry out bios program code for motherboard 15, test.
Under the driving of the continuous integration and the compact tendency of the day on the mainboard architecture now, Intel (Intel) has proposed transmission interface of new generation one low pin number (Low Pin Count, LPC) transmission interface, so ISA ROM (read-only memory) slot (30 branch connecting pin) will be replaced by LPC ROM (read-only memory) slot (7 branch connecting pin) gradually, because LPC transmission interface signal pins figure place significantly reduces, can reduce volume and cost that motherboard is provided with memory bank, reduce and simplify motherboard design relatively, thereby so the LPC transmission interface is widely used in the motherboard gradually.
But present memory analog is all the transmission interface of ISA kenel, promptly can't be used in the memory bank that is provided with the LPC transmission interface, therefore, the present invention is promptly at the switching device that proposes a kind of memory analog at the problems referred to above, allow the ROM (read-only memory) slot of different transmission interfaces specification, can use memory analog, to address the above problem.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of switching device of memory analog, convertible transmission signals specification, and allow memory analog applicable to the ROM (read-only memory) slot of different transmission interfaces specification, improve the convenience on using.
Another object of the present invention, the error detecting code that is to provide a kind of switching device of memory analog, fechtable motherboard executive system routine code to start shooting selftest, and display result.
The switching device of memory analog of the present invention, include one first connector and one second connector, and relatively be connected with set one first ROM (read-only memory) slot or the one second ROM (read-only memory) slot of a motherboard, the transmission interface specification of two read-only storage slot is inequality, when first connector is connected with first ROM (read-only memory), when motherboard starts, one controller of switching device will be with one first read mode, read the system-program code that a memory analog is stored up, and system-program code is reached the first ROM (read-only memory) slot by first connector, carry out for motherboard, be connected with the second ROM (read-only memory) slot and work as second connector, when motherboard starts, controller can be with one second read mode, read the system-program code that memory analog stores up, and system-program code is reached the first ROM (read-only memory) slot by second connector, carry out for motherboard, so the present invention can allow memory analog be used in the transmission interface of different size, with the storer of emulating host computer plate, allow the research staff make things convenient for the test macro program code.
Description of drawings
Fig. 1 is the embodiment calcspar of known memory analog;
Fig. 2 is the circuit block diagram of preferred embodiment of the present invention.
Symbol description:
10 personal computers
12 ISA memory analogs
15 motherboards
17 ISA memory banks
20 switching devices
22 ISA Memory connectors
24 ISA Memory connectors
26 buffer cells
30 switching devices
31 first connectors
32 second connectors
33 the 3rd connectors
34 the 4th connectors
36 controllers
38 first displays
39 second displays
40 memory analogs
50 motherboards
52 memory read slots
54 test ports
60 personal computers
Embodiment
Seeing also Fig. 2, is the circuit block diagram of preferred embodiment of the present invention; As shown in the figure, switching device 30 of the present invention is to be used for being connected with a motherboard 50 with a memory analog 40, when the research staff uses a personal computer 60 with system-program code, be that bios program code transfers to memory analog 40 and carries out emulation testing, when motherboard 50 starts, to read the bios program code that memory analog 40 stores through ROM (read-only memory) slot 52 or test port 54, carry out for motherboard 50, at this moment, switching device 30 will be according to the transmission interface kind of ROM (read-only memory) slot 52 with test port 54, read the bios program code of memory analog 40 with suitable read mode, test port 54 is the present invention to connect the convenience of motherboard 50 set in carrying out test b IOS program code in order to allow switching device 30 that test port 54 is a LPC male end mouth in present embodiment.
The controller 36 of switching device 30 is the kinds that connect motherboard 50 transmission interfaces according to switching device 30, read bios program code and the buffering signals that memory analog 40 is stored up with suitable read mode, when the ROM (read-only memory) slot 52 of first connector 31 with ISA transmission interface specification is connected, when motherboard 50 starts, to send control signal through ROM (read-only memory) slot 52, to read bios program code, control signal will be through first connector 31 to controller 36, because of the transmission interface of the transmission interface of memory analog 40 and ROM (read-only memory) slot 52 is all block form (parallel) and the access clock pulse is also compatible, so controller 36 will read bios program code with one first read mode, first read module is that controller 36 is only made signal damping, see through the 4th connector 34 afterwards again and transfer to memory analog 40, read bios program code, bios program code will see through the 4th connector 34 with reverse path and transfer to controller 36, promptly see through first connector, 31 transmission bios program codes at last to ROM (read-only memory) slot 52, carry out for motherboard 50.
In addition, when the ROM (read-only memory) slot 52 of motherboard 50 is a LPC ROM (read-only memory) slot, and switching device 30 will connect ROM (read-only memory) slot 52 with second connector 32, because the transmission interface of memory analog 40 is different with LPC ROM (read-only memory) slot, the signal of LPC interface is transmitted as list type (serial), so controller 25 will read bios program code to memory analog 40 with one second read mode, also be about to ROM (read-only memory) slot 52 control signals transmitted and carry out the LPC interface to the ISA interface conversion, be that list type changes block form and clock pulse conversion (changing into 8MHz by 33MHz), make the transmission interface specification that meets memory analog 40, to read bios program code, and also must carry out the ISA interface to the LPC interface conversion by via controller 36 by the bios program code that memory analog 40 is read, promptly change into list type and clock pulse conversion (changing into 33MHz) by 8MHz by block form, make the transmission interface specification that meets ROM (read-only memory) slot 52, promptly bios program code is passed to ROM (read-only memory) slot 52 at last, carry out bios program code for motherboard 50 via second connector 32.
In like manner, when the test port 54 of the 3rd connector 33 and motherboard 50 is connected, controller 36 also will carry out bios program code to memory analog 40 with second read mode and read, that is the signal that test port 54 transmits carried out the LPC interface to the ISA interface conversion, can read the bios program code of memory analog 40, in addition, the bios program code of being read by memory analog 40 then carries out the ISA interface to the LPC interface conversion, make the transmission interface specification that meets test port 32, via the 3rd connector 33 bios program code is passed to test port 54 again, carry out bios program code for motherboard 50.Controller 36 of the present invention can be Application Specific Integrated Circuit (Application Specific Integrated Circuit, ASIC) or complicated programmable logical unit (Complex Programmable Logic Device, CPLD).
In addition, allow the research and development slip-stick artist for convenience in the process of test b IOS program code, know test result, switching device 30 of the present invention more is provided with one first display 38 and one second display 39, both are connected with controller 36, and can be seven-segment display, when motherboard 50 is carried out bios program code and the selftest of starting shooting (Power On Self Test, POST) time, the error detecting code that is produced in test process (post/debug code) can be delivered to the I/O port 80h and/or the 84h of motherboard 50, controller 36 of the present invention can be tackled this error detecting code and error detecting code is deciphered, and decode results is transferred to first display 38 and 39 demonstrations of second display, for research and development slip-stick artist reference,, can not need to buy in addition again and use debug (Debug) card or (POST card) to revise bios program code.
And, the debug of commonly using (Debug) card or (POST card) are mostly for being inserted in outward on the motherboard, and connection transmission interface has now developed a PCI-Express specification that high-speed transfer, but the definition of the transmission signals of this transmission interface will make the outside plug type Debug Card of commonly using can't tackle error detecting code, so use the present invention to carry out the bios program code emulation testing, fechtable is learnt test result, to revise bios program code,, very convenient for the research staff.
In sum, the ROM (read-only memory) slot 52 that switching device 30 of the present invention can provide according to motherboard 50 and the transmission interface specification of test port 54, use different connectors 31,32,33 are connected with motherboard 50, and controller 36 can be according to different transmission interface specifications, with conversion of suitable read mode or switching signal transmission interface not, so that memory analog 40 is read bios program code, carry out for motherboard 50, so memory analog 40 can be used in the ROM (read-only memory) slot 52 or the test port 54 of different transmission interfaces, in addition, switching device 30 more can be tackled motherboard 50 when the execution bios program code carries out selftest, what produced removes error code, go forward side by side row decoding and be shown in first display 38 and second display 39, for research staff's reference, very convenient.
Claims (14)
1. the switching device of a memory analog, the switching device that it is characterized in that described memory analog is with suitable read mode, allow this memory analog read the system-program code that execution is stored in this memory analog for a motherboard through one first ROM (read-only memory) slot or one second ROM (read-only memory) slot, this switching device includes:
One first connector is in order to connect this first ROM (read-only memory) slot;
One second connector is in order to connect this second ROM (read-only memory) slot;
One controller, it is to be connected with this memory analog with this first connector, this second connector;
Wherein, this first connector connects this first ROM (read-only memory) slot, when this motherboard is opened, this controller reads this system-program code with one first read mode, and see through this first connector and transfer to this first ROM (read-only memory) slot, carry out, when this second connector connects this second ROM (read-only memory) slot, when this motherboard is opened, this controller reads this system-program code with one second read mode, and see through this second connector and transfer to this second ROM (read-only memory) slot, carry out.
2. the switching device of memory analog according to claim 1, it is characterized in that: this first ROM (read-only memory) slot is an ISA ROM (read-only memory) slot, this second ROM (read-only memory) slot is a LPC ROM (read-only memory) slot, this memory analog and this first ROM (read-only memory) slot transmission interface compatibility, this first read mode directly reads this system-program code for this controller, this second read mode is changed control signals transmitted and this system-program code transmission signals between this second ROM (read-only memory) slot and this memory analog for this controller, be LPC/ISA and ISA/LPC transmission interface, to read this system-program code in this memory analog, carry out.
3. the switching device of memory analog according to claim 1 is characterized in that: the transmission signals between this first ROM (read-only memory) slot of this controller available buffer or this second ROM (read-only memory) slot and this memory analog.
4. the switching device of memory analog according to claim 1, it is characterized in that: more be provided with a test port on this motherboard, this switching device more is provided with in order to connect one the 3rd connector of this test port, the 3rd connector connects this test port, when this motherboard starts, this controller reads this system-program code with suitable read mode, and gives this test port through the 3rd connector, carries out.
5. the switching device of memory analog according to claim 4, it is characterized in that: this test port is the LPC port, this controller reads this system-program code with this second read mode, this second read mode is control signals transmitted and this system-program code transmission signals between this test port of conversion and this memory analog, be LPC/ISA and ISA/LPC transmission interface, to read this system-program code in this memory analog, carry out.
6. the switching device of memory analog according to claim 1, it is characterized in that: more be provided with one the 4th connector, the 4th connector is connected with this memory analog, this controller sees through the 4th connector, and transmission signals to this memory analog reads this system-program code.
7. the switching device of a memory analog, the switching device that it is characterized in that described memory analog is with suitable read mode, allow this memory analog read the system-program code that execution is stored in this memory analog for a motherboard through one first ROM (read-only memory) slot or one second ROM (read-only memory) slot, this switching device includes:
One first connector is in order to connect this first ROM (read-only memory) slot;
One second connector is in order to connect this second ROM (read-only memory) slot;
One controller, it is to be connected with this memory analog with this first connector, this second connector;
One display unit, it is connected with this controller, shows the test result when this controller captures this motherboard and carries out this system-program code and test;
Wherein, this first connector connects this first ROM (read-only memory) slot, when this motherboard is opened, this controller reads this system-program code with one first read mode, and see through this first connector and transfer to this first ROM (read-only memory) slot, carry out, when this second connector connects this second ROM (read-only memory) slot, when this motherboard is opened, this controller reads this system-program code with one second read mode, and see through this second connector and transfer to this second ROM (read-only memory) slot, carry out.
8. the switching device of memory analog according to claim 7 is characterized in that: this controller is the error detecting code of this motherboard of acquisition I/O port 80h, deciphers and export to be shown in this display unit.
9. the switching device of memory analog according to claim 7 is characterized in that: this controller is the error detecting code of this motherboard of acquisition I/O port 84h, deciphers and export to be shown in this display unit.
10. the switching device of memory analog according to claim 7, it is characterized in that: this first ROM (read-only memory) slot is an ISA ROM (read-only memory) slot, this second ROM (read-only memory) slot is a LPC ROM (read-only memory) slot, this memory analog and this first ROM (read-only memory) slot transmission interface compatibility, this first read mode directly reads this system-program code for this controller, this second read mode is changed control signals transmitted and this system-program code transmission signals between this second ROM (read-only memory) slot and this memory analog for this controller, be LPC/ISA and ISA/LPC transmission interface, to read this system-program code in this memory analog, carry out.
11. the switching device of memory analog according to claim 7 is characterized in that: the transmission signals between this first ROM (read-only memory) slot of this controller available buffer or this second ROM (read-only memory) slot and this memory analog.
12. the switching device of memory analog according to claim 7, it is characterized in that: more be provided with a test port on this motherboard, this switching device more is provided with in order to connect one the 3rd connector of this test port, the 3rd connector connects this test port, when this motherboard starts, this controller reads this system-program code with suitable read mode, and gives this test port through the 3rd connector, carries out.
13. the switching device of memory analog according to claim 12, it is characterized in that: this test port is the LPC port, this controller reads this system-program code with this second read mode, this second read mode is control signals transmitted and this system-program code transmission signals between this test port of conversion and this memory analog, be LPC/ISA and ISA/LPC transmission interface, to read this system-program code in this memory analog, carry out.
14. the switching device of memory analog according to claim 7, it is characterized in that: more be provided with one the 4th connector, the 4th connector is connected with this memory analog, this controller sees through the 4th connector, and transmission signals to this memory analog reads this system-program code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100837239A CN1304947C (en) | 2004-10-14 | 2004-10-14 | Switching equipment of memory analog device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100837239A CN1304947C (en) | 2004-10-14 | 2004-10-14 | Switching equipment of memory analog device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1614559A true CN1614559A (en) | 2005-05-11 |
| CN1304947C CN1304947C (en) | 2007-03-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100837239A Active CN1304947C (en) | 2004-10-14 | 2004-10-14 | Switching equipment of memory analog device |
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| CN (1) | CN1304947C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100452008C (en) * | 2007-02-16 | 2009-01-14 | 威盛电子股份有限公司 | Switching equipment of read-only storage |
| CN106934081A (en) * | 2015-12-29 | 2017-07-07 | 伊姆西公司 | Disc driver analogy method and device |
| CN109002328A (en) * | 2018-07-20 | 2018-12-14 | 郑州云海信息技术有限公司 | A kind of starting method and device storing equipment |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11167493A (en) * | 1997-12-02 | 1999-06-22 | Nec Corp | Information processor and starting method of its extended device |
| CN1123828C (en) * | 2000-03-03 | 2003-10-08 | 英业达股份有限公司 | Method and its device for display BIOS error code |
| CN1180346C (en) * | 2001-02-20 | 2004-12-15 | 技嘉科技股份有限公司 | Autoamtic safe reset method of BIOS storage in computer system |
| US6807504B2 (en) * | 2002-11-21 | 2004-10-19 | Via Technologies, Inc. | Apparatus for testing I/O ports of a computer motherboard |
-
2004
- 2004-10-14 CN CNB2004100837239A patent/CN1304947C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100452008C (en) * | 2007-02-16 | 2009-01-14 | 威盛电子股份有限公司 | Switching equipment of read-only storage |
| CN106934081A (en) * | 2015-12-29 | 2017-07-07 | 伊姆西公司 | Disc driver analogy method and device |
| CN106934081B (en) * | 2015-12-29 | 2020-03-20 | 伊姆西Ip控股有限责任公司 | Disk drive simulation method and apparatus |
| CN109002328A (en) * | 2018-07-20 | 2018-12-14 | 郑州云海信息技术有限公司 | A kind of starting method and device storing equipment |
| CN109002328B (en) * | 2018-07-20 | 2021-08-31 | 郑州云海信息技术有限公司 | Starting method and device of storage equipment |
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| Publication number | Publication date |
|---|---|
| CN1304947C (en) | 2007-03-14 |
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