CN1598757A - Design method of number mixed multipler for supporting single-instruction multiple-operated - Google Patents

Abstract

The invention discloses a design method of a mixed multiplier supporting single instruction and multiple operands, aiming to make the multiplier work in both common mode and SIMD mode. The technical solution is to design a new hybrid multiplier structure, which is composed of an operand expansion unit, a decoder, two partial product generators, a correction value generation unit, a partial product compression unit and an adder. The decoder judges the working mode and the operand type, the operand expansion unit expands the operand, and the two partial product generators each generate n/2+1 partial products and send them to the partial product compression unit. The correction value generation component is a correction value for the high-order product when generating SIMD mode. The partial product compression unit compresses the partial product and the correction value into two 4n-bit numbers, and the adder adds them to obtain a 4n-bit product. In normal mode, it is the product of two 2n-bit operands; in SIMD mode, the lower 2n bits are the product of the lower n-bit multiplication, and the upper 2n bits are the product of the upper n-bit multiplication.

Description

A Design Method of Hybrid Multiplier Supporting Single Instruction Multiple Operands

Technical field: the present invention relates to the design method of the multiplier in digital signal processor (DSP) and high-performance microprocessor, especially the design method of the multiplier that supports single instruction multiple operand (SIMD).

Background Art: The multiplier is an important part in DSP and microprocessor, and multiplication operation is widely used in fields such as scientific calculation and digital signal processing. Traditional multipliers are generally composed of operand expansion units, decoders, partial product generation units, partial product compression units, and a propagated carry adder (CPL). Partial product generation is a key technology in the design of high-performance multipliers. The 2-bit Booth encoding circuit is widely used in multiplier design because of its simple design and few partial products. With the development of information technology, the processing of multimedia data such as video and audio has become an important application field of digital signal processing. A notable feature of multimedia data processing is to perform the same operation on multiple small data items. In order to improve the ability of multimedia data processing, many processors have added SIMD instructions, so that the processor can execute multiple short data operations by executing one instruction. . There are two ways to implement SIMD instructions, one is to set a special SIMD unit, which can only perform SIMD operations, such as the MMX unit in the Pentium II processor; the other is to improve the traditional scalar arithmetic unit, so that It not only maintains scalar computing capability, but also has the capability to perform SIMD operations, such as Intel(R) XScale ^(TM) . The latter implementation method can increase its multimedia data processing ability several times without making major changes to the architecture, so it has been widely used in the design of embedded microprocessors such as DSP, such as TI (Texas Instruments) and AD (Analog Devices) The design of the company's latest DSP multiplier has adopted this method. Such a multiplier that supports both one long data multiplication operation and multiple short data multiplication operations is called a hybrid multiplier. Considering the characteristics of operand representation and design complexity in computers, hybrid multipliers generally only support two short data multiplication operations at the same time. A very straightforward way to design this hybrid multiplier is to set multiple multipliers. The disadvantages The hardware overhead is high; another method is to use pipelining technology, such as Intel® XScale ^TM , which has the disadvantage of increasing CPI, that is, the number of beats executed by a single instruction. Therefore, there is an urgent need for a new and efficient hybrid multiplier design method for high-performance, low-power microprocessor design.

Summary of the invention: The technical problem to be solved by the present invention is to provide a new hybrid multiplier design method, so that the multiplier can work in both normal mode and SIMD mode with only a small increase in hardware overhead. The technical solution is to design a new hybrid multiplier structure, the current working mode of the multiplier is indicated by the control signal, and the product corresponding to the normal mode and the SIMD mode can be obtained only by accumulating and summing the partial products. Assuming that operand 1 and operand 2 are multiplicand and multiplier respectively, and their word length is 2n bits, the mixed multiplier designed by the present invention can complete a 2n * 2n multiplication operation in normal mode; when working in SIMD In mode, it regards each 2n-bit operand as two n-bit short operands, and at this time, two n×n multiplication operations can be completed simultaneously.

The specific technical solution of the present invention is: the hybrid multiplier is composed of an operand expansion unit, a decoder, a partial product generator 1, a partial product generator 2, a correction value generation unit, a partial product compression unit and an adder. The decoder judges the working mode and the type of the operand according to the input control signal, and controls the operation of the operand expansion unit and the correction value generation unit. The operand expansion unit expands the operand under the control of the decoder, and the expanded multiplicand 1 and multiplier 1 are sent to the partial product generator 1, and the multiplicand 2 and multiplier 2 are sent to the partial product to generate Device 2. Each of the two partial product generators generates (n/2+1) partial products, which are sent to the partial product compression unit. The correction value generating unit generates the correction value for the high bit product in SIMD mode under the control of the decoder. The partial product compression section compresses (n+2) partial products and the correction value input from the correction value generation section into two 4n-bit numbers. The adder adds two 4n-bit numbers input from the partial product compression part to obtain a 4n-bit product.

The operand expansion part of the hybrid multiplier of the present invention expands the operand 1 and the operand 2, respectively generates two multiplicands and two multipliers and sends them to two partial product generators. The length of multiplicand 1 and multiplicand 2 is 2n+2 bits. In normal mode, the lower 2n bits of multiplicand 1 and multiplicand 2 are equal to operand 1, and the upper two bits are expanded to operand 1 The sign bit; in SIMD mode, the lower n bits of the multiplicand 1 are equal to the lower n bits of the operand 1, and the nth to 2n+1th bits of the multiplicand 1 are all extended to the lower n bits of the operand 1 Sign bit; the low n position of the multiplicand 2 is 0, the nth to 2n-1 bits are equal to the high n bits of the operand 1, and the highest two bits, namely the 2n and 2n+1 bits, are extended to the high n of the operand 1 The sign bit of the bit; the length of the multiplier 1 and the multiplier 2 are both n+3 bits, the multiplier 1 mainly comes from the lower n bits of the operand 2, and the multiplier 2 mainly comes from the upper n bits of the operand 2, the operation The number extension part also needs to extend 1 prefix and 2 sign bits respectively in front of and behind the multiplier 1 and the multiplier 2, the prefix of the multiplier 1 is 0, the sign bit of the multiplier 2 is the same as the upper n bits of the operand 2 The sign bit is the same, the sign bit of multiplier 1 and the prefix of multiplier 2 are configured differently in different working modes. .

The present invention also uses two-bit Booth multiplication to generate partial products. The generation of the partial product of the hybrid multiplier of the present invention is divided into two parts, which are respectively completed by a partial product generator 1 and a partial product generator 2, which are respectively equivalent to a partial product generator of a 2n×n multiplier, and generate low and high bits respectively. (n/2+1) partial products. In SIMD mode, when the sign bit of the low-order product is 1, it will affect the high-order product. The present invention designs a correction value generating component to generate a high-order product correction value to correct the high 2n bits of the product, so that the sign bit of the low-order product is 0. The method of using two-bit Booth multiplication to generate partial products is:

A partial product is obtained by shifting and inverting the multiplicand under the control of adjacent 3-bit binary numbers in the multiplier. When the multiplicand is determined, different combinations of adjacent 3-bit binary numbers in the multiplier will produce different partial products. Suppose b is the multiplier; b _k is the kth bit of the multiplier. In an ordinary two-bit Booth multiplier, a 2n×2n multiplication needs to generate n+1 partial products. The first partial product is generated by [b ₁ , b ₀ , 0], and the kth (1<k<n+1) partial product is generated by [b _2k-1 , b _2(k-1) , b _{2k- 3} ] control generation, the n+1th partial product is generated by [s, s, b _2n-1 ] control, where b _2n-1 is the highest bit of the multiplier, s is the sign bit, when the multiplier is When the multiplier is a signed number, s=b _2n-1 , and when the multiplier is an unsigned number, s=0. Assuming that the weight q of the partial product is the number of digits that the partial product needs to be shifted to the right (to the higher order) during accumulation, then the weight q _k of the kth partial product = 2(k-1).

The partial product generation unit of the present invention is composed of a partial product generator 1 and a partial product generator 2 . The input of the partial product generator 1 is the multiplicand 1 and the multiplier 1, and the input of the partial product generator 2 is the multiplicand 2 and the multiplier 2. Partial product generator 1 generates low-order (n/2+1) partial products, and partial product generator 2 generates high-order (n/2+1) partial products. Partial product generator 2 determines the value of the first three sign bits of its first partial product according to the mode of operation.

When the hybrid multiplier works in the common mode, the 1st to the n/2th partial product of the partial product generator 1 and the generation method and weight of the 1st to the n/2th partial product of the common multiplier are respectively the same; The (n/2+1)th partial product of product generator 1 is 0. The 1st to (n/2+1) partial products of the partial product generator 2 are the same as the generation methods and weights of the (n/2+1) to (n+1) partial products of the common multiplier . Therefore, in the normal mode, the partial products of the hybrid multiplier and the common multiplier are exactly the same, and the (n+2) parts of the hybrid multiplier are accumulated and added to obtain a product of 2n×2n multiplication. At this time, both the sign bit of the multiplier 1 and the prefix of the multiplier 2 are set to b _n-1 .

When the hybrid multiplier works in SIMD mode, the upper n bits of the multiplicand 1 of the partial product generator 1 are extended to the sign of the lower n bits of the operand 1, and the two sign bits of the multiplier 1 are extended to the lower n bits of the operand 2. The sign bit of the bit; the control code to generate the 1st to n/2th partial product is the same as in the normal mode; the weight of the 1st to n/2th partial product is the same as in the normal mode; the (n/2+1 ) partial products are generated under the control of [s, s, b _n-1 ], where b _n-1 is the highest bit of the low n-bit multiplier, s is the sign bit, and when the low-bit multiplier is a signed number, s= b _n-1 , when the low-order multiplier is an unsigned number, s=0; the weight of the (n/2+1)th partial product is n. In SIMD mode, the lower n bits of the multiplicand 2 of the partial product generator 2 are set to 0, the upper n bits remain unchanged, and the prefix of the multiplier 2 is 0; the first part of the partial product generator 2 is generated The control code of the product changes from [b _n+1 , b _n , b _n-1 ] to [b _n+1 , b _n , 0]; the rest of the partial product generator 2 is the same as in the normal mode; the partial product The weights of all partial products of Generator 2 remain the same. Actually, in SIMD mode, each partial product generator is equivalent to a partial product generator of a 2n×n multiplier. The effective partial product of the multiplication of the low n-bit operands is located in the low order part of the partial product of the partial product generator 1; the effective partial product of the multiplication of the high n-bit operands is located in the high order part of the partial product of the partial product generator 2.

Since the lower n bits of the partial product of the partial product generator 2 are 0, even the first partial product with the smallest weight will be moved to the right by n bits when accumulating, so the partial product of the partial product generator 2 will not The result of 2n bits has an impact, and the lower 2n bits of the accumulated result are the product of the lower n×n multiplication. Although the partial product of the high-order multiplication will not affect the low-order product, the sign bit of the partial product of the low-order multiplication will generate a carry to the high-order product during accumulation. Therefore, in order to obtain the correct result, a correction value must be added to the result of the upper 2n bits to eliminate the influence of the sign bit of the low-order product on the high-order product. The sign bits of the low-order product are either all 0s or all 1s. If the sign bit of the low-order product can be extended to the highest bit of the high-order product, when the sign bit of the low-order product is 0, the low-order product will not affect the high-order product, and a 0 is added to the lowest bit of the high-order product; When the sign bit of the low-order product is 1, as long as a 1 is added to the lowest bit of the high-order product, the sign of the low-order product at the high-order product can be changed to 0, and the high-order product will not be affected. In order to extend the sign bit of the low-order multiplication to the highest bit of the high-order product, the present invention adds (2 ^n-1 -1) to the highest (n-1) bit of the high-order product. Therefore, the correction value in the SIMD mode of the present invention consists of two parts, 0 or 1 added to the lowest bit of the high-order product and (2 ^n-1 -1) added to the high (n-1) bit, this correction value Generated by the correction value generation unit under the control of the decoder.

The partial product compression part compresses (n+2) partial products generated by two partial product generators and correction values of high-order results (in normal mode, this correction value is all 0) into two 4n-bit numbers. These two numbers are added by the propagation carry adder, and finally a 4n-bit product is obtained. In normal mode, it is the product of two 2n-bit operands; in SIMD mode, the lower 2n bits are the product of the lower n-bit multiplication, and the upper 2n bits are the product of the upper n-bit multiplication.

Adopt the present invention to produce following technical effect:

1. The present invention makes full use of the hardware resources in the multiplier, with less hardware overhead, the partial product generating part is divided into two partial product generators, a correction value generating part is designed, and the corresponding partial product compression part is added. A circuit that doubles the ability to handle multiplication operations with short operands.

2. There is no feedback between the parts of the multiplier designed by the present invention, and it can be easily divided into several flow stations to obtain higher performance.

Description of drawings:

Fig. 1 is the logic structure diagram of common multiplier;

Fig. 2 is the dot product diagram of the partial product of common 16-bit multipliers;

Fig. 3 is the dot product diagram of the partial product of the 16 mixed multipliers realized by the present invention;

Fig. 4 is a schematic diagram of the principle of correction value generation;

Fig. 5 is the logical structural diagram of the mixed multiplier that adopts the present invention to design;

Detailed ways:

Figure 1 is a logic diagram of an ordinary multiplier. The ordinary multiplier is composed of an operand expansion unit, a decoder, a partial product generation unit, a partial product compression unit and an adder (CPL). The operand extension unit carries out sign extension to the operand 1 and the operand 2 under the control of the decoder to become the multiplicand and the multiplier input to the partial product generation unit, and the partial product generation unit generates (n+1) partial products , the partial product compression unit compresses (n+1) partial products into two 4n-bit numbers, and the last adder that propagates the carry sums the two numbers to obtain a 4n-bit product.

Figure 2 is a dot product diagram of the partial product of an ordinary 16-bit multiplier considering the weight of the partial product. The highest bit of the partial product is on the right and the lowest bit is on the left. E in the figure is the symbol of the partial product, and S indicates whether the partial product has been negated and complemented. When the partial product needs to be negated and complemented, it is not immediately converted to the complement of its complement, but through its It is represented by the redundant form of adding 1 to the lowest bit of the inverse code. Fig. 3 adopts the dot product diagram of the partial product of 16 (2n) mixed multipliers designed by the present invention, wherein 1-5 partial products are produced by partial product generator 1, and n/2+1=5 partial products is 0. The 6th to 10th partial products are generated by the partial product generator 2 . The sixth partial product is equivalent to the fifth partial product in Figure 3 in normal mode, and its highest three bits E ₁ E ₂ E ₃ =E10; in SIMD mode, the sixth partial product is the high order part The first partial product of multiplication, its highest three bits E ₁ E ₂ E ₃ = E EE, E represents the negation of E. This is because when 2-bit Booth encoding is used, the sign extension methods of the first partial product and the remaining partial products are different.

In FIG. 4, the principle of correction value generation in the present invention is illustrated by taking 16-bit multiplication as an example. In the figure, a 16-bit multiplier is used to realize the multiplication of the low-order part in Figure 3. The method is to extend the sign bit of the multiplicand and the multiplier of the low-order multiplication by 8 bits, and the part shown in Figure 4(a) can be obtained product. After adding the partial products in Figure 4(a), the result in Figure 4(b) can be obtained, where S=0 or 1. Comparing the partial product in Figure 4(a) with the partial product of the low-order multiplication in the I region in Figure 3, it can be found that Figure 4(a) only adds 32'hfe00_0000, and "fe" is in Figure 4(a) The hexadecimal representation of the seven 1s in Region II on the right. When the sign bit of the low part product in Fig. 3 was 0, the present invention added 32' hfe00_0000 to the part product of region I in Fig. 3; The partial product of 32'hfe01_0000 can make the final result of the partial product in region I in Figure 3 become the result in Figure 4(c), that is, the sign bit of the low-order product will not affect the high-order product. The added value 32'hfe00_0000 or 32'hfe01_0000 is the correction value.

Fig. 5 is the structural diagram of the hybrid multiplier that adopts the design of the present invention, and it is by operand extension unit, decoder, partial product generator 1, partial product generator 2, correction value generation unit, partial product compression unit and adder composition. Compared with the ordinary multiplier, in addition to the general sign extension, the operand extension part of the hybrid multiplier should also extend the nth to (2n-1) bits of the multiplicand 1 into a sign in SIMD mode The lower n bits of the multiplicand 2 should be set to 0; the multiplier 1 and the multiplier 2 are also generated by the operand expansion unit. The partial products of the hybrid multiplier are generated by two partial product generators, each of which generates (n/2+1) partial products, and the partial product generator 2 needs to determine its first partial product up to three according to the working mode. bit value. The correction value generating unit generates a correction value of the high-order result according to the control signal and the sign bits of the multiplicand 1 and the multiplier 1. The partial product compression unit compresses (n+2) partial products generated by the two partial product generators and the correction values of high-order results into two 4n-bit numbers. The final adder that propagates the carry sums the two numbers to get a 4n-bit product. In normal mode, it is the product of two 2n-bit operands; in SIMD mode, the lower 2n bits are n-bit multiplication. The product, the upper 2n bits are the product of the multiplication of the upper n bits.

Claims (4)

1. method for designing of supporting the mixed multiplier of single instrction multioperand, comprise the operand widening parts in its mixed multiplier structure, code translator, partial-product generator, partial product compression member and totalizer, adopt two Booth multiplication to produce partial product, it is characterized in that also designing in the mixed multiplier structure modified value production part is arranged, the partial product production part is designed to two parts, by partial-product generator 1, partial-product generator 2 is formed, they are equivalent to the partial-product generator of a 2n * n multiplier respectively, produce low level and n/2+1 high-order partial product respectively, by a current mode of operation of control signal indication multiplier, code translator is according to the type of control signal judgment task pattern and operand, widening parts and the work of modified value production part are counted in control operation, the operand widening parts is under the control of code translator, operand is expanded, multiplicand 1 and multiplier 1 after the expansion are delivered to partial-product generator 1, multiplicand 2 and multiplier 2 are delivered to partial-product generator 2, partial-product generator 1 and partial-product generator 2 respectively produce n/2+1 partial product, deliver to the partial product compression member, when the modified value production part produces the SIMD pattern under the control of code translator to the modified value of high-order product, high 2n position to product is revised, and makes that the sign bit of low level product is 0; The partial product compression member is compressed into the high-order result's of n+2 partial-product sum of two partial-product generators generations modified value the number of two 4n positions, by propagating the add with carry musical instruments used in a Buddhist or Taoist mass this two numbers addition, finally obtain the product of a 4n position, under general mode, it is exactly the product of two 2n positional operands; Under the SIMD pattern, low 2n position is the product of low n position multiplication, and high 2n position is the product of high n position multiplication.

2. a kind of method for designing of supporting the mixed multiplier of single instrction multioperand as claimed in claim 1, it is characterized in that described operand widening parts expands operand 1 and operand 2, produce two multiplicands respectively and two multipliers are delivered to two partial-product generators, the length of multiplicand 1 and multiplicand 2 is the 2n+2 position, under general mode, the low 2n position of multiplicand 1 and multiplicand 2 equals operand 1, simultaneously high two sign bits that are extended to operand 1; Under the SIMD pattern, the low n position of multiplicand 1 equals the low n position of operand 1, and n to the 2n+1 position of multiplicand 1 all is extended to the sign bit of the low n position of operand 1; The low n position of multiplicand 2 is the high n position that 0, the n to the 2n-1 position equals operand 1, and the highest two is the sign bit that 2n and 2n+1 position expand to the high n position of operand 1; The length of multiplier 1 and multiplier 2 all is the n+3 position, multiplier 1 mainly comes from the low n position of operand 2, multiplier 2 mainly comes from the high n position of operand 2, the operand widening parts also will respectively be expanded 1 prefix and 2 bit sign positions in the front and back of multiplier 1 and multiplier 2, the prefix of multiplier 1 is 0, the sign bit of multiplier 2 is consistent with the sign bit of operand 2 high n positions, and the prefix of the sign bit of multiplier 1 and multiplier 2 is different configurations under different mode of operations.

3. a kind of method for designing of supporting the mixed multiplier of single instrction multioperand as claimed in claim 1, when it is characterized in that the present invention adopts two Booth multiplication to produce partial product, the input of partial-product generator 1 is multiplicand 1 and multiplier 1, the input of partial-product generator 2 is multiplicand 2 and multiplier 2, partial-product generator 1 produces n/2+1 partial product of low level, partial-product generator 2 produces n/2+1 high-order partial product, and partial-product generator 2 is determined the value of its Senior Three sign bit of first partial product according to mode of operation:

3.1 when mixed multiplier is operated in general mode, the 1st to n/2 partial product of partial-product generator 1 and general multipliers the 1st identical respectively to the production method and the power of n/2 partial product; N/2+1 partial product of partial-product generator 1 is 0, and the 1st to n/2+1 partial product of partial-product generator 2 is identical respectively with the production method and the power of n/2+1 to a n+1 partial product of general multipliers; Therefore when general mode, the partial product of mixed multiplier and general multipliers is just the same, and n+2 partial product of mixed multiplier added up promptly obtains the product of a 2n * 2n multiplication, and at this moment, the prefix of the sign bit of multiplier 1 and multiplier 2 all is changed to b _N-1

3.2 when mixed multiplier was operated in the SIMD pattern, the high n position of the multiplicand 1 of partial-product generator 1 expanded to the symbol of operand 1 low n position, two sign bits of multiplier 1 expand to the sign bit of operand 2 low n positions; Produce the 1st identical during with general mode to the control code of n/2 partial product; The 1st is identical during with general mode to the power of n/2 partial product; N/2+1 partial product is by [s, s, b _N-1] control generation, wherein b _N-1Be the most significant digit of low n position multiplier, s is a sign bit, when the low level multiplier is signed number, and s=b _N-1, when the low level multiplier is unsigned number, s=0; The power of n/2+1 partial product is n; Under the SIMD pattern, the low n position of the multiplicand 2 of partial-product generator 2 is changed to 0, and high n position remains unchanged, and the prefix of multiplier 2 is 0; The control code of the 1st partial product of the generation of partial-product generator 2 is by [b _N+1, b _n, b _N-1] become [b _N+1, b _n, 0]; The remainder of partial-product generator 2 is identical when amassing with general mode; The power of partial-product generator 2 all partial products remains unchanged; Under the SIMD pattern, each partial-product generator all is equivalent to the partial-product generator of the multiplier of a 2n * n, the long-pending low portion that is positioned at the partial product of partial-product generator 1 of the live part of low n positional operand multiplication, the long-pending high-order portion that is positioned at the partial product of partial-product generator 2 of the live part of high n positional operand multiplication.

4. a kind of method for designing of supporting the mixed multiplier of single instrction multioperand as claimed in claim 1, it is characterized in that method that the present invention revises the result of high 2n position is that result to high 2n position adds a modified value when the SIMD pattern, concrete grammar is to make the sign bit of low level product expand to the most significant digit of high-order product, when the sign bit of low level product is 0, the low level product can not exert an influence to high-order product, and this moment, the lowest order at high-order product added one 0; When the sign bit of low level product is 1, add one 1 at the lowest order of high-order product, just can make the symbol at high-order product place of low level product become 0; For the sign bit that makes the low level multiplication expands to the most significant digit of high-order product, the present invention adds 2 in the highest n-1 position of high-order product ^N-1-1, therefore, the modified value under the SIMD pattern of the present invention is made up of two parts, be added in high-order product lowest order 0 or 1 and be added in 2 on the high n-1 position ^N-1-1, this modified value adds 2 by the modified value production part is created in high-order product under the control of code translator the highest n-1 position ^N-1-1, the modified value under the SIMD pattern promptly of the present invention is made up of two parts, be added in high-order product lowest order 0 or 1 and be added in 2 on the high n-1 position ^N-1-1, this modified value is produced under the control of code translator by the modified value production part.

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