CN110399117A - A kind of mixing multiplication addition process method and device - Google Patents

A kind of mixing multiplication addition process method and device Download PDF

Info

Publication number
CN110399117A
CN110399117A CN201910702995.9A CN201910702995A CN110399117A CN 110399117 A CN110399117 A CN 110399117A CN 201910702995 A CN201910702995 A CN 201910702995A CN 110399117 A CN110399117 A CN 110399117A
Authority
CN
China
Prior art keywords
operand
intermediate operands
addition result
digit
operands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910702995.9A
Other languages
Chinese (zh)
Other versions
CN110399117B (en
Inventor
历广绪
冯闯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Suiyuan Intelligent Technology Co Ltd
Original Assignee
Shanghai Suiyuan Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Suiyuan Intelligent Technology Co Ltd filed Critical Shanghai Suiyuan Intelligent Technology Co Ltd
Priority to CN201910702995.9A priority Critical patent/CN110399117B/en
Publication of CN110399117A publication Critical patent/CN110399117A/en
Application granted granted Critical
Publication of CN110399117B publication Critical patent/CN110399117B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/501Half or full adders, i.e. basic adder cells for one denomination
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3059Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

The present invention provides a kind of mixing multiplication addition process method and device, the first order is successively carried out to first operand and second operand to handle to third level processing, the front two of the 5th intermediate operands and the 6th intermediate operands that are handled in fourth stage processing based on the third level obtains compression number, by compression number splicing before the 6th intermediate operands, the 7th intermediate operands are obtained;Then the sign bit of third operand is extended in level V processing, obtains the 4th operand, the 4th operand and the 7th intermediate operands are added, and Shape correction is carried out to addition result.Wherein the digit of the 4th operand and the 7th intermediate operands is identical, and the 7th intermediate operands are the compression numbers for splicing a units reduction on the basis of six intermediate operands, therefore the digit of the 4th operand and the 7th intermediate operands is less than twice of digit of first operand, the digit of two addition numbers in level V processing is reduced, to reduce resource and the time of adder occupancy.

Description

A kind of mixing multiplication addition process method and device
Technical field
The invention belongs to data computing technique field more particularly to a kind of mixing multiplication addition process method and devices.
Background technique
In the operand to integer type, (digit of operand is denoted as N to processor, and N is 8,16,32,64 at present Position and 128 etc.) carry out mixing multiplication add operation when using multilevel flow water transport calculate execute, this multilevel flow water transport calculate original Reason is: first operand and second operand are subjected to multiplication operation and obtain intermediate operands, by third operand be extended to Intermediate operands have identical digit extended operation number, wherein first operand, second operand and third operand position Number is N, and the digit of intermediate operands is 2N, and extended operation number and intermediate operands are then carried out sum operation, obtain to Shape data treats shape data and carries out Overflow handling according to the top N to shape data, obtains mixing multiplication add operation Result.Specific multilevel flow water transport calculation is as shown in Figure 1, process is as follows:
The first order: the first operand (SRC0 as shown in figure 1) that digit is N is split by high operation by decoder Number (A as shown in figure 1) and low level operand (B as shown in figure 1) tear the second operand (SRC1 as shown in figure 1) that digit is N open It is divided into high operation number (C as shown in figure 1) and low level operand (D as shown in figure 1), digit and the low level operation of high operation number Several digits is respectively the half of respective operations number;
The second level: the intermediate operands of four N bit (i.e. digit is N), four multiplication are obtained by four multipliers The multiplication mode of device is respectively: A*C, A*D, B*C and B*D;
The third level: phase add operation is carried out by intermediate operands of two adders to four N bit, obtains two centres As a result, respectively H and L, carrying out phase add operation to the intermediate operands of four N bit is: by a high position and B*C of A*C, A*D A high position is added, and the low level of B*D, A*D are added with the low level of B*C;
The fourth stage: two intermediate results H and L are fused into the intermediate operands of a 2N bit, and third operand is expanded Transform into 2N bit;
Level V: the intermediate operands of 2N bit are added with the third operand after extension, and to addition result It carrying out Shape correction (also known as clamp processing), so-called Shape correction refers to when the integer as addition result overflows, It is shaped into the positive number maximum value or negative maximum value of the digit of the addition result.
It is can be found that from process shown in above-mentioned Fig. 1: since third operand is extended to 2N bit by the fourth stage, so that the 4th Grade needs at least to occupy the resource of 2N bit when transmitting operand to level V, and needs adding using high-bit width in level V Musical instruments used in a Buddhist or Taoist mass carries out the add operation of 2N bit, and the adder of high-bit width is made to occupy ALU (the Arithmetic and Logic of processor Unit, arithmetic logic unit) resource and the time.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of mixing multiplication addition process method and device, for reducing The occupancy of resource and processing time.
The present invention provides a kind of mixing multiplication addition process method, and the method is used for first operand, the second operation Several and third operand carries out Pyatyi processing, the position of the first operand, the second operand and the third operand Counting the identical and described digit is even number, which comprises
The first operand is split into the first high operation number and the first low level operand by first order processing, by institute It states second operand and splits into the second high operation number and the second low level operand;
The second level processing, by the first high operation number successively with the second high operation number and second low level Operand is multiplied, and obtains the first intermediate operands and the second intermediate operands;By the first low level operand successively with it is described Second high operation number is multiplied with the second low level operand, obtains third intermediate operands and the 4th intermediate operands;
Third level processing, by first intermediate operands, the high-order portion of second intermediate operands and described the The high-order portion of three intermediate operands is added, and obtains the 5th intermediate operands;It will be in the 4th intermediate operands, described second Between the low portion of operand be added with the low portion of the third intermediate operands, obtain the 6th intermediate operands;
Fourth stage processing, the front two based on the 5th intermediate operands and the 6th intermediate operands, are pressed The digit of contracting number, the compression number is less than the digit of the first operand;By compression number splicing among the described 6th Before operand, the 7th intermediate operands are obtained;
Level V processing is extended the sign bit of the third operand, obtains the 4th operand, the 4th behaviour It counts identical with the digit of the 7th intermediate operands, the 4th operand is added with the 7th intermediate operands, And Shape correction is carried out to addition result.
Preferably, the front two based on the 5th intermediate operands and the 6th intermediate operands, is pressed Contracting number includes:
The front two of 6th intermediate operands and the 5th intermediate operands are subjected to add operation, obtained wait press Contracting operand;
If the operand to be compressed is signed number, to the first default position of the operand to be compressed to second pre- If position carries out obtaining the first operating result with operation, and the described first default position to the described second default position is carried out or operated To the second operating result, the first default position is last into second of the operand to be compressed, institute State one into the second last position of second that the second default position is the operand to be compressed, and the second default position position Before the described first default position;
The operand to be compressed is intercepted based on first operating result or second operating result, is obtained The compression number;
If the operand to be compressed is unsigned number, position is preset to the 4th pre- to the third of the operand to be compressed If position carries out or operation obtains third operating result, the third presets last position that position is the operand to be compressed to the One in two, the 4th default position is first of the operand to be compressed one into the second last position, and The 4th default position is located at before the default position of the third, and the 4th default position and the third preset the difference of position less than institute State the digit of first operand and 1 difference;
It is intercepted based on operand to be compressed described in the third operand pair, obtains the compression number.
Preferably, the sign bit to the third operand is extended, if obtaining the 4th operand includes: institute Stating third operand is signed number, increases the first of the third operand of presetting digit capacity before the third operand The value of position;
If the third operand is unsigned number, increase the presetting digit capacity before the third operand Zero;
The presetting digit capacity is identical as the compression digit of number.
Preferably, described to include: to addition result progress Shape correction
Obtain the identifier that Shape correction is carried out to the addition result;
Shape correction is carried out to the addition result based on the identifier.
Preferably, the identifier for carrying out Shape correction to the addition result that obtains includes:
If the addition result is unsigned number, obtained being added knot according to the first presetting digit capacity before the addition result The first identifier of fruit accords with, and obtains the second mark of addition result according to the corresponding action type of the addition result and the compression number Know symbol;
If the addition result is signed number, obtained being added knot according to the second presetting digit capacity before the addition result The third identifier of fruit obtains the 4th mark of addition result according to the corresponding action type of the addition result and the compression number Know symbol, second presetting digit capacity is greater than first presetting digit capacity.
Preferably, described to include: to addition result progress Shape correction based on the identifier
If the addition result be unsigned number and the addition result first identifier symbol and the addition result Second identifier symbol is effective, and the addition result is shaped as full 0;
If addition result accords with the effective but described addition result for the first identifier of unsigned number and the addition result Second identifier symbol is invalid, and the addition result is shaped as full F;
If addition result be unsigned number and the addition result first identifier symbol and the addition result second Identifier is invalid, forbids to the addition result shaping;
If the addition result be signed number and the addition result third identifier and the addition result 4th identifier is effective, the corresponding negative maximum value of the digit that the addition result is shaped as the addition result;
If addition result is that the third identifier of signed number and the addition result is effective but the addition result 4th identifier is invalid, the corresponding positive number maximum value of the digit that the addition result is shaped as the addition result;
If addition result be signed number and the addition result third identifier and the addition result the 4th Identifier is invalid, forbids to the addition result shaping.
The present invention also provides a kind of mixing multiplication addition process device, described device is used for first operand, the second behaviour It counts and third operand carries out Pyatyi processing, the first operand, the second operand and the third operand Digit is identical and the digit is even number, and described device includes:
First order processing module, for the first operand to be split into the first high operation number and the operation of the first low level Number, splits into the second high operation number and the second low level operand for the second operand;
Second level processing module, for by the first high operation number successively with the second high operation number and described Second low level operand is multiplied, and obtains the first intermediate operands and the second intermediate operands;By the first low level operand according to It is secondary to be multiplied with the second high operation number and the second low level operand, obtain behaviour among third intermediate operands and the 4th It counts;
Third level processing module, for by the high-order portion of first intermediate operands, second intermediate operands It is added with the high-order portion of the third intermediate operands, obtains the 5th intermediate operands;By the 4th intermediate operands, institute The low portion for stating the second intermediate operands is added with the low portion of the third intermediate operands, obtains the 6th intermediary operation Number;
Fourth stage processing module, for based on before the 5th intermediate operands and the 6th intermediate operands two Position, obtains compression number, and the digit of the compression number is less than the digit of the first operand;The compression number is spliced described Before 6th intermediate operands, the 7th intermediate operands are obtained;
Level V processing module is extended for the sign bit to the third operand, obtains the 4th operand, institute It is identical with the digit of the 7th intermediate operands to state the 4th operand, by the 4th operand and the 7th intermediary operation Number is added, and carries out Shape correction to addition result.
The present invention also provides a kind of processor, the processor includes:
Decoder, for the first operand to be split into the first high operation number and the first low level operand, by institute It states second operand and splits into the second high operation number and the second low level operand, the first operand, second operation The number digit identical and described with the digit of third operand is even number;
Multiplier, for by the first high operation number successively with the second high operation number and second low level Operand is multiplied, and obtains the first intermediate operands and the second intermediate operands;By the first low level operand successively with it is described Second high operation number is multiplied with the second low level operand, obtains third intermediate operands and the 4th intermediate operands;
First adder, for by first intermediate operands, the high-order portion of second intermediate operands and institute The high-order portion for stating third intermediate operands is added, and obtains the 5th intermediate operands;By the 4th intermediate operands, described The low portion of two intermediate operands is added with the low portion of the third intermediate operands, obtains the 6th intermediate operands;
Compression module is obtained for the front two based on the 5th intermediate operands and the 6th intermediate operands Number is compressed, the digit of the compression number is less than the digit of the first operand;
Splicing module, for compression number splicing before the 6th intermediate operands, to be obtained behaviour among the 7th It counts;
Expansion module is extended for the sign bit to the third operand, obtains the 4th operand, and the described 4th Operand is identical with the digit of the 7th intermediate operands;
Second adder obtains addition result for the 4th operand to be added with the 7th intermediate operands;
Shape correction module, for carrying out Shape correction to addition result.
Preferably, the compression module includes:
Third adder, for being added the front two of the 6th intermediate operands and the 5th intermediate operands Method operation, obtains operand to be compressed;
First logical unit, if being signed number for the operand to be compressed, to the operation to be compressed The default position of several first to the second default position carries out obtaining the first operating result with operation, and to the described first default position to described Second default position carries out or operation obtains the second operating result, and the first default position is last of the operand to be compressed One into second of position, the second default position are one of the second of the operand to be compressed into the second last position Position, and the second default position is located at before the described first default position;
First compression unit, for being based on first operating result or second operating result to the behaviour to be compressed It counts and is intercepted, obtain the compression number;
Second logical unit, if being unsigned number for the operand to be compressed, to the operation to be compressed Several thirds presets position and carries out or operate to the 4th default position to obtain third operating result, and it is described wait press that the third, which presets position, Last into second of contracting operand, the 4th default position be first of the operand to be compressed extremely One in the second last position, and the 4th default position is located at before the default position of the third, the 4th default position and institute The difference for stating the default position of third is less than the digit of the first operand and 1 difference;
Second compression unit obtains institute for being intercepted based on operand to be compressed described in the third operand pair State compression number.
The present invention also provides a kind of storage medium, computer program code, the calculating are stored in the storage medium Machine program code realizes above-mentioned mixing multiplication addition process method when being run by processor.
From above-mentioned technical proposal it is found that by successively carrying out first order processing, to first operand and second operand After two stage treatment and third level processing, can in fourth stage processing the 5th intermediate operands that be handled based on the third level The compression number of units reduction is obtained with the front two of the 6th intermediate operands, by compression number splicing in the 6th intermediate operands Before, the 7th intermediate operands are obtained;Then the sign bit of third operand is extended in level V processing, obtains the 4th operand and the 7th intermediate operands are added by four operands, and carry out Shape correction to addition result.Wherein the 4th behaviour It counts identical with the digit of the 7th intermediate operands, and the 7th intermediate operands are spliced on the basis of six intermediate operands The compression number that one units reduces, therefore the digit of the 4th operand and the 7th intermediate operands can be less than the two of first operand Times digit, compared with the existing technology for, the digit of two addition numbers in level V processing is reduced, in this way in level V processing The bit wide of adder can be reduced, to reduce resource and the time of adder occupancy.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention Some embodiments for those of ordinary skill in the art without creative efforts, can also basis These attached drawings obtain other attached drawings.
Fig. 1 is multistep treatment schematic diagram in the prior art;
Fig. 2 is the schematic diagram of mixing multiplication addition process method provided in an embodiment of the present invention;
Fig. 3 is a kind of compression schematic diagram provided in an embodiment of the present invention;
Fig. 4 is another compression schematic diagram provided in an embodiment of the present invention;
Fig. 5 is another compression schematic diagram provided in an embodiment of the present invention;
Fig. 6 is another compression schematic diagram provided in an embodiment of the present invention;
Fig. 7 is a kind of hardware schematic provided in an embodiment of the present invention for realizing mixing multiplication addition process method;
Fig. 8 is the structural schematic diagram of mixing multiplication addition process device provided in an embodiment of the present invention;
Fig. 9 is the structural schematic diagram of processor provided in an embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Referring to Fig. 2, it illustrates a kind of mixing multiplication addition process method provided in an embodiment of the present invention, which multiplies Method addition process method be used for first operand, second operand and third operand carry out Pyatyi processing, first operand, Identical (digit N) and digit are even number, its corresponding processing at different levels in conjunction with Fig. 2 to second operand with the digit of third operand It is as follows:
First operand (SRC0 in Fig. 2) is split into the first high operation number (N/ in Fig. 2 by first order processing 2bit A) and the first low level operand (the N/2bit B in Fig. 2), second operand (SRC1 in Fig. 2) is split into second High operation number (the N/2bit C in Fig. 2) and the second low level operand (the N/2bit D in Fig. 2).
First high operation number is successively multiplied with the second high operation number and the second low level operand by second level processing, Obtain the first intermediate operands (A*C in Fig. 2) and the second intermediate operands (A*D in Fig. 2).By the first low level operand according to It is secondary to be multiplied with the second high operation number and the second low level operand, it obtains in third intermediate operands (B*C in Fig. 2) and the 4th Between operand (B*D in Fig. 2).
Third level processing, by the high-order portion (half of the A*D in Fig. 2 of the first intermediate operands, the second intermediate operands Of high) it is added with the high-order portion (the half of high of the B*C in Fig. 2) of third intermediate operands, it obtains among the 5th Operand (H in Fig. 2).By the low portion (half of the A*D in Fig. 2 of the 4th intermediate operands, the second intermediate operands Of low) it is added with the low portion (the half of low of the B*C in Fig. 2) of third intermediate operands, obtain behaviour among the 6th Count (L in Fig. 2).
Fourth stage processing, the front two based on the 5th intermediate operands and the 6th intermediate operands obtain compression number (in Fig. 2 S), compress number digit be less than first operand digit;Will compression number splicing before the 6th intermediate operands, obtain the Seven intermediate operands (Hx).
Level V processing is extended the sign bit of third operand (E in Fig. 2), obtains the 4th operand (Fig. 2 In Ex), the digit of the 4th operand and the 7th intermediate operands is identical, by the 4th operand and the 7th intermediate operands phase Add, and Shape correction is carried out to addition result.
Wherein in fourth stage processing, the process for obtaining compression number includes but is not limited to following steps:
1) front two of the 6th intermediate operands and the 5th intermediate operands are subjected to phase add operation, obtain operation to be compressed Number (M in Fig. 2), wherein the front two of the 6th intermediate operands is the carry of the 6th intermediate operands as a result, such as the L in Fig. 2 [N+1,N])。
If 2) operand to be compressed is signed number, treat squeeze operation number the first default position (be denoted as ls, indicate from Start to compress on the left of operand to be compressed) (it is denoted as rs, is pressed indicating on the right side of the operand to be compressed to the second default position Contracting) obtained the first operating result (being denoted as CA) with operation (' & '), and to the first default position to the second default position progress or behaviour Make (' | ') to obtain the second operating result (being denoted as CO), the first default position is last position of operand to be compressed into second One (i.e. ls belongs to [0, N-2]), the second default position is one into the second last position of second of operand to be compressed (i.e. rs belongs to [N-2,1]), and the second default position is located at before the first default position.
3) it treats squeeze operation number based on the first operating result or the second operating result and is intercepted, obtain compression number.In It is treated in the present embodiment based on the first operating result or the second operating result and is needed when squeeze operation number is intercepted depending on wait press When contracting operand is signed number depending on the primary value of operand to be compressed, process is as follows:
If the primary value that operand to be compressed is signed number and operand to be compressed be 1 (such as M [N-1]= =1 ' b1), squeeze operation number is treated based on the first operating result and is intercepted, compression number is obtained;
When being treated squeeze operation number based on the first operating result and being intercepted, first based on operand to be compressed is extremely Position (N-rs+1) of operand to be compressed, the first operating result, operand to be compressed the position (ls-1) to operation to be compressed Last several positions, composition compress the data for being used to carry out operation in number, such as carrying out operation in the compression number of composition Data are as follows:
S'={ 1 ' b1, M [N-2], M [...], M [N-rs+1], CA, M [ls-1], M [...], M [0] }, for being transported Sign bit is added before the data S' of calculation obtains compression number S.
If the primary value that operand to be compressed is signed number and operand to be compressed be 0 (M [N-1]== 1 ' b0), squeeze operation number is treated based on the second operating result and is intercepted, compression number is obtained;
When being treated squeeze operation number based on the second operating result and being intercepted, first based on operand to be compressed is extremely Position (N-rs+1) of operand to be compressed, the second operating result, operand to be compressed the position (ls-1) to operation to be compressed Last several positions, composition compress the data for being used to carry out operation in number, such as carrying out operation in the compression number of composition Data are as follows:
S'={ 1 ' b0, M [N-2], M [...], M [N-rs+1], CO, M [ls-1], M [...], M [0] }, for being transported Sign bit is added before the data S' of calculation obtains compression number S.
If 4) operand to be compressed is unsigned number, treat squeeze operation number third preset position (be denoted as ls, indicate from Start to compress on the left of operand to be compressed) (it is denoted as rs, is pressed indicating on the right side of the operand to be compressed to the 4th default position Contracting) carry out or operation (' | ') obtain third operating result (being denoted as COO), third preset position be operand to be compressed last One (i.e. ls belong to [0, N-2]) of the position into second, the 4th default position are first of operand to be compressed to last the One (i.e. rs belongs to [N-1,1]) in two, and the 4th default position is located at before the default position of third, the 4th default position and third The difference of default position is less than the digit of first operand and 1 difference (i.e. rs-ls is less than N-1).
It is intercepted based on third operand pair operand to be compressed, obtains compression number.It is being based on third operating result pair When operand to be compressed is intercepted, first based on operand to be compressed to operand to be compressed position (N-rs+1), The position (ls-1) to last position of operand to be compressed of third operating result, operand to be compressed, composition compresses to be used in number It is as follows for carrying out the data of operation in the data for carrying out operation, such as in the compression number of composition:
S'={ M [N-1], M [...], M [N-rs+1], COO, M [ls-1], M [...], M [0] }, for carrying out operation Sign bit is added before data S' obtains compression number S.
Separately below by taking Fig. 3 to Fig. 6 as an example, X=2, ls=0, rs=when operand to be compressed is signed number are given N-2;X=3, ls=1, rs=N-2;X=3, ls=0, rs=N-3;X=5, ls=2, rs=N-3 obtain being used in compression number S X=2, ls=0, rs=N-1 when the example of the data S' of progress operation and operand to be compressed are unsigned number;X=3, ls =1 or ls=2, rs=N-1;X=3, ls=0, rs=N-2 or rs=N-3;X=5, ls=0 or ls=1 or ls =2, rs=N-1 or rs=N-2 or rs=N-3 are obtained in compression number S for carrying out the example of the data S' of operation, wherein X indicates the maximum number of digits for the S' that operand to be compressed obtains after being intercepted.
With X=3, ls=1, rs=N-2 in Fig. 4, the operand to be compressed of signed number is intercepted, and with X= 3, ls=1 or ls=2, rs=N-1, it is illustrated for being intercepted to the operand to be compressed of unsigned number:
For the operand to be compressed of signed number, treat the position (N-2) of squeeze operation number to penultimate into Row obtains the first operating result CA with operation (' & '), and the position (N-2) for treating squeeze operation number carries out or grasps to penultimate Make (' | ') and obtains the second operating result CO, if first M [N-1] value of the operand to be compressed of signed number is 1 (1 ' B1), then intercepted using S'={ 1 ' b1, M [N-2], M [...], M [N-rs+1], CA, M [ls-1], M [...], M [0] }, because M [0] is taken for ls=1, the M [ls-1] to M [0] after CA;Rs=N-2, M [N-rs+1] M [3] before CA, if The digit that interception 1 ' b1 to M [3] then will lead to S' is greater than 3, so needing to choose 1 ' b1 in [3] from 1 ' b1 to M, by 1 ' b1, CA S', i.e. S'={ 1 ' b1, CA, M [0] } are formed with M [0].If first M of the operand to be compressed of same signed number [N-1] value is 0 (1 ' b0), the then S'=obtained { 1 ' b0, CO, M [0] }.
For the operand to be compressed of unsigned number, if ls=1, that is, M [1] is participated in or operation, squeeze operation number is treated The position (N-1) carries out or operates (' | ') to penultimate and obtains third operating result COO, i.e., carries out to M [N-1] to M [1] Or operation because M [N-1] to M [1] is both participated in or is operated, then based on S'=M [N-1], M [...], M [N-rs+1], COO, M [ls-1], M [...], M [0] } cannot be by M [N-1] to M [1] as the data in S' when being intercepted, and because M [0] The S'={ COO, M [0] } for being not engaged in or operating, therefore obtained based on above-mentioned formula.If ls=2, that is, M [1] is not involved in or grasps Make, participates in or that operate is M [N-1] to M [2], the then S'=obtained { COO, M [1], M [0] }.
For attached drawing 3, attached drawing 5 and attached drawing 6, to signed number and unsigned number wait press in attached drawing 3, attached drawing 5 and attached drawing 6 How contracting operand, which obtains S', is illustrated, and no longer illustrates this present embodiment.
In level V processing, in order to guarantee that the 4th operand and the fourth stage that obtain after the extension of third operand are handled The digit of the 7th intermediate operands arrived is identical, and the present embodiment is to a kind of extended mode of third operand:
If third operand is signed number, increase the of the third operand of presetting digit capacity before third operand One value, presetting digit capacity is identical as the compression digit of number, wherein if third operand is signed number, third operand Sign bit is exactly E [N-1], i.e., primary value, therefore passes through and increase the first of third operand before third operand The value mode of position realizes the extension of sign bit, it is assumed that the digit for compressing number is (X+1), and wherein X is in compression number S for carrying out The digit of the data S' of operation, 1 is the sign bit for compressing number S, then increasing (X+1) before third operand, a its is primary Value, to keep the 4th operand identical as the digit of the 7th intermediate operands that the fourth stage is handled.
If third operand is unsigned number, increases the zero of presetting digit capacity before third operand, similarly preset Digit is identical as the compression digit of number, and why increasing by zero is because unsigned number does not have sign bit, by way of increasing by zero Keep the 4th operand identical as the digit of the 7th intermediate operands that the fourth stage is handled.
In level V processing, the 4th operand and the 7th intermediate operands are added and can grasp because of first operand, second Action type corresponding with third operand of counting is different and different, it is assumed that first operand SRC0, second operand are SRC1 and third operand are E, and action type includes: E-SRC0*SRC1, SRC0*SRC1- /+E, and corresponding phase add operation is such as Under:
7th intermediate operands Hx={ S, L [N-1:0] }, S are compression number, and L [N-1:0] is the 6th intermediate operands, right Every of Hx, which carries out negating transformation, obtains Hv, and the digit of Hv is identical as the digit of Hx, every progress to the 4th operand Ex It negates transformation and obtains Ev, and the digit of Ev is identical as the digit of Ex;If action type is E-SRC0*SRC1, addition result F =Hx+Ev, if action type is SRC0*SRC1-E, addition result F=Hx+Ex, if action type is SRC0*SRC1+ E, then addition result F=Hv+Ex.
Further, after obtaining addition result, such as first identifier accords with uo=| and { F [X+N:N] } is tied according to being added Preceding X+1 of fruit obtain, and the calculating process of second identifier symbol is: second identifier symbol sgn_clp=sub0&&S [X-1:0]= ={ 0, xxx } | | sub1&&S [X-1:0]=={ 1, xxx }, xxx indicates 0 or 1, in the process for actually calculating second identifier symbol In, it is only necessary to consider that first of first and sub1&&S [X-1:0] of sub0&&S [X-1:0], sub0 indicate E-SRC0* SRC1, sub1 indicate SRC0*SRC1- /+E.
If addition result is signed number, phase is obtained according to the second presetting digit capacity before addition result (such as X+2 first) The third identifier for adding result obtains the 4th identifier of addition result according to the corresponding action type of addition result and compression number It determines, the second presetting digit capacity is greater than the first presetting digit capacity.
Such as third identifier so=F [X+N] &&!(&F[X+N-1:N-1])||!F [X+N] && | (F [X+N-1:N-1]), It is obtained according to preceding X+2 of addition result, and the calculating process of the 4th identifier is: the 4th identifier usgn_clp=sub0 | | Sub1&&S [X-1:0]=={ (X) { 1 ' b0 } }, S [X-1:0]=={ (X) { 1 ' b0 } } expression takes X zero to be compared with sub1 The operation such as relatively sentence.
And it is as follows based on the process that identifier carries out Shape correction to addition result:
If addition result is that the first identifier symbol of unsigned number and addition result and the second identifier of addition result accord with Effectively, it will add up result and be shaped as full 0.
If addition result accords with effective but addition result second identifier for the first identifier of unsigned number and addition result Symbol is invalid, will add up result and is shaped as full F.
If addition result is that the first identifier symbol of unsigned number and addition result and the second identifier of addition result accord with In vain, forbid to addition result shaping.
If addition result is signed number and the third identifier of addition result and the 4th identifier of addition result are equal Effectively, it will add up the corresponding negative maximum value of digit that result is shaped as addition result, such as the digit of addition result is 32, then Obtain 32 corresponding negative maximum values.
If addition result be the third identifier of signed number and addition result effectively but the 4th mark of addition result Symbol is invalid, will add up the corresponding positive number maximum value of digit that result is shaped as addition result.
If addition result is signed number and the third identifier of addition result and the 4th identifier of addition result are equal In vain, forbid to addition result shaping.
When the value of above-mentioned first identifier symbol and second identifier symbol is 1, first identifier symbol and second identifier symbol are indicated effectively, If the value of first identifier symbol and second identifier symbol is 0, indicate that first identifier symbol and second identifier symbol are invalid, likewise, on When the value for stating third identifier and the 4th identifier is 1, indicate that third identifier and the 4th identifier are effective, if third mark The value for knowing symbol and the 4th identifier is 0, indicates that third identifier and the 4th identifier are invalid.If obtained based on above-mentioned operation First identifier is accorded with to the 4th identifier, is accorded with first identifier to the 4th identifier and is carried out inversion operation, then first identifier accords with Value to the 4th identifier indicates effective when being 0, indicates invalid when value is 1, corresponding to be tied based on identifier to addition The process that fruit carries out Shape correction is as follows:
If addition result is that the first identifier symbol of unsigned number and addition result and the second identifier of addition result accord with Effectively, it will add up result and be shaped as full F.
If addition result accords with effective but addition result second identifier for the first identifier of unsigned number and addition result Symbol is invalid, will add up result and is shaped as full 0.
If addition result is that the first identifier symbol of unsigned number and addition result and the second identifier of addition result accord with In vain, forbid to addition result shaping.
If addition result is signed number and the third identifier of addition result and the 4th identifier of addition result are equal Effectively, it will add up the corresponding positive number maximum value of digit that result is shaped as addition result, such as the digit of addition result is 32, then Obtain 32 corresponding positive number maximum values.
If addition result be the third identifier of signed number and addition result effectively but the 4th mark of addition result Symbol is invalid, will add up the corresponding negative maximum value of digit that result is shaped as addition result.
If addition result is signed number and the third identifier of addition result and the 4th identifier of addition result are equal In vain, forbid to addition result shaping.
It based on above scheme, is given below with N=32, for X=2, the present embodiment provides methods in the fourth stage and the 5th A kind of hardware realization of grade:
When the fourth stage obtains compression number, for signed number, if the highest order M [31] of operand M to be compressed Value be 1 select CA as the position cps in figure, if the value of the highest order [31] of operand M to be compressed selects CA work for 1 For the position cps in figure, the S' in compression number is formed with highest order M [31], for unsigned number, step-by-step ' or ' COO is obtained, most Compression number S is selected further according to is_sgn mark afterwards, the 32bit for the L being calculated according to compression number S and the fourth stage carries out position spelling It connects to obtain Hx, Hx is transmitted to level V.Wherein is_sign mark is for indicating that forming the operand to be compressed of compression number is to have Symbolic number or unsigned number indicate that operand to be compressed is signed number (signed), such as if the value of is_sign is 1 The value of fruit is_sign is 0, indicates that operand to be compressed is unsigned number (unsigned).
In level V, Hx is negated to obtain Hv.3bit signed symbol Bits Expanding is carried out to E and forms Ex, while Ex is asked It is counter to obtain Ev.It then is that sub0 or sub1 selects Hx/Hv according to the obtained instruction type of instruction resolution phase, Ex/Ev is into adding Musical instruments used in a Buddhist or Taoist mass carries out operation and obtains the addition result F of 35bit, calculates separately out so and uo according to signed number and unsigned number.For Unsigned number, if it is sub1 type instruction and S==2 ' b00 and uo is effective or sub0 type instruction and uo it is effective, then It is shaped into 32 ' h0000_0000 (full 0), 32 ' hFFFF_FFFF (full F) is otherwise shaped under the conditions of uo is effective.For having Symbolic number, if it is being shaped into 32 ' under sub0 type instruction and S==2 ' b00 or S==2 ' b01 and the effective situation of so H8000_0000 (i.e. 32 corresponding negative maximum values);If it is sub1 type instruction and S==2 ' b10 or S==2 ' 32 ' h8000_0000 (i.e. 32 corresponding negative maximum values) are shaped into b11 and the effective situation of so;Otherwise other conditions and Effective clamp to the 7FFF_FFFF of so (i.e. 32 corresponding positive number maximum values).
From above-mentioned technical proposal it is found that by successively carrying out first order processing, to first operand and second operand After two stage treatment and third level processing, can in fourth stage processing the 5th intermediate operands that be handled based on the third level The compression number of units reduction is obtained with the front two of the 6th intermediate operands, by compression number splicing in the 6th intermediate operands Before, the 7th intermediate operands are obtained;Then the sign bit of third operand is extended in level V processing, obtains the 4th operand and the 7th intermediate operands are added by four operands, and carry out Shape correction to addition result.Wherein the 4th behaviour It counts identical with the digit of the 7th intermediate operands, and the 7th intermediate operands are spliced on the basis of six intermediate operands The compression number that one units reduces, therefore the digit of the 4th operand and the 7th intermediate operands can be less than the two of first operand Times digit, compared with the existing technology for, the digit of two addition numbers in level V processing is reduced, in this way in level V processing The bit wide of adder can be reduced, to reduce resource and the time of adder occupancy.
For the various method embodiments described above, for simple description, therefore, it is stated as a series of action combinations, but Be those skilled in the art should understand that, the present invention is not limited by the sequence of acts described because according to the present invention, certain A little steps can be performed in other orders or simultaneously.Secondly, those skilled in the art should also know that, it is retouched in specification The embodiment stated belongs to preferred embodiment, and related actions and modules are not necessarily necessary for the present invention.
Corresponding with above method embodiment, the embodiment of the present invention also provides a kind of mixing multiplication addition process device, should Mix multiplication addition process device be used for first operand, second operand and third operand carry out Pyatyi processing, first Operand, second operand are identical with the digit of third operand and digit is even number, and structure is as shown in figure 8, may include: At first order processing module 10, second level processing module 20, third level processing module 30, fourth stage processing module 40 and level V Manage module 50.
First order processing module 10, for first operand to be split into the first high operation number and the operation of the first low level Number, splits into the second high operation number and the second low level operand for second operand.
Second level processing module 20, for successively grasping the first high operation number with the second high operation number and the second low level It counts multiplication, obtains the first intermediate operands and the second intermediate operands;First low level operand is successively grasped with second high position It counts and is multiplied with the second low level operand, obtain third intermediate operands and the 4th intermediate operands.
Third level processing module 30, for by the first intermediate operands, the high-order portion of the second intermediate operands and third The high-order portion of intermediate operands is added, and obtains the 5th intermediate operands;By the 4th intermediate operands, the second intermediate operands Low portion is added with the low portion of third intermediate operands, obtains the 6th intermediate operands.
Fourth stage processing module 40 is obtained for the front two based on the 5th intermediate operands and the 6th intermediate operands Number is compressed, the digit for compressing number is less than the digit of first operand;By compression number splicing before the 6th intermediate operands, obtain 7th intermediate operands.
The process that wherein fourth stage processing module 40 obtains compression number includes but is not limited to following steps:
1) front two of the 6th intermediate operands and the 5th intermediate operands are subjected to phase add operation, obtain operation to be compressed Number (M in Fig. 2), wherein the front two of the 6th intermediate operands is the carry of the 6th intermediate operands as a result, such as the L in Fig. 2 [N+1,N])。
If 2) operand to be compressed is signed number, treat squeeze operation number the first default position (be denoted as ls, indicate from Start to compress on the left of operand to be compressed) (it is denoted as rs, is pressed indicating on the right side of the operand to be compressed to the second default position Contracting) obtained the first operating result (being denoted as CA) with operation (' & '), and to the first default position to the second default position progress or behaviour Make (' | ') to obtain the second operating result (being denoted as CO), the first default position is last position of operand to be compressed into second One (i.e. ls belongs to [0, N-2]), the second default position is one into the second last position of second of operand to be compressed (i.e. rs belongs to [N-2,1]), and the second default position is located at before the first default position.
3) it treats squeeze operation number based on the first operating result or the second operating result and is intercepted, obtain compression number.In It is treated in the present embodiment based on the first operating result or the second operating result and is needed when squeeze operation number is intercepted depending on wait press When contracting operand is signed number depending on the primary value of operand to be compressed, process is as follows:
If the primary value that operand to be compressed is signed number and operand to be compressed be 1 (such as M [N-1]= =1 ' b1), squeeze operation number is treated based on the first operating result and is intercepted, compression number is obtained;
When being treated squeeze operation number based on the first operating result and being intercepted, first based on operand to be compressed is extremely Position (N-rs+1) of operand to be compressed, the first operating result, operand to be compressed the position (ls-1) to operation to be compressed Last several positions, composition compress the data for being used to carry out operation in number, such as carrying out operation in the compression number of composition Data are as follows:
S'={ 1 ' b1, M [N-2], M [...], M [N-rs+1], CA, M [ls-1], M [...], M [0] }, for being transported Sign bit is added before the data S' of calculation obtains compression number S.
If the primary value that operand to be compressed is signed number and operand to be compressed be 0 (M [N-1]== 1 ' b0), squeeze operation number is treated based on the second operating result and is intercepted, compression number is obtained;
When being treated squeeze operation number based on the second operating result and being intercepted, first based on operand to be compressed is extremely Position (N-rs+1) of operand to be compressed, the second operating result, operand to be compressed the position (ls-1) to operation to be compressed Last several positions, composition compress the data for being used to carry out operation in number, such as carrying out operation in the compression number of composition Data are as follows:
S'={ 1 ' b0, M [N-2], M [...], M [N-rs+1], CO, M [ls-1], M [...], M [0] }, for being transported Sign bit is added before the data S' of calculation obtains compression number S.
If 4) operand to be compressed is unsigned number, treat squeeze operation number third preset position (be denoted as ls, indicate from Start to compress on the left of operand to be compressed) (it is denoted as rs, is pressed indicating on the right side of the operand to be compressed to the 4th default position Contracting) carry out or operation (' | ') obtain third operating result (being denoted as COO), third preset position be operand to be compressed last One (i.e. ls belong to [0, N-2]) of the position into second, the 4th default position are first of operand to be compressed to last the One (i.e. rs belongs to [N-1,1]) in two, and the 4th default position is located at before the default position of third, the 4th default position and third The difference of default position is less than the digit of first operand and 1 difference (i.e. rs-ls is less than N-1).
It is intercepted based on third operand pair operand to be compressed, obtains compression number.It is being based on third operating result pair When operand to be compressed is intercepted, first based on operand to be compressed to operand to be compressed position (N-rs+1), The position (ls-1) to last position of operand to be compressed of third operating result, operand to be compressed, composition compresses to be used in number It is as follows for carrying out the data of operation in the data for carrying out operation, such as in the compression number of composition:
S'={ M [N-1], M [...], M [N-rs+1], COO, M [ls-1], M [...], M [0] }, for carrying out operation Sign bit is added before data S' obtains compression number S.
The above method is please referred to for the detailed description that above-mentioned fourth stage processing module 40 obtains the process of compression number to implement Example, no longer illustrates this present embodiment.
Level V processing module 50 is extended for the sign bit to third operand, obtains the 4th operand, and the 4th The digit of operand and the 7th intermediate operands is identical, and the 4th operand and the 7th intermediate operands are added, and ties to being added Fruit carries out Shape correction.
In the present embodiment, a kind of mode that level V processing module 50 is extended the sign bit of third operand It is: if third operand is signed number, increases first of the third operand of presetting digit capacity before third operand Value, presetting digit capacity with compression the digit of number it is identical, wherein if third operand be signed number, third operate numerical symbol Position is exactly E [N-1], i.e., primary value, thus by before third operand increase third operand it is primary The extension of value mode realization sign bit, it is assumed that the digit for compressing number is (X+1), and wherein X is in compression number S for carrying out operation Data S' digit, 1 is the sign bit for compressing number S, then increases (X+1) a its before third operand and primary take Value, to keep the 4th operand identical as the digit of the 7th intermediate operands that the fourth stage is handled.
If third operand is unsigned number, increases the zero of presetting digit capacity before third operand, similarly preset Digit is identical as the compression digit of number, and why increasing by zero is because unsigned number does not have sign bit, by way of increasing by zero Keep the 4th operand identical as the digit of the 7th intermediate operands that the fourth stage is handled.
And level V processing module 50 can be because of the first operation to the addition of the 4th operand and the 7th intermediate operands Number, second operand action type corresponding with third operand are different and different, as phase after obtaining addition result Adding result is that signed number or unsigned number execute different Shape corrections, and detailed process please refers to above method embodiment, right This present embodiment no longer illustrates.
From above-mentioned technical proposal it is found that passing through first order processing module 10, second level processing module 20 and third level processing After module 30 successively carries out first order processing, second level processing and third level processing to first operand and second operand, Fourth stage processing module 40 can be based on the 5th intermediate operands and the 6th intermediate operands that third level processing module 30 obtains Front two obtain a units reduction compression number, will compression number splicing before the 6th intermediate operands, obtain in the 7th Between operand;Then it is extended by sign bit of the level V processing module 50 to third operand, obtains the 4th operand, 4th operand and the 7th intermediate operands are added, and Shape correction is carried out to addition result.Wherein the 4th operand and The digit of seven intermediate operands is identical, and the 7th intermediate operands are to splice a units on the basis of six intermediate operands Reduced compression number, therefore the digit of the 4th operand and the 7th intermediate operands can be less than twice of digit of first operand, For compared with the existing technology, the digit of two addition numbers in level V processing is reduced, can be dropped in level V processing in this way The bit wide of low adder, to reduce resource and the time of adder occupancy.
The embodiment of the present invention also provides a kind of processor, and structure is as shown in figure 9, may include: decoder 100, multiplication At device 200, first adder 300, compression module 400, splicing module 500, expansion module 600, second adder 700 and shaping Manage module 800.
Decoder 100, for first operand to be split into the first high operation number and the first low level operand, by second Operand splits into the second high operation number and the second low level operand, first operand, second operand and third operand Digit is identical and digit is even number.
Multiplier 200, for by the first high operation number successively with the second high operation number and the second low level operand phase Multiply, obtains the first intermediate operands and the second intermediate operands;By the first low level operand successively with the second high operation number and Second low level operand is multiplied, and obtains third intermediate operands and the 4th intermediate operands.
First adder 300, for will be among the first intermediate operands, the high-order portion of the second intermediate operands and third The high-order portion of operand is added, and obtains the 5th intermediate operands;By the low level of the 4th intermediate operands, the second intermediate operands Part is added with the low portion of third intermediate operands, obtains the 6th intermediate operands.
Compression module 400 is compressed for the front two based on the 5th intermediate operands and the 6th intermediate operands Number, the digit for compressing number are less than the digit of first operand.
Wherein, compression module 400 may include: third adder, the first logical unit, the first compression unit, Two logical unit and the second compression unit.
Third adder, for the front two of the 6th intermediate operands and the 5th intermediate operands to be carried out add operation, Obtain operand to be compressed.
First logical unit treats the first of squeeze operation number if being signed number for operand to be compressed Default position carries out obtaining the first operating result with operation to the second default position, and the first default position is carried out to the second default position or Operation obtains the second operating result, and the first default position is last into second of operand to be compressed, and second Default position is one of the second of operand to be compressed into the second last position, and the second default position be located at the first default position it Before.
First compression unit, for treating squeeze operation number based on the first operating result or the second operating result and being cut It takes, obtains compression number.
Second logical unit treats the third of squeeze operation number if being unsigned number for operand to be compressed Default position is carried out to the 4th default position or operation obtains third operating result, and third presets last that position is operand to be compressed One into second of position, the 4th default position are first of operand to be compressed one into the second last position, and the Four default positions are located at before the default position of third, and the difference of the 4th default position and the default position of third is less than the digit and 1 of first operand Difference.
Second compression unit obtains compression number for being intercepted based on third operand pair operand to be compressed.
For the first logical unit, the first compression unit, the second logical unit and the second compression unit tool Body implementation procedure please refers to the related description in above method embodiment, no longer illustrates this present embodiment.
Splicing module 500 obtains the 7th intermediate operands for that will compress number splicing before the 6th intermediate operands.
Expansion module 600 is extended for the sign bit to third operand, obtains the 4th operand, the 4th operation Number is identical with the digit of the 7th intermediate operands.A kind of extended mode is:
If third operand is signed number, increase the of the third operand of presetting digit capacity before third operand One value, presetting digit capacity is identical as the compression digit of number, wherein if third operand is signed number, third operand Sign bit is exactly E [N-1], i.e., primary value, therefore passes through and increase the first of third operand before third operand The value mode of position realizes the extension of sign bit, it is assumed that the digit for compressing number is (X+1), and wherein X is in compression number S for carrying out The digit of the data S' of operation, 1 is the sign bit for compressing number S, then increasing (X+1) before third operand, a its is primary Value, to keep the 4th operand identical as the digit of the 7th intermediate operands that the fourth stage is handled.
If third operand is unsigned number, increases the zero of presetting digit capacity before third operand, similarly preset Digit is identical as the compression digit of number, and why increasing by zero is because unsigned number does not have sign bit, by way of increasing by zero Keep the 4th operand identical as the digit of the 7th intermediate operands that the fourth stage is handled.
Second adder 700 obtains addition result for the 4th operand and the 7th intermediate operands to be added. In Pyatyi processing, the 4th operand and the 7th intermediate operands are added and can grasp because of first operand, second operand and third Corresponding action type of counting is different and different, referring specifically to the related description in above method embodiment, to this this implementation Example no longer illustrates.
Shape correction module 800, for carrying out Shape correction to addition result.As Shape correction module 800 is obtained to phase Add result to carry out the identifier of Shape correction, and Shape correction is carried out to addition result based on identifier.
Wherein identifier is needed depending on addition result depending on unsigned number or signed number, for example, if addition result is Unsigned number is accorded with according to the first identifier that the first presetting digit capacity before addition result (such as X+1 first) obtains addition result, according to The corresponding action type of addition result and compression number obtain the second identifier symbol of addition result;If addition result is to have symbol Number, obtains the third identifier of addition result according to the second presetting digit capacity before addition result (such as X+2 first), ties according to being added The 4th identifier that the corresponding action type of fruit and compression number obtain addition result determines that it is default that the second presetting digit capacity is greater than first Digit;Detailed process please refers to the related description in embodiment of the method, no longer illustrates this present embodiment.And it is based on identifier The Shape correction carried out to addition result also please refers to the related description in embodiment of the method, no longer illustrates this present embodiment.
Herein it should be noted is that: decoder 100 that above-mentioned processor includes, multiplier 200, first adder 300, compression module 400, splicing module 500, expansion module 600, second adder 700 and Shape correction module 800, and pressure Third adder that contracting module 400 includes, the first logical unit, the first compression unit, the second logical unit and Two compression units can be realized by active computer logical block etc., as shown in fig. 7, can also be realized by programming mode, To this present embodiment without limiting.
The embodiment of the present invention also provides a kind of storage medium, and computer program code, computer are stored in storage medium Above-mentioned mixing multiplication addition process method is realized when program code is run by processor.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For device class embodiment, since it is basically similar to the method embodiment, so being described relatively simple, related place ginseng See the part explanation of embodiment of the method.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged Except there is also other identical elements in the process, method, article or apparatus that includes the element.
The foregoing description of the disclosed embodiments can be realized those skilled in the art or using the present invention.To this A variety of modifications of a little embodiments will be apparent for a person skilled in the art, and the general principles defined herein can Without departing from the spirit or scope of the present invention, to realize in other embodiments.Therefore, the present invention will not be limited It is formed on the embodiments shown herein, and is to fit to consistent with the principles and novel features disclosed in this article widest Range.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered It is considered as protection scope of the present invention.

Claims (10)

1. a kind of mixing multiplication addition process method, which is characterized in that the method is used for first operand, second operand Pyatyi processing, the digit of the first operand, the second operand and the third operand are carried out with third operand The identical and described digit is even number, which comprises
The first operand is split into the first high operation number and the first low level operand by first order processing, by described the Two operands split into the second high operation number and the second low level operand;
Second level processing successively operates the first high operation number with the second high operation number and second low level Number is multiplied, and obtains the first intermediate operands and the second intermediate operands;By the first low level operand successively with described second High operation number is multiplied with the second low level operand, obtains third intermediate operands and the 4th intermediate operands;
The third level processing, by first intermediate operands, second intermediate operands high-order portion and the third in Between operand high-order portion be added, obtain the 5th intermediate operands;By behaviour among the 4th intermediate operands, described second The low portion counted is added with the low portion of the third intermediate operands, obtains the 6th intermediate operands;
Fourth stage processing, the front two based on the 5th intermediate operands and the 6th intermediate operands obtain compression number, The digit of the compression number is less than the digit of the first operand;The compression number is spliced in the 6th intermediate operands Before, the 7th intermediate operands are obtained;
Level V processing is extended the sign bit of the third operand, obtains the 4th operand, the 4th operand It is identical with the digit of the 7th intermediate operands, the 4th operand is added with the 7th intermediate operands, and right Addition result carries out Shape correction.
2. the method according to claim 1, wherein described be based on the 5th intermediate operands and the described 6th The front two of intermediate operands, obtaining compression number includes:
The front two of 6th intermediate operands and the 5th intermediate operands are subjected to add operation, obtain behaviour to be compressed It counts;
If the operand to be compressed is signed number, to the first default position to the second default position of the operand to be compressed It carries out obtaining the first operating result with operation, and the described first default position is carried out to the described second default position or operation obtains the Two operating results, the first default position are last into second of the operand to be compressed, described the Two default positions are one of the second of the operand to be compressed into the second last position, and the second default position is located at institute Before stating the first default position;
The operand to be compressed is intercepted based on first operating result or second operating result, is obtained described Compress number;
If the operand to be compressed is unsigned number, position to the 4th default position is preset to the third of the operand to be compressed It carries out or operation obtains third operating result, the third presets last position that position is the operand to be compressed to second In one, the 4th default position is first of the operand to be compressed one into the second last position, and described 4th default position is located at before the third presets position, and the 4th default position and the third preset the difference of position less than described the The digit of one operand and 1 difference;
It is intercepted based on operand to be compressed described in the third operand pair, obtains the compression number.
3. the method according to claim 1, wherein the sign bit to the third operand expands Exhibition increases pre- if it is signed number that obtain the 4th operand, which include: the third operand, before the third operand If the primary value of the third operand of digit;
If the third operand is unsigned number, increase the zero of the presetting digit capacity before the third operand;
The presetting digit capacity is identical as the compression digit of number.
4. the method according to claim 1, wherein described include: to addition result progress Shape correction
Obtain the identifier that Shape correction is carried out to the addition result;
Shape correction is carried out to the addition result based on the identifier.
5. according to the method described in claim 4, it is characterized in that, described obtain carries out Shape correction to the addition result Identifier includes:
If the addition result is unsigned number, addition result is obtained according to the first presetting digit capacity before the addition result First identifier symbol, obtains the second identifier of addition result according to the corresponding action type of the addition result and the compression number Symbol;
If the addition result is signed number, addition result is obtained according to the second presetting digit capacity before the addition result Third identifier obtains the 4th mark of addition result according to the corresponding action type of the addition result and the compression number Symbol, second presetting digit capacity are greater than first presetting digit capacity.
6. according to the method described in claim 5, it is characterized in that, described carry out the addition result based on the identifier Shape correction includes:
If the addition result be unsigned number and the addition result first identifier symbol and the addition result second Identifier is effective, and the addition result is shaped as full 0;
If addition result accords with the second of the effective but described addition result for the first identifier of unsigned number and the addition result Identifier is invalid, and the addition result is shaped as full F;
If addition result is the second identifier of the first identifier symbol and the addition result of unsigned number and the addition result It is invalid to accord with, and forbids to the addition result shaping;
If the addition result be signed number and the addition result third identifier and the addition result the 4th Identifier is effective, the corresponding negative maximum value of the digit that the addition result is shaped as the addition result;
If addition result be that the third identifier of signed number and the addition result is effective but the addition result the 4th Identifier is invalid, the corresponding positive number maximum value of the digit that the addition result is shaped as the addition result;
If addition result is the third identifier of signed number and the addition result and the 4th mark of the addition result It is invalid to accord with, and forbids to the addition result shaping.
7. a kind of mixing multiplication addition process device, which is characterized in that described device is used for first operand, second operand Pyatyi processing, the digit of the first operand, the second operand and the third operand are carried out with third operand The identical and described digit is even number, and described device includes:
First order processing module, for the first operand to be split into the first high operation number and the first low level operand, The second operand is split into the second high operation number and the second low level operand;
Second level processing module, for by the first high operation number successively with the second high operation number and described second Low level operand is multiplied, and obtains the first intermediate operands and the second intermediate operands;By the first low level operand successively with The second high operation number is multiplied with the second low level operand, obtains third intermediate operands and the 4th intermediary operation Number;
Third level processing module, for by first intermediate operands, the high-order portion of second intermediate operands and institute The high-order portion for stating third intermediate operands is added, and obtains the 5th intermediate operands;By the 4th intermediate operands, described The low portion of two intermediate operands is added with the low portion of the third intermediate operands, obtains the 6th intermediate operands;
Fourth stage processing module is obtained for the front two based on the 5th intermediate operands and the 6th intermediate operands Digit to compression number, the compression number is less than the digit of the first operand;The compression number is spliced the described 6th Before intermediate operands, the 7th intermediate operands are obtained;
Level V processing module is extended for the sign bit to the third operand, obtains the 4th operand, and described Four operands are identical with the digit of the 7th intermediate operands, by the 4th operand and the 7th intermediate operands phase Add, and Shape correction is carried out to addition result.
8. a kind of processor, which is characterized in that the processor includes:
Decoder, for the first operand to be split into the first high operation number and the first low level operand, by described Two operands split into the second high operation number and the second low level operand, the first operand, the second operand and The digit of third operand is identical and the digit is even number;
Multiplier, for successively operating the first high operation number with the second high operation number and second low level Number is multiplied, and obtains the first intermediate operands and the second intermediate operands;By the first low level operand successively with described second High operation number is multiplied with the second low level operand, obtains third intermediate operands and the 4th intermediate operands;
First adder, for by the high-order portion of first intermediate operands, second intermediate operands and described The high-order portion of three intermediate operands is added, and obtains the 5th intermediate operands;It will be in the 4th intermediate operands, described second Between the low portion of operand be added with the low portion of the third intermediate operands, obtain the 6th intermediate operands;
Compression module is compressed for the front two based on the 5th intermediate operands and the 6th intermediate operands The digit of number, the compression number is less than the digit of the first operand;
Splicing module, for compression number splicing before the 6th intermediate operands, to be obtained the 7th intermediate operands;
Expansion module is extended for the sign bit to the third operand, obtains the 4th operand, the 4th operation Number is identical with the digit of the 7th intermediate operands;
Second adder obtains addition result for the 4th operand to be added with the 7th intermediate operands;
Shape correction module, for carrying out Shape correction to addition result.
9. processor according to claim 8, which is characterized in that the compression module includes:
Third adder, for the front two of the 6th intermediate operands and the 5th intermediate operands to be carried out addition behaviour Make, obtains operand to be compressed;
First logical unit, if being signed number for the operand to be compressed, to the operand to be compressed First default position to the second default position carries out obtaining the first operating result with operation, and to the described first default position to described second Default position carries out or operation obtains the second operating result, the first default position be last position of the operand to be compressed extremely One in second, the second default position is one of the second of the operand to be compressed into the second last position, And the second default position is located at before the described first default position;
First compression unit, for being based on first operating result or second operating result to the operand to be compressed It is intercepted, obtains the compression number;
Second logical unit, if being unsigned number for the operand to be compressed, to the operand to be compressed Third presets position and carries out or operate to the 4th default position to obtain third operating result, and it is the behaviour to be compressed that the third, which presets position, Last into second to count, the 4th default position are first of the operand to be compressed to last One in second, and the 4th default position is located at before the third presets position, the 4th default position and described the The difference of three default positions is less than the digit of the first operand and 1 difference;
Second compression unit obtains the pressure for being intercepted based on operand to be compressed described in the third operand pair Contracting number.
10. a kind of storage medium, which is characterized in that be stored with computer program code, the computer in the storage medium The mixing multiplication addition process method as described in claim 1 to 6 any one is realized when program code is run by processor.
CN201910702995.9A 2019-07-31 2019-07-31 Hybrid multiplication and addition processing method and device Active CN110399117B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910702995.9A CN110399117B (en) 2019-07-31 2019-07-31 Hybrid multiplication and addition processing method and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910702995.9A CN110399117B (en) 2019-07-31 2019-07-31 Hybrid multiplication and addition processing method and device

Publications (2)

Publication Number Publication Date
CN110399117A true CN110399117A (en) 2019-11-01
CN110399117B CN110399117B (en) 2021-05-28

Family

ID=68326981

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910702995.9A Active CN110399117B (en) 2019-07-31 2019-07-31 Hybrid multiplication and addition processing method and device

Country Status (1)

Country Link
CN (1) CN110399117B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112434317A (en) * 2020-11-24 2021-03-02 深圳前海微众银行股份有限公司 Data processing method, device, equipment and storage medium

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040133618A1 (en) * 2002-11-06 2004-07-08 Nokia Corporation Method and system for performing a multiplication operation and a device
CN1598757A (en) * 2004-09-02 2005-03-23 中国人民解放军国防科学技术大学 Design method of number mixed multipler for supporting single-instruction multiple-operated
CN101174200A (en) * 2007-05-18 2008-05-07 清华大学 5-grade stream line structure of floating point multiplier adder integrated unit
CN101178645A (en) * 2007-12-20 2008-05-14 清华大学 Paralleling floating point multiplication addition unit
CN101986260A (en) * 2010-11-25 2011-03-16 中国人民解放军国防科学技术大学 Multiply-add method and multiply-add apparatus
CN102722352A (en) * 2012-05-21 2012-10-10 华南理工大学 Booth multiplier
US8417760B2 (en) * 2005-10-28 2013-04-09 Infineon Technologies Ag Device and method for calculating a multiplication addition operation and for calculating a result of a modular multiplication
CN103294446A (en) * 2013-05-14 2013-09-11 中国科学院自动化研究所 Fixed-point multiply-accumulator
CN103795421A (en) * 2014-02-26 2014-05-14 活点信息技术有限公司 Method for data compression and decompression i
CN104025024A (en) * 2011-12-22 2014-09-03 英特尔公司 Packed data operation mask shift processors, methods, systems, and instructions
CN105045560A (en) * 2015-08-25 2015-11-11 浪潮(北京)电子信息产业有限公司 Fixed-point multiply-add operation method and apparatus

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040133618A1 (en) * 2002-11-06 2004-07-08 Nokia Corporation Method and system for performing a multiplication operation and a device
CN1735857A (en) * 2002-11-06 2006-02-15 诺基亚有限公司 Method and system for performing a multiplication operation and a device
CN1598757A (en) * 2004-09-02 2005-03-23 中国人民解放军国防科学技术大学 Design method of number mixed multipler for supporting single-instruction multiple-operated
US8417760B2 (en) * 2005-10-28 2013-04-09 Infineon Technologies Ag Device and method for calculating a multiplication addition operation and for calculating a result of a modular multiplication
CN101174200A (en) * 2007-05-18 2008-05-07 清华大学 5-grade stream line structure of floating point multiplier adder integrated unit
CN101178645A (en) * 2007-12-20 2008-05-14 清华大学 Paralleling floating point multiplication addition unit
CN101986260A (en) * 2010-11-25 2011-03-16 中国人民解放军国防科学技术大学 Multiply-add method and multiply-add apparatus
CN104025024A (en) * 2011-12-22 2014-09-03 英特尔公司 Packed data operation mask shift processors, methods, systems, and instructions
CN102722352A (en) * 2012-05-21 2012-10-10 华南理工大学 Booth multiplier
CN103294446A (en) * 2013-05-14 2013-09-11 中国科学院自动化研究所 Fixed-point multiply-accumulator
CN103795421A (en) * 2014-02-26 2014-05-14 活点信息技术有限公司 Method for data compression and decompression i
CN105045560A (en) * 2015-08-25 2015-11-11 浪潮(北京)电子信息产业有限公司 Fixed-point multiply-add operation method and apparatus

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
ISSA QIQIEH等: "《Energy-efficient approximate multiplier design using bit significance-driven logic compression》", 《DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2017》 *
PING HUANG等: "《An IEEE floating-point adder for multi-operation》", 《PROCEEDINGS. 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, 2004.》 *
S. SMITH: "《Serial/Parallel architectures for area-efficient vector multiplication》", 《ICASSP "87. IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING》 *
吉伟等: "基于FPGA的高速流水定点乘法器的设计", 《计算机技术与发展》 *
李正杰等: "《一种千万门FPGA芯片中DSP硬核的设计》", 《微电子学》 *
赵倩等: "《基于流水线重构技术的16x16位乘加器的设计》", 《微计算机信息》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112434317A (en) * 2020-11-24 2021-03-02 深圳前海微众银行股份有限公司 Data processing method, device, equipment and storage medium

Also Published As

Publication number Publication date
CN110399117B (en) 2021-05-28

Similar Documents

Publication Publication Date Title
US9804841B2 (en) Single instruction multiple data add processors, methods, systems, and instructions
CN115344237B (en) Data processing method combining Karatsuba and Montgomery modular multiplication
CN109814838B (en) Method, hardware device and system for obtaining intermediate result set in encryption and decryption operation
US7546330B2 (en) Systems for performing multiply-accumulate operations on operands representing complex numbers
US7580966B2 (en) Method and device for reducing the time required to perform a product, multiplication and modular exponentiation calculation using the Montgomery method
CN110109646A (en) Data processing method, device and adder and multiplier and storage medium
KR20200055647A (en) Multiplier and method for operating thereof
US11604970B2 (en) Micro-processor circuit and method of performing neural network operation
US20140101220A1 (en) Composite finite field multiplier
CN110399117A (en) A kind of mixing multiplication addition process method and device
US7546329B2 (en) Systems for performing multiplication operations on operands representing complex numbers
US7120660B2 (en) Method of and apparatus for modular multiplication
Barua et al. Binary arithmetic for DNA computers
WO2022146436A1 (en) A low footprint hardware architecture for kyber-kem
US20050149595A1 (en) Apparatus and method for calculating a result of a modular multiplication
CN113672196B (en) Double multiplication calculating device and method based on single digital signal processing unit
JPH0234054B2 (en)
US7607165B2 (en) Method and apparatus for multiplication and/or modular reduction processing
CN114527956A (en) Computing method for non-fixed point scalar multiplication in SPA attack resistant SM2 cryptographic algorithm
CN108874367B (en) Compound finite field inverter based on power operation and inversion method thereof
Nadjia et al. High throughput parallel montgomery modular exponentiation on FPGA
CN1258883C (en) Method for converting binary representation of number in signed binary representation
US20120237025A1 (en) Device and method for determining an inverse of a value related to a modulus
CN111610955B (en) Data saturation and packaging processing component, chip and equipment
CN112685003B (en) Arithmetic device for obtaining modular multiplication result of homologous password

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant