CN1591820A - Dielectric cavity priority double mosaic producing process - Google Patents
Dielectric cavity priority double mosaic producing process Download PDFInfo
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- CN1591820A CN1591820A CN 03156535 CN03156535A CN1591820A CN 1591820 A CN1591820 A CN 1591820A CN 03156535 CN03156535 CN 03156535 CN 03156535 A CN03156535 A CN 03156535A CN 1591820 A CN1591820 A CN 1591820A
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- interlayer hole
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Abstract
The present invention provides a dielectric layer hole priority double-mosaic process. Said process includes the following steps: providing a semiconductor substrate on which a conductive structure is formed and a dielectric layer is set, in which said dielectric layer contains a dielectric layer hole opening for exposing partial said conductive structure; filling the interior of said electric layer hole opening with gap-filling polymer (GFP) material and forming a gap-filled polymer layer on said dielectric layer; back etching said gap-filled polymer layer to a predefined depth to make the surface of said gap-filled polymer layer is lower than surface of said dielectric layer to form recessed groove, so that the side wall of partial said dielectric layer hole opening can be exposed; and making a surface treatment process to change the characteristics of side wall of said dielectric layer hole opening and surface of said gap-filled polymer layer, so that it can prevent the deep ultra-violet (DUV) photoresist to be filled into said recessed groove from producing any physical or chemical action with the above-mentioned side wall and surface.
Description
Technical field
The invention relates to a kind of dual damascene (dual dama scene) processing procedure, refer to preferential (via-first) double-insert process of a kind of interlayer hole especially, the DUV photoresistance in the time of can solving definition irrigation canals and ditches pattern residues in the problem in the interlayer hole.
Background technology
Copper dual-damascene (dual damascene) technology collocation dielectric layer with low dielectric constant be present known to for high integration, (high-speed) logical integrated circuit chip manufacturing and at the metal interconnect solution of the deep-sub-micrometer below 0.18 micron (deep sub-micro) manufacture of semiconductor the best at a high speed.This is because copper has low-resistance value (than aluminium low 30%) and preferable anti-electricity causes the characteristic of moving (electromigration resistance), the RC that advanced low-k materials then can help to reduce between the plain conductor postpones (RC delay), hence one can see that, and copper metal double-insert interconnect technology seems in integrated circuit manufacture process and becomes more and more important.At present, double-insert process has preferential (trench-first) dual damascene of so-called irrigation canals and ditches, preferential (via-first) dual damascene of interlayer hole, part interlayer hole (partial-via) dual damascene basically, and aims at selection such as (self-aligned) dual damascene voluntarily.Wherein, preferential (via-first) dual damascene of interlayer hole briefly promptly is to utilize little shadow of multiple tracks and etching step, and the definition interlayer hole defines irrigation canals and ditches in the interlayer hole top subsequently more earlier, constitutes the dual-damascene structure of one.
See also Fig. 1 to Fig. 5, Fig. 1 to Fig. 5 is preferential (via-first) double-insert process of known interlayer hole.As shown in Figure 1, prior art method at first provides semiconductor substrate 100, has conductive structure 111 and 112 on it, and for example copper is inlayed lead, is formed in bottom or the component layer 101.Then; deposition forms protective coating (capping layer) 115 on the semiconductor-based end 100 in regular turn; its composition is generally silicon nitride; be covered in the exposed surface of this conductive structure 111 and 112; an and storehouse dielectric layer 120; it generally includes one first dielectric layer 121, one second dielectric layer 123, and a etching stopping layer 122 between first dielectric layer 121 and second dielectric layer 123.On first dielectric layer 121, can deposit a silicon oxynitride (SiNO) subsequently again and stop layer 130.Then, stop to form on the layer 130 a DUV photoresist layer 140 in silicon oxynitride, and define interlayer hole perforate 141 and 142 in a DUV photoresist layer 140, suppose that wherein interlayer hole perforate 141 is independent (isolated) interlayer hole pattern, that is it there is no other interlayer hole pattern around contiguous and is defined, and interlayer hole perforate 142 is intensive (dense) interlayer hole pattern.Then; carrying out an etch process, is etch shield with a DUV photoresist layer 140, via the interlayer hole perforate 141 and 142 in the DUV photoresist layer 140 in regular turn the etching silicon oxynitride stop the layer 130, storehouse dielectric layer 120; up to protective coating 115, so to form interlayer hole 151 and 152.
As shown in Figure 2, after removing a DUV photoresist layer 140, on the semiconductor-based end 100, be coated with a joint filling macromolecule layer 201 immediately, and fill up interlayer hole 151 and 152.Joint filling macromolecule layer 201 generally is made of the i-line photoresistance.The coating class of joint filling macromolecule layer 201 is like general photoresistance coating process, thereafter and in addition baking hardening.As shown in Figure 3, then carry out an etch-back processing procedure, joint filling macromolecule layer 201 is etched back to a desired depth, make the surface of joint filling macromolecule layer 201 be lower than silicon oxynitride and stop layer 130, form groove 301 and 302.As shown in Figure 4, prior art method then directly is coated with the 2nd DUV photoresist layer 401 on the semiconductor-based end 100, and fills up groove 301 and 302.
See also Fig. 5 and Fig. 6, wherein Fig. 6 is the top view of Fig. 5, and Fig. 5 is the section of Fig. 6 along AA ' tangent line.Then carry out an exposure manufacture process, utilize a definition that the light shield of irrigation canals and ditches pattern is arranged, being light source with DUV exposes irrigation canals and ditches pattern (not shown) respectively at the top of groove 301 and 302.Subsequently, utilize developer solution that the photoresistance that is exposed to the sun is removed, respectively at the top formation irrigation canals and ditches 411 and 412 of groove 301 and 302.Yet, when developer solution (being generally hydrophily) develops at the photoresistance that carries out independence (isolated) interlayer hole 151 upper grooves 301, it is residual 511 often can't to clean the photoresistance that takes place fully as shown in Figure 5, and it can cause the generation of little irrigation canals and ditches (micro-trenching) or short hedge (fence) phenomenon.This may be because the surface of joint filling macromolecule layer 201 is repellency (hydrophobic), adds that capillarity causes due to the bottom of independent interlayer hole 151 upper grooves 301 of the difficult contact of developer solution.
Summary of the invention
Therefore, main purpose of the present invention is to provide a kind of dual damascene interconnect processing procedure, can avoid the generation of little irrigation canals and ditches (micro-trenching) or short hedge (fence) phenomenon.
For reaching above-mentioned purpose, the invention provides the preferential double-insert process of a kind of interlayer hole, comprise the following step: the semiconductor substrate is provided, is formed with conductive structure and dielectric layer on it and is located on this semiconductor-based end, wherein this dielectric layer includes an interlayer hole perforate, exposes this conductive structure of part; In this interlayer hole perforate, fill up joint filling macromolecular material (GFP), and form a joint filling macromolecule layer on this dielectric layer; This joint filling macromolecule layer one desired depth of etch-back makes the surface of this joint filling macromolecule layer be lower than the surface of this dielectric layer, forms groove, exposes the sidewall of this interlayer hole perforate of part whereby; And carry out surface treatment means, in order to the characteristic on the surface of the sidewall that changes this interlayer hole perforate and this joint filling macromolecule layer, avoid the sidewall of follow-up deep UV (DUV) photoresistance of inserting this groove and this interlayer hole perforate whereby or any physics or chemical action take place with the surface of this joint filling macromolecule layer.
According to above-mentioned purpose, the invention provides the preferential double-insert process of a kind of interlayer hole, include the following step: provide the semiconductor substrate, being formed with a conductive structure and a dielectric layer on it was located on this semiconductor-based end, wherein this dielectric layer includes an interlayer hole perforate, exposes this conductive structure of part; In this interlayer hole perforate, fill up a joint filling macromolecular material, and form a joint filling macromolecule layer on this dielectric layer; This joint filling macromolecule layer one desired depth of etch-back makes the surface of this joint filling macromolecule layer be lower than the surface of this dielectric layer, forms a groove, exposes the sidewall of this interlayer hole perforate of part whereby; Carry out surface treatment means, in order to the characteristic on the surface of the sidewall of this interlayer hole perforate of homogenization and this joint filling macromolecule layer; In this groove, insert deep UV (DUV) photoresistance, and on this dielectric layer, form a photoresist layer; Carry out a micro-photographing process, in this photoresist layer, to form a ditch channel opening that is positioned in this interlayer hole perforate; And be etch shield with this photoresist layer, via this this dielectric layer of ditch channel opening etching and this joint filling macromolecule layer.Wherein this joint filling macromolecular material is constituted by the i-line photoresistance.These surface treatment means are the surfaces that contact sidewall and this joint filling macromolecule layer of this interlayer hole perforate with the living radical that this joint filling macromolecular material is had a low rate of etch.
Description of drawings
Fig. 1 to Fig. 5 is preferential (via-first) double-insert process of known interlayer hole;
Fig. 6 is the top view of Fig. 5;
Fig. 7 to Figure 11 is the method schematic diagram according to the present invention's first preferred embodiment;
Figure 12 and Figure 13 are the method schematic diagram according to the present invention's second preferred embodiment.
Symbol description:
100～semiconductor-based the end
101～bottom or component layer
111,112～conductive structure
115～protective coating
120～storehouse dielectric layer
121～the first dielectric layers
122～etching stopping layer
123～the second dielectric layers
130～silicon oxynitride stops layer
140～the one DUV photoresist layers
141,142～interlayer hole perforate
151,152～interlayer hole
201～joint filling macromolecule layer
301,302～groove
401～the 2nd DUV photoresist layers
411,412～irrigation canals and ditches perforate
511～photoresistance is residual
700～semiconductor-based the end
711,712～conductive structure
715～protective coating
720～storehouse dielectric layer
721～the first dielectric layers
722～etching stopping layer
723～the second dielectric layers
730～silicon oxynitride stops layer
740～the one DUV photoresist layers
741,742～interlayer hole perforate
751,752～interlayer hole
801～joint filling macromolecule layer
901,902～groove
911,912～interlayer hole sidewall
1001～the 2nd DUV photoresist layers
1011,1012～irrigation canals and ditches perforate
1201～macromolecule membrane
Embodiment
See also Fig. 7 to Figure 11, Fig. 7 to Figure 11 is according to preferential (via-first) double-insert process generalized section of the interlayer hole of the present invention's first preferred embodiment.Shown in figure seven, the inventive method at first provides semiconductor substrate 700, has conductive structure 711 and 712 on it, and for example copper is inlayed lead.Then; deposition forms protective coating (cappinglayer) 715 on the semiconductor-based end 700 in regular turn; its composition is generally silicon nitride; be covered in the exposed surface of this conductive structure 711 and 712; an and storehouse dielectric layer 720; it generally includes one first dielectric layer 721, one second dielectric layer 723, and a etching stopping layer 722 between first dielectric layer 721 and second dielectric layer 723.The dielectric constant of first and second dielectric layer is preferable less than 3, and its selection has FLARE
TM, SiLK
TM, arylene ether polymer (poly (arylene ether) polymer), parylene compounds, polyimide (polyimide) be macromolecule, fluoridize polyimide (fluorinated polyimide), HSQ, BCB, fluorine silex glass (FSG), silicon dioxide, porous silica glass (nanoporous silica) or Teflon or the like, but be not limited to above-mentioned listed composition.On first dielectric layer 721, can select to deposit a silicon oxynitride (SiNO) subsequently usually again and stop layer 730.Then, stop to form on the layer 730 a DUV photoresist layer 740 in silicon oxynitride, and define interlayer hole perforate 741 and 742 in a DUV photoresist layer 740, suppose that wherein interlayer hole perforate 741 is independent (isolated) interlayer hole pattern, that is it there is no other interlayer hole pattern around contiguous and is defined, and interlayer hole perforate 742 is intensive (dense) interlayer hole pattern, that is still has other interlayer hole pattern to be defined around its vicinity.Then; carrying out an etch process, is etch shield with a DUV photoresist layer 740, via the interlayer hole perforate 741 and 742 in the DUV photoresist layer 740 in regular turn the etching silicon oxynitride stop the layer 730, storehouse dielectric layer 720; up to protective coating 715, so to form interlayer hole 751 and 752. Interlayer hole 751 and 752 average pore size are about about 0.1 to 0.2 micron.
As shown in Figure 8, removing a DUV photoresist layer 740 backs (utilizing the oxygen ashing method), on the semiconductor-based end 700, be coated with a joint filling macromolecule layer 801 immediately, and fill up interlayer hole 751 and 752.Joint filling macromolecule layer 801 generally is made of the i-line photoresistance, for example contain novolak resin, polystyrene resins (poly hydroxystyrene, PHS) or acrylate (acrylate) class or the like i-line photoresistance composition.The coating class of joint filling macromolecule layer 801 is like general photoresistance coating process, thereafter and in addition baking hardening.As shown in Figure 9, then carry out an etch-back processing procedure, joint filling macromolecule layer 801 is etched back to a desired depth, make the surface of joint filling macromolecule layer 801 be lower than silicon oxynitride and stop layer 730, form groove 901 and 902.Groove 901 and 902 be respectively by the sidewall 911 of the part interlayer hole perforate 751 that exposes and 752 and 912 and the surface institute of joint filling macromolecule layer 801 constituted.Subsequently, carry out surface treatment means, the interlayer hole perforate 751 that exposes in order to change and the characteristic on 752 sidewalls and joint filling macromolecule layer 801 surfaces are avoided the sidewall 911 and 912 or with the surface of joint filling macromolecule layer 801 any physics or chemical action take place of follow-up deep UV (DUV) photoresistance of inserting groove 901 and 902 and interlayer hole perforate whereby.
According to first preferred embodiment of the present invention, these surface treatment means are (to be preferably the living radical that is less than or equal to 100 dust per minutes (/min) rate of etch) joint filling polymer material layer 801 is had a low rate of etch, for example oxygen radical (oxygen radical) or superoxide radical (superoxide radical), the sidewall 911 of contact interlayer hole perforate and 912 and the surface of joint filling macromolecule layer 801.By utilizing the sidewall 911 and 912 and the surface of joint filling macromolecule layer 801 that the joint filling macromolecular material is had the interlayer hole perforate that the living radical contact of low rate of etch exposes, can make the surface of joint filling macromolecule layer 801 become hydrophily (hydrophilic) surface or make the sidewall 911 and 912 of the interlayer hole perforate that exposes form most hydrogen-oxygen keys, can make follow-up hydrophily developer solution be goed deep into groove 901 and 902 removing DUV photoresistances whereby with the surface of joint filling macromolecule layer 801.Be noted that the present invention emphasizes with the sidewall 911 of the living radical contact interlayer hole perforate that joint filling polymer material layer 801 had a low rate of etch and 912 and the surface of joint filling macromolecule layer 801, in other words, it is used and not only is defined in oxygen radical or the superoxide radical of being lifted, and other possible free radical source comprises ozone (O
3), hydrogen peroxide (H
2O
2), and any can be through decomposing to produce the material that contains oxygen (but nonnitrogenous) of free radical, for example carbon monoxide, carbon dioxide etc.In addition, these surface treatment means can dry type or wet method (no matter embathe or wash) carry out.
As shown in figure 10, the inventive method then directly is coated with the 2nd DUV photoresist layer 1001 on the semiconductor-based end 700, and fills up groove 901 and 902.
As shown in figure 11, then carry out an exposure manufacture process, utilize a definition that the light shield (not shown) of irrigation canals and ditches pattern is arranged, being light source with DUV exposes irrigation canals and ditches pattern (not shown) respectively at the top of groove 901 and 902.Subsequently, utilize developer solution that the photoresistance that is exposed to the sun is removed, respectively at the top formation irrigation canals and ditches 1011 and 1012 of groove 901 and 902.As shown in figure 11, prior art method institute issuable photoresistance is residual does not exist.
See also Figure 12 and Figure 13, Figure 12 and Figure 13 are according to the preferential double-insert process generalized section of the interlayer hole of the present invention's second preferred embodiment.As shown in figure 12, after removing a DUV photoresist layer 740, on the semiconductor-based end 700, be coated with a joint filling macromolecule layer 801 immediately, and fill up interlayer hole 751 and 752.Then carry out an etch-back processing procedure, joint filling macromolecule layer 801 is etched back to a desired depth, make the surface of joint filling macromolecule layer 801 be lower than silicon oxynitride and stop layer 830, form groove 901 and 902.Groove 901 and 902 be respectively by the sidewall 911 of the part interlayer hole perforate 751 that exposes and 752 and 912 and the surface institute of joint filling macromolecule layer 801 constituted.Subsequently, carry out surface treatment means, the interlayer hole perforate 751 that exposes in order to homogenization and the characteristic on 752 sidewalls and joint filling macromolecule layer 801 surfaces are avoided the sidewall 911 and 912 or with the surface of joint filling macromolecule layer 801 any physics or chemical action take place of follow-up deep UV (DUV) photoresistance of inserting groove 901 and 902 and interlayer hole perforate whereby.
According to second preferred embodiment of the present invention, these surface treatment means be in the sidewall 911 of interlayer hole perforate and 912 with the surface of joint filling macromolecule layer 801 on formation one all thick macromolecule membrane 1201.Macromolecule membrane 1201 can utilize CHF
3/ H
2, CF
4/ CHF
3Or other similar electricity slurry that can form the hydrocarbon film of macromolecule is combined to form, and its thickness is about 50 dusts (angstrom) between 150 dusts.
Claims (23)
1. preferential (via-first) double-insert process of an interlayer hole includes the following step:
The semiconductor substrate is provided, is formed with a conductive structure (conductive structure) and a dielectric layer on it and is located on this semiconductor-based end, wherein this dielectric layer includes an interlayer hole perforate (via opening), exposes this conductive structure of part;
(gap-filling polymer GFP), and forms a joint filling macromolecule layer (GFP layer) on this dielectric layer to fill up a joint filling macromolecular material in this interlayer hole perforate;
This joint filling macromolecule layer one desired depth of etch-back makes the surface of this joint filling macromolecule layer be lower than the surface of this dielectric layer, forms a groove, exposes the sidewall of this interlayer hole perforate of part whereby; And
Carry out surface treatment means, in order to the characteristic on the surface of the sidewall that changes this interlayer hole perforate and this joint filling macromolecule layer, avoid the sidewall of follow-up deep UV (DUV) photoresistance of inserting this groove and this interlayer hole perforate whereby or any physics or chemical action take place with the surface of this joint filling macromolecule layer.
2. the preferential double-insert process of interlayer hole according to claim 1, wherein this joint filling macromolecular material is constituted by the i-line photoresistance.
3. the preferential double-insert process of interlayer hole according to claim 1, wherein the dielectric constant of this dielectric layer is less than 3.
4. the preferential double-insert process of interlayer hole according to claim 1 wherein has one to stop layer in addition on this dielectric layer.
5. the preferential double-insert process of interlayer hole according to claim 4, wherein this stop the layer being constituted by silicon oxynitride (silicon oxynitride).
6. the preferential double-insert process of interlayer hole according to claim 1, wherein these surface treatment means are the surfaces that contact sidewall and this joint filling macromolecule layer of this interlayer hole perforate with the living radical that this joint filling macromolecular material is had a low rate of etch.
7. the preferential double-insert process of interlayer hole according to claim 6 wherein should low rate of etch be to be less than or equal to 100 dust per minutes (/min).
8. the preferential double-insert process of interlayer hole according to claim 6, wherein this living radical includes oxygen radical (oxygen radical) and superoxide radical (superoxideradical).
9. the preferential double-insert process of interlayer hole according to claim 6, wherein, can make the surface of this joint filling macromolecule layer become hydrophily (hydrophilic) surface by utilizing the living radical that this joint filling macromolecular material is had low rate of etch to contact the surface of sidewall and this joint filling macromolecule layer of this interlayer hole perforate.
10. the preferential double-insert process of interlayer hole according to claim 1, wherein these surface treatment means are to form an all thick macromolecule membrane in the sidewall of this interlayer hole perforate and the surface of this joint filling macromolecule layer.
11. the preferential double-insert process of interlayer hole according to claim 10, wherein this macromolecule membrane is to utilize CHF
3/ H
2Or CF
4/ CHF
3The electricity slurry forms.
12. the preferential double-insert process of interlayer hole according to claim 10, wherein the thickness of this macromolecule membrane is that 50 dusts (angstrom) are to 150 dusts.
13. the preferential double-insert process of interlayer hole includes the following step:
The semiconductor substrate is provided, is formed with a conductive structure and a dielectric layer on it and is located on this semiconductor-based end, wherein this dielectric layer includes an interlayer hole perforate, exposes this conductive structure of part;
In this interlayer hole perforate, fill up a joint filling macromolecular material, and form a joint filling macromolecule layer on this dielectric layer;
This joint filling macromolecule layer one desired depth of etch-back makes the surface of this joint filling macromolecule layer be lower than the surface of this dielectric layer, forms a groove, exposes the sidewall of this interlayer hole perforate of part whereby;
Carry out surface treatment means, in order to the characteristic on the surface of the sidewall of this interlayer hole perforate of homogenization and this joint filling macromolecule layer;
In this groove, insert deep UV (DUV) photoresistance, and on this dielectric layer, form a photoresist layer;
Carry out a micro-photographing process, in this photoresist layer, to form a ditch channel opening that is positioned in this interlayer hole perforate; And
With this photoresist layer is etch shield, via this this dielectric layer of ditch channel opening etching and this joint filling macromolecule layer.
14. the preferential double-insert process of interlayer hole according to claim 13, wherein this joint filling macromolecular material is constituted by the i-line photoresistance.
15. the preferential double-insert process of interlayer hole according to claim 13, wherein the dielectric constant of this dielectric layer is less than 3.
16. the preferential double-insert process of interlayer hole according to claim 13 wherein has one to stop layer in addition on this dielectric layer.
17. the preferential double-insert process of interlayer hole according to claim 13, wherein these surface treatment means are the surfaces that contact sidewall and this joint filling macromolecule layer of this interlayer hole perforate with the living radical that this joint filling macromolecular material is had a low rate of etch.
18. the preferential double-insert process of interlayer hole according to claim 17 wherein should low rate of etch be to be less than or equal to 100 dust per minutes (/min).
19. the preferential double-insert process of interlayer hole according to claim 17, wherein this living radical includes oxygen radical and superoxide radical.
20. the preferential double-insert process of interlayer hole according to claim 17, wherein, can make the surface of this joint filling macromolecule layer become hydrophilic surface by utilizing the living radical that this joint filling macromolecular material is had low rate of etch to contact the surface of sidewall and this joint filling macromolecule layer of this interlayer hole perforate.
21. the preferential double-insert process of interlayer hole according to claim 13, wherein these surface treatment means are to form an all thick macromolecule membrane in the sidewall of this interlayer hole perforate and the surface of this joint filling macromolecule layer.
22. the preferential double-insert process of interlayer hole according to claim 21, wherein this macromolecule membrane is to utilize CHF
3/ H
2Or CF
4/ CHF
3The electricity slurry forms.
23. the preferential double-insert process of interlayer hole according to claim 21, wherein the thickness of this macromolecule membrane is that 50 dusts (angstrom) are to 150 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031565352A CN1294640C (en) | 2003-09-03 | 2003-09-03 | Dielectric cavity priority double mosaic producing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031565352A CN1294640C (en) | 2003-09-03 | 2003-09-03 | Dielectric cavity priority double mosaic producing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1591820A true CN1591820A (en) | 2005-03-09 |
| CN1294640C CN1294640C (en) | 2007-01-10 |
Family
ID=34598462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031565352A Expired - Lifetime CN1294640C (en) | 2003-09-03 | 2003-09-03 | Dielectric cavity priority double mosaic producing process |
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| Country | Link |
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| CN (1) | CN1294640C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420001C (en) * | 2005-05-27 | 2008-09-17 | 中芯国际集成电路制造(上海)有限公司 | Method for improving CMP process window of deep slot DRAM tungsten metal bit line |
| CN101312161B (en) * | 2007-05-21 | 2010-12-01 | 国际商业机器公司 | Electronic structure and manufacturing method |
| CN101971301A (en) * | 2008-03-11 | 2011-02-09 | 朗姆研究公司 | Line width roughness improvement with noble gas plasma |
| CN110391230A (en) * | 2018-04-16 | 2019-10-29 | 华邦电子股份有限公司 | Memory device and its manufacturing method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106001004A (en) * | 2016-07-08 | 2016-10-12 | 北京睿昱达科技有限公司 | Glow discharge plasma photovoltaic panel cleaning device and photovoltaic panel cleaning method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6432814B1 (en) * | 2000-11-30 | 2002-08-13 | Agere Systems Guardian Corp. | Method of manufacturing an interconnect structure having a passivation layer for preventing subsequent processing reactions |
| US6794292B2 (en) * | 2001-07-16 | 2004-09-21 | United Microelectronics Corp. | Extrusion-free wet cleaning process for copper-dual damascene structures |
| US6511916B1 (en) * | 2002-01-07 | 2003-01-28 | United Microelectronics Corp. | Method for removing the photoresist layer in the damascene process |
| US6579791B1 (en) * | 2002-02-12 | 2003-06-17 | Taiwan Semiconductor Manufacturing Company | Method to form dual damascene structure |
-
2003
- 2003-09-03 CN CNB031565352A patent/CN1294640C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420001C (en) * | 2005-05-27 | 2008-09-17 | 中芯国际集成电路制造(上海)有限公司 | Method for improving CMP process window of deep slot DRAM tungsten metal bit line |
| CN101312161B (en) * | 2007-05-21 | 2010-12-01 | 国际商业机器公司 | Electronic structure and manufacturing method |
| CN101971301A (en) * | 2008-03-11 | 2011-02-09 | 朗姆研究公司 | Line width roughness improvement with noble gas plasma |
| CN101971301B (en) * | 2008-03-11 | 2014-11-19 | 朗姆研究公司 | Line width roughness improvement with noble gas plasma |
| CN110391230A (en) * | 2018-04-16 | 2019-10-29 | 华邦电子股份有限公司 | Memory device and its manufacturing method |
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| Publication number | Publication date |
|---|---|
| CN1294640C (en) | 2007-01-10 |
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| CX01 | Expiry of patent term |
Granted publication date: 20070110 |