CN1588272A - Real time power managing method and its system - Google Patents
Real time power managing method and its system Download PDFInfo
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- CN1588272A CN1588272A CN 200410055974 CN200410055974A CN1588272A CN 1588272 A CN1588272 A CN 1588272A CN 200410055974 CN200410055974 CN 200410055974 CN 200410055974 A CN200410055974 A CN 200410055974A CN 1588272 A CN1588272 A CN 1588272A
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Abstract
It is a real time power supply management system and method which is used to quickly adjust computer system's power expenditure. The north bridge chip detects system's executive state and according to this detect the south bridge chip quickly adjusts inner component's voltage and frequency by transmitting corresponding control signal to a controller through a set of sideband signal lead. In this system the sideband signal lead replaces the SMBUS. It is a quicker and real-time electricity-saving mechanism.
Description
Technical field
The present invention relates to a kind of method of computer system power source management, particularly replace the System and method for of stepping power management interface (ACPI) System Management Bus (SMBUS).
Background technology
In computer system now, power saving one is to being important topic.Especially more crucial on the brain machine that with battery is main power supply.Computer system now the real according to this power management specification of doing mainly be from stepping power management interface (Advanced Configuration and Power Interface; ACPI) standard.Its framework as shown in Figure 1a.
ACPI is the specification for software and the mutual collocation of hardware.The principle of power saving is to detect the running situation by operating system, by software driver, follows a specific communication protocol and sends order, makes hardware according to design, reduces operating voltage and frequency, reaches purpose of power saving.Known system framework 100 as shown in Figure 1a comprises software layer 101, system hardware layer 103 and between the ACPI of centre key-course 112.Known power management, be by the 104 executive operating system power managements (OSPM) 106 of the operating system in the software layer 101, detect the practice condition of application program 102, issue an order by device driver 108 and 110 pairs of ACPI key-courses 112 of ACPI driver, convert the action of power saving to hardware signal, be sent to system hardware layer 103.ACPI key-course 112 is the frameworks between hardware and software, comprises program, ACPI control table (table), and ACPI register (register).In system hardware layer 103, control signal is by 124 master controls of South Bridge chip group, is sent to voltage controller 122 and frequency generator 126 by System Management Bus 128.Voltage controller 122 can change central processing unit 114, draw and quicken the operating voltage of port one 16 and internal memory 120 according to the control signal that System Management Bus 128 transmits, and frequency generator 126 can produce different clocks for each nextport hardware component NextPort according to the control signal that System Management Bus 128 transmits.
Generally, this is a kind of technology of being come control hardware by software.Need to support the program of ACPI standard and the common collocation of nextport hardware component NextPort to finish.Carry out because operating system and software are dependent on hardware, and the power management of hardware is dependent on the execution of software, when hardware because of battery saving mode during by reduction of speed, software execution usefulness also reduces, control ability and fiduciary level all have bottleneck.For instance, when central processing unit 114 enters the C3 sleep state, central processing unit 114 contents are not preserved, and high-speed cache can't be kept consistance, and system can't accept master control running (Master) and break in service.When taking place, master control requirement and interrupt request just reply running, but utmost point time-consuming.Because all power down modes of hardware all are by the software decision, can't real time reaction go out the true practice condition of hardware, so power saving effect is also had a greatly reduced quality.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of real-time method for managing power supply, be used for the power consumption of quick adjustment computer system.This real-time method for managing power supply comprises the following step.At first, a utilization rate of detection system running, and, produce a corresponding control signal according to this utilization rate and a flow coding schedule.Then, dynamically adjust the running parameter of an internal system assembly according to this control signal and a control parameter list.
Wherein produce the step of this control signal, comprise a grade of load of judging this utilization rate, and contrast this grade of load and this flow coding schedule, to obtain this control signal.And this flow coding schedule is to set according to the kenel and the characteristic of system in advance, in order to define a plurality of grades of load.This control parameter list is a Control of Voltage parameter list that is set by software for by a communication protocol, in order to define the Control of Voltage parameter of corresponding each grade of load, or a frequency control parameter list, in order to define the frequency control parameter of corresponding each grade of load.This internal system assembly is to be central processing unit, the internal memory or the acceleration port of drawing.
Another object of the present invention is to provide a kind of real-time power-supply management system, be used for the power consumption of quick adjustment computer system.This real-time power-supply management system comprises following assembly.One first chip, one second chip, a System Management Bus, polygon band signal lead-in wire, and a controller.This first chip is used for the detection system operating state, to produce a load information.This second chip is used for according to this load information, to produce a control signal.This System Management Bus (SMBUS) is used to transmit power management command.These sideband signals lead-in wires (sideband pins) are used for transmitting in real time this control signal.And this controller is used to receive this control signal, to regulate the running parameter of an internal system assembly.
Wherein this first chip is a north bridge chips, and this second chip is a South Bridge chip, and this System Management Bus is the communication protocol transmission power management command according to stepping power management interface (ACPI).This second chip further comprises kenel and the predefined flow coding schedule of characteristic according to present system.This controller is to be a voltage controller, comprises a Control of Voltage parameter list, in order to according to this control signal, regulates the voltage of this internal system assembly.And this Control of Voltage parameter list is preestablished by this System Management Bus by software.This controller can also be a frequency controller, comprises a frequency control parameter list, in order to according to this control signal, regulates the frequency of this internal system assembly.And this frequency control parameter list is preestablished by this System Management Bus by software.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 a is framework Figure 100 of known power source administration interface (ACPI).
Fig. 1 b is a known power source managing power saving control situation synoptic diagram.
Fig. 2 a is framework Figure 200 of the embodiment of the invention.
Fig. 2 b is the power-saving control situation synoptic diagram of the embodiment of the invention.
Fig. 3 is the south bridge flow coding schedule 202 in the embodiment of the invention.
Fig. 4 is the frequency control parameter list 204 in the embodiment of the invention.
Fig. 5 is the Control of Voltage parameter list 206 in the embodiment of the invention.
Attached symbol description
101～software layer, 102～application program
103～system hardware layer, 104～operating system
106～operating system power management, 108～device driver
110～ACPI driver, 112～ACPI key-course
Port is quickened in 114～central processing unit 116～drawing
118～north bridge chipset, 120～internal memory
122～voltage controller, 124～South Bridge chip group
126～frequency generator, 128～System Management Bus
202～south bridge flow coding schedule, 224～South Bridge chip group
222～voltage controller, 226～frequency generator
Embodiment
Because the South Bridge chip group is the key of control total system frequency and voltage, and electronic circuit is as long as these two kinds of important documents just can be controlled electrical source consumption in hand, so as long as south bridge can be accurate and real-time according to the frequency and the voltage of the utilization rate automatic control system of system, the power supply that natural system just can efficient control system.And,, and more close to system applies live telecast and accurately control so real-time can be good far beyond software because these controls all are initiatively to be initiated by south bridge.In addition, because south bridge control system now is to adopt System Management Bus (SMBUS) communication protocol, the time (suppose that clock is 100KHz, and expend 30 position write times) of 300 μ S is wanted in order of this kind mode at least.Just can finish if simultaneously voltage and frequency are done control then taken approximately above 1ms.The present invention proposes sideband signals (sideband signal) lead-in wire and replaces SMBUS, with control system frequency and voltage faster.
Shown in Fig. 2 a and Fig. 2 b, do not need the intervention of software in the framework 200 of the present invention, the substitute is one group of register of real work in South Bridge chip group 224, south bridge flow coding schedule 202 is in order to the foundation as power-saving control.And newly-increased many sideband signals lead-in wire is connected to voltage controller 222 and frequency generator 226 respectively, totally three of GPOa as shown in FIG., GPOb and GPOc.The number of pin count is not subject to the limits, the situation of apparent load classification and deciding.In nextport hardware component NextPort, north bridge chipset 118 has been controlled central processing unit 114, has been drawn and quicken all flow informations of port one 16, internal memory 120 and South Bridge chip group 224, can say so and understand system load unit the most completely.So in a preferred embodiment, by the various load states of north bridge chipset 118 detection systems, comprise central processing unit 114 utilization rates, internal memory 120 utilization rates are drawn and are quickened port one 16 utilization rates etc., send information to South Bridge chip group 224.The monitoring of system load can be a kind of performance of hardware state, that is does not need to carry out extra sampling action, and data itself are to exist in real time.This South Bridge chip group 224 is carried out the judgement of the grade of load after receiving the load information that north bridge chipset 118 transmitted, that these levels can be divided into is high, normally, lower and extremely low.As shown in Figure 3, the south bridge flow coding schedule 202 in the South Bridge chip group 224 can be a jumper list, is used for being defined in the corresponding control signal of output under what situation.In this example, GPOa, GPOb, GPOc respectively have two kinds of potential states (High and Low), so can produce eight kinds of combinations.This south bridge flow coding schedule 202 can comprise the load state of various other assemblies, defines more detailed jumper list, and it is described to be not limited to present embodiment.This south bridge flow coding schedule 202 can be when system start-up, and South Bridge chip group 224 initiatively produces automatically according to the entire system situation, also can be by the program fine setting, by the outside input from definite value.So by information and south bridge flow coding schedule 202 that comparison South Bridge chip group 224 transmits, South Bridge chip group 224 just produces corresponding control signal, sends voltage controller 222 and frequency generator 226 to from these sideband signals lead-in wire GPOa, GPOb and GPOc.In the present embodiment, voltage controller 222 has control central processing unit 114, and the function of the operating voltage of draw acceleration port one 16 and north bridge chipset 118 wherein comprises a Control of Voltage parameter list 206, as shown in Figure 5.With reference to this Control of Voltage parameter list 206, can know the pairing controlled variable of current potential of sideband signals lead-in wire GPOa, GPOb and GPOc, for example three's current potential is when High, High, High, and promptly superpressure 10%.After knowing controlled variable, voltage controller 222 just to the corresponding operating voltage of these assembly outputs, makes it to be operated in the predetermined scope.Similarly, frequency generator 226 is to be responsible for producing the frequency of operation that internal system is respectively answered assembly, along with the increase and decrease of frequency, has determined the power saving and the power consumption of assembly.After the CONTROLLED POTENTIAL that receives sideband signals lead-in wire GPOa, GPOb and GPOc transmission, with reference to a frequency control parameter list 204 shown in Figure 4, to know the controlled variable of these current potential correspondences.For example when the current potential of these three sideband signals lead-in wires was Low, Low, High, controlled variable was exactly frequency reducing 20%.At last, this frequency generator 226 produces the frequency of correspondence just according to the controlled variable of correspondence for each corresponding assembly.
Wherein, the transmission of this control signal, be by sideband signals lead-in wire GPOa, GPOb and GPOc, replaced the communication protocol transmission of known system management bus 128 with ACPI, so need the improvement of South Bridge chip group 224, voltage controller 222 and frequency generator 226 on the hardware, to break through the bottleneck of control rate.And as south bridge flow coding schedule 202, this frequency control parameter list 204 and Control of Voltage parameter list 206 also can be when system start-up, are initiatively produced automatically according to the entire system situation by firmware, or by program fine setting, by the outside input from definite value.
Lift another preferred embodiment with Fig. 2 a, the normal working voltage of supposing central processing unit 114 is 3.3 volts (V), normal working frequency is 2.0G hertz (Hz), and define in known this south bridge flow coding schedule 202, frequency control parameter list 204 and the Control of Voltage parameter list 206, when central processing unit 114 is in high load, just boost 1% and the processing of overclocking 10%.Then the operating load that detects central processing unit 114 when north bridge chipset 118 is 100%, this load information passes in the South Bridge chip group 224 and contrasts with south bridge flow coding schedule 202, be " load is high ", this South Bridge chip group 224 is just sent corresponding lead signal GPOa to voltage controller 222 and frequency generator 226, GPOb and GPOc, after making voltage controller 222 contrast Control of Voltage parameter lists 206, to central processing unit 114 output 3.33V, and behind the frequency generator 226 contrast frequency control parameter lists 204, make the frequency of central processing unit 214 be upgraded to 2.2GHz.In other words, framework of the present invention in assembly work permissible range, except the problem of the known power saving management of efficient solution, in needs, even can produce the usefulness higher than expection.
Fig. 1 b is known power source managing power saving control situation synoptic diagram.The load 301 of central processing unit is a curve that changes in time.And regulation rate 302 display power supply management systems are with the degree of central processing unit frequency reducing.Full to 100% the time when load 301, regulation rate 302 is controlled at 100%.If load reduces, then also frequency reducing thereupon of central processing unit is to reduce the power consumption expenditure.Relatively, Fig. 2 b is the power-saving control situation synoptic diagram for the embodiment of the invention.Maximum characteristic is exactly that real-time and the degree of accuracy of regulation rate 303 all increased relatively, the loading range that more can proper system really operates.And be 100% o'clock in load, further may look hardware capabilities and the overclocking of allowing x%, so not only power saving more of the present invention, can also bring into play the usefulness of hardware more completely.
In sum, the invention provides a South Bridge chip group 124 with polygon band signal lead-in wire control-management system voltage and frequency, collocation north bridge chipset 118 perfect system intraware monitoring mechanisms, exempt the inconvenience that software monitoring and control hardware bring, make the usefulness of system perform to maximum, it is minimum that energy resource consumption is then reduced to.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (10)
1. real-time method for managing power supply comprises the following step:
Utilization rate by the running of one first chip detecting system;
According to this utilization rate and a flow coding schedule, produce a corresponding control signal by one second chip; And
According to this control signal and a control parameter list, dynamically adjust the running parameter of an internal system assembly by one group of sideband signals lead-in wire;
Wherein, this group sideband signals lead-in wire be connected in this second chip, in order to not by soft communication agreement, directly transmit this control signal apace.
2. real-time method for managing power supply as claimed in claim 1, wherein, produce the step of this control signal, comprise a grade of load of judging this utilization rate by this first chip, and contrast this grade of load and this flow coding schedule by this second chip, obtain this control signal.
3. real-time method for managing power supply as claimed in claim 1, wherein, this flow coding schedule is to set according to the kenel and the characteristic of system in advance, in order to define a plurality of grades of load.
4. real-time method for managing power supply as claimed in claim 3, wherein, this control parameter list is a Control of Voltage parameter list that is set by software by a communication protocol, in order to define the Control of Voltage parameter of corresponding each grade of load.
5. real-time method for managing power supply as claimed in claim 3, wherein, this control parameter list is a frequency control parameter list that is set by software by a communication protocol, in order to define the frequency control parameter of corresponding each grade of load.
6. real-time method for managing power supply as claimed in claim 1, wherein, this internal system assembly be central processing unit, internal memory or draw quicken port one of them, and this first chip is a north bridge chips, this second chip is a South Bridge chip.
7. a real-time power-supply management system is used for the power consumption of quick adjustment computer system, comprises following assembly:
One first chip in order to the detection system operating state, produces a load information;
One second chip in order to according to this load information, produces a control signal;
One System Management Bus is in order to transmit power management command by soft communication agreement;
One controller is in order to receive this control signal, to regulate the running parameter of an internal system assembly; And
Polygon band signal lead-in wire is connected between this second chip and this controller, in order to not by soft communication agreement, transmits this control signal in real time.
8. real-time power-supply management system as claimed in claim 7, wherein:
This first chip is a north bridge chips, and this second chip is a South Bridge chip, and this System Management Bus is the communication protocol transmission power management command according to stepping power management interface; And
This second chip further comprises kenel and the predefined flow coding schedule of characteristic according to present system.
9. real-time power-supply management system as claimed in claim 7, wherein:
This controller is a voltage controller, comprises a Control of Voltage parameter list, in order to according to this control signal, regulates the voltage of this internal system assembly; And
This Control of Voltage parameter list is preestablished by this System Management Bus by software.
10. real-time power-supply management system as claimed in claim 7, wherein:
This controller is a frequency controller, comprises a frequency control parameter list, in order to according to this control signal, regulates the frequency of this internal system assembly; And
This frequency control parameter list is preestablished by this System Management Bus by software.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200410055974 CN1261846C (en) | 2004-08-03 | 2004-08-03 | Real time power managing method and its system |
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| CN 200410055974 CN1261846C (en) | 2004-08-03 | 2004-08-03 | Real time power managing method and its system |
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| CN1588272A true CN1588272A (en) | 2005-03-02 |
| CN1261846C CN1261846C (en) | 2006-06-28 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100478843C (en) * | 2006-06-13 | 2009-04-15 | 威盛电子股份有限公司 | Method and chip set for reducing computer system power consumption under working condition |
| CN101237656B (en) * | 2008-03-10 | 2012-06-13 | 北京天碁科技有限公司 | Method for improving terminal service duration and terminal device using this method |
| CN105489216A (en) * | 2016-01-19 | 2016-04-13 | 百度在线网络技术（北京）有限公司 | Voice synthesis system optimization method and device |
-
2004
- 2004-08-03 CN CN 200410055974 patent/CN1261846C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100478843C (en) * | 2006-06-13 | 2009-04-15 | 威盛电子股份有限公司 | Method and chip set for reducing computer system power consumption under working condition |
| CN101237656B (en) * | 2008-03-10 | 2012-06-13 | 北京天碁科技有限公司 | Method for improving terminal service duration and terminal device using this method |
| CN105489216A (en) * | 2016-01-19 | 2016-04-13 | 百度在线网络技术（北京）有限公司 | Voice synthesis system optimization method and device |
| CN105489216B (en) * | 2016-01-19 | 2020-03-03 | 百度在线网络技术（北京）有限公司 | Method and device for optimizing speech synthesis system |
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| Publication number | Publication date |
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| CN1261846C (en) | 2006-06-28 |
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Granted publication date: 20060628 |