CN1581449A - Thin film transistor manufacturing method and its structure - Google Patents

Thin film transistor manufacturing method and its structure Download PDF

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CN1581449A
CN1581449A CN 03127436 CN03127436A CN1581449A CN 1581449 A CN1581449 A CN 1581449A CN 03127436 CN03127436 CN 03127436 CN 03127436 A CN03127436 A CN 03127436A CN 1581449 A CN1581449 A CN 1581449A
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grid
doped region
layer
heavily doped
polysilicon layer
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CN100395875C (en
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陈坤宏
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AU Optronics Corp
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AU Optronics Corp
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Abstract

The disclosed thin film transistor includes at least buffer layer on base plate, first polycrystalline silicon layer and second polycrystalline silicon layer on the said buffer layer. The first polycrystalline silicon layer possesses first gate region, light dope region and first heavy dope region. The second polycrystalline silicon layer possesses second gate region and second heavy dope region. First gate region is surrounded by light dope region and first heavy dope region. The second gate region is surrounded by second heavy dope region. Drain/source electrodes are located in first and second heavy dope regions. Grid oxide layer is on first polycrystalline silicon layer, second polycrystalline silicon layer and buffer layer. First grid layer and second grid layer are positioned on grid oxide layer.

Description

Method of manufacturing thin film transistor and structure thereof
Technical field
The present invention relates to a kind of formation method of manufacturing thin film transistor and structure thereof, more specifically, relate to a kind of formation and have lightly doped method of manufacturing thin film transistor and structure thereof.
Background technology
Low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) technology is to utilize excimer laser as thermal source, laser is through behind the projection system, the equally distributed laser beam of meeting produce power is incident upon on the glass substrate with amorphous silicon structures, behind the energy of the absorption of the amorphous silicon structures on glass substrate excimer laser, can be transformed into polysilicon structure, because of the entire process process all is to finish below 600 ℃, so, on general glass substrate.
Though the manufacturing of low-temperature polysilicon film is many more than the manufacturing complexity of amorphous silicon membrane, yet low-temperature polysilicon film has following multiple advantage:
1. owing to can improving electron mobility, the low temperature polycrystalline silicon technology reaches 200 (cm 2/ Vsec), therefore, help the miniaturization of thin-film transistor component, so, can improve the panel aperture opening ratio, make that display brightness increases, consumption rate reduces.
2. the low temperature manufacturing helps using glass substrate, so, can reduce production costs significantly.
3. the low temperature polycrystalline silicon technology makes the manufacturing of CMOS directly to carry out on glass substrate.
4. the low temperature polycrystalline silicon technology makes the part drive circuit can be produced on the glass substrate, and therefore, the circuit on the printed circuit board (PCB) is simple relatively, so can save the area of printed circuit board (PCB), increases the module integration density.
So the LCD of utilizing low-temperature polysilicon film to form occupy the status that becomes more and more important.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of formation method of manufacturing thin film transistor and structure thereof.
Thin-film transistor of the present invention comprises first transistor npn npn and second transistor npn npn that is positioned on the substrate, wherein first transistor npn npn has first grid zone, lightly doped region and first heavily doped region, second transistor npn npn has the second grid zone and second heavily doped region, the first grid region exterior is in regular turn around the lightly doped region and first heavily doped region, and the second grid region exterior centers on second heavily doped region, and this method comprises at least:
Form resilient coating to substrate;
Form first polysilicon layer and second polysilicon layer to resilient coating, wherein first polysilicon layer and second polysilicon layer are corresponding to first transistor npn npn and second transistor npn npn;
Form first and be heavily doped in first heavily doped region, it utilizes the photoresist that hides first grid zone, lightly doped region and second polysilicon layer is shielding, and injects the first heavily doped impurity and form;
The deposition grid oxic horizon is on first polysilicon layer, second polysilicon layer and substrate; Form light dope in lightly doped region, it utilizes the photoresist that hides first grid zone and second polysilicon layer is to shield, and injects the first light dope matter and form;
Form second and be heavily doped in second heavily doped region, it utilizes the photoresist that hides first polysilicon layer and second grid zone is shielding, and injects the second heavily doped impurity and form;
Activate first heavy doping, light dope, second heavy doping, wherein, the direction of irradiate light is parallel with the direction of injecting ion; And
Form first grid and second grid to grid oxic horizon, and lay respectively at the top of first polysilicon layer and second polysilicon layer.
The method of formation thin-film transistor of the present invention also comprises:
Formation has the inner layer dielectric layer of pattern on grid oxic horizon, first grid and second grid, and the inner layer dielectric layer with pattern optionally exposes first heavy doping, second heavy doping, first grid and second grid;
Form electrode to be electrically connected first heavy doping, second heavy doping, first grid and the second grid that is exposed;
Formation has the protective layer of pattern on inner layer dielectric layer and electrode, and the protective layer with pattern exposes the partial electrode of first transistor npn npn that is positioned at pixel region;
Formation has the flatness layer of pattern on inner layer dielectric layer, and the flatness layer with pattern has identical pattern with the protective layer with pattern; And
Form the partial electrode that transparency electrode is exposed with the quilt that is electrically connected first transistor npn npn.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1～11 have shown the making flow process of low-temperature polysilicon film transistor of the present invention.
Embodiment
The invention provides a kind of manufacture method and structure thereof that forms low-temperature polysilicon film transistor.
At first, please refer to Fig. 1, resilient coating 102, polysilicon layer 104, be formed in regular turn on the substrate 100, then, form photoresist (not being shown among the figure) again with pattern, and be that etching is carried out in shielding with the photoresist, thereby form polysilicon layer 104 as shown in Figure 1.
Substrate 100 among the present invention can be glass or plastic material, and the thickness of polysilicon layer 104 is about 200～1000 dusts, and it is to utilize excimer laser, by carrying out the crystallization tempering and form being formed on amorphous silicon layer on the resilient coating 102.The polysilicon layer 104 of left is in order to forming the nmos pass transistor in the CMOS transistor, and middle polysilicon layer 104 is in order to forming the PMOS transistor in the CMOS transistor, and the most right-hand polysilicon layer 104 is in order to form the nmos pass transistor in the pixel region.
Resilient coating 102 can be made of silica or silicon nitride, and it is as heat insulation layer, also promptly accepts in the drawing process of irradiation of excimer laser at polysilicon layer 104, and resilient coating 102 can make the temperature of substrate 100, the unlikely De Taigao of liter and produce distortion.
Then, in Fig. 2,, form photoresist 105 and arrive on the substrate 100 with pattern by photoetching process, photoresist 105 covers desire fully and forms the transistorized PMOS transistor area of CMOS, and desire forms the area of grid and the lightly doped region of nmos transistor region.And be shielding with photoresist 105, substrate 100 is injected the phosphorus impurities of heavy concentration, its dosage is about 1 * 10 19/ cm 3To 1 * 10 22/ cm 3Between, to form source/ drain 104a, 104b, 104c and 104d in nmos pass transistor.
Then, with reference to figure 3, remove residual photoresist 105, and grid oxic horizon 106 is formed on resilient coating 102 and the polysilicon layer 104, the thickness of grid oxic horizon 106 is about between 500～1500 dusts, and its material can be silicon dioxide.Then, utilize photoetching process, the photoresist 107 that formation has pattern is to grid oxic horizon 106, and photoresist 107 covers desire fully and forms the transistorized PMOS transistor area of CMOS, and desire forms the area of grid of nmos transistor region.And be shielding with photoresist 107, substrate 100 is injected the phosphorus impurities of light concentration, its dosage is about 1 * 10 19/ cm 3To 1 * 10 22/ cm 3Between, to form light dope 104m, 104n, 104x and 104y in nmos pass transistor.
Then, in Fig. 4, remove residual photoresist 107, and pass through photoetching process once more, formation has the photoresist 109 of pattern to grid oxic horizon 106, and photoresist 109 covers whole nmos transistor region, and the transistorized area of grid of PMOS.And be shielding with photoresist 109, substrate 100 is injected the boron impurity of heavy concentration, its dosage is about 1 * 10 16/ cm 3To 1 * 10 19/ cm 3Between, to form transistorized source/drain 104i of PMOS and 104j.
Obviously, embodiments of the invention are not limited to form has lightly doped nmos pass transistor, formation has lightly doped PMOS transistor also can be as an alternative embodiment of the invention, at this moment, the implantation step that utilizes photoresist 105 and photoresist 107 to be carried out for shielding, inject the boron impurity of heavy concentration and light concentration respectively, the implantation step that utilizes photoresist 109 to be carried out for shielding injects the phosphorus impurities that weighs concentration.
Yet the lattice of polysilicon layer 104 is destroyed in injection process, and lattice is rearranged containing under the situation of impurity, therefore doping so that activation is injected into, utilizes excimer laser irradiation, make lattice and impurity finish the process that rearranges, as shown in Figure 5.This activation process of the present invention owing to carried out before forming grid, therefore, can make the degree of activation enough, and need not shine simultaneously from the front and back of substrate 100 only from the front direct irradiation laser of substrate 100.
Then, please refer to Fig. 6, depositing conducting layer and utilizes photoetching and etching technics to grid oxic horizon 106, forms grid layer 108, and grid layer 108 can be made up of with titanium/aluminium/titanium (Ti/Al/Ti) molybdenum (Mo), chromium (Cr).
Then, in Fig. 7, form inner layer dielectric layer 110 on whole base plate 100, and utilize photoetching and etching technics, in inner layer dielectric layer 110 and grid oxic horizon 106, form several openings, these openings can expose wherein several of grid 108 and source/ drain 104a, 104b, 104c, 104d, 104i and 104j.What present embodiment was shown is that opening all is positioned at the situation on source/ drain 104a, 104b, 104c, 104d, 104i and the 104j.
Then, in Fig. 8, form conductive layer to inner layer dielectric layer 110, and fill up the opening that is positioned among inner layer dielectric layer 110 and the grid oxic horizon 106, utilize photoetching and etching technics again, the electrode 112 that formation can be electrically connected with source/ drain 104a, 104b, 104c, 104d, 104i and 104j.When the opening that is arranged in inner layer dielectric layer 110 and grid oxic horizon 106, when exposing grid 108 simultaneously, then electrode 112 also is electrically connected with grid 108.
Then, in Fig. 9, form protective layer 114 on electrode 112 and inner layer dielectric layer 110, and utilize photoetching and etching technics, form opening in the protective layer 114 of pixel region, this opening exposes the electrode 112 of pixel region.In Figure 10, form flatness layer 116 to protective layer 114, and fill up the opening in the protective layer 114, utilize photoetching and etching technics again, in the flatness layer 116 of pixel region and protective layer 114, form opening, flatness layer 116 is in order to prevent that stray capacitance from producing.It should be noted that the patterning protective layer 114 and the mask of flatness layer 116 are same mask.
At last; in Figure 11; the conductive layer that formation is made up of indium tin oxide (ITO) is to flatness layer 116; and fill up opening in protective layer 114 and the flatness layer 116; utilize photoetching and etching technics again; the transparency electrode 118 that formation can be electrically connected with the electrode 112 of pixel region is to finish the manufacturing with low-temperature polysilicon film transistor.
The disclosed manufacture method of the above embodiment of the present invention only from the front direct irradiation laser of substrate 100, carrying out activated impurity, and has a light dope injection process, has lightly doped nmos pass transistor or PMOS transistor with formation.
In sum; though the present invention with a preferred embodiment openly as above; yet it is not to be used for limiting the present invention; any those of ordinary skill in the art; without departing from the spirit and scope of the present invention; should do various changes and retouching, so protection scope of the present invention should be with being as the criterion that claims were defined.

Claims (20)

1. method that on substrate, forms first transistor npn npn and second transistor npn npn, wherein first transistor npn npn has first grid zone, lightly doped region and first heavily doped region, second transistor npn npn has the second grid zone and second heavily doped region, the first grid region exterior is in regular turn around the lightly doped region and first heavily doped region, and the second grid region exterior centers on second heavily doped region, and this method comprises at least:
Form first polysilicon layer and second polysilicon layer to this substrate, wherein first polysilicon layer and second polysilicon layer are corresponding to first transistor npn npn and second transistor npn npn;
Form first and be heavily doped in first heavily doped region, it utilizes the photoresist that hides first grid zone, lightly doped region and second polysilicon layer to be shielding, and forms by injecting the first heavily doped impurity;
The deposition grid oxic horizon is on first polysilicon layer, second polysilicon layer and substrate;
Form light dope in this lightly doped region, wherein utilize the photoresist that hides the first grid zone and second polysilicon layer to be shielding, and form by injecting the first light dope matter;
Form second and be heavily doped in this second heavily doped region, wherein utilize the photoresist that hides first polysilicon layer and second grid zone to be shielding, and form by injecting the second heavily doped impurity;
Activate first heavy doping, light dope and second heavy doping, wherein, the direction of irradiate light is parallel with the direction of injecting ion; And
Form first grid and second grid to grid oxic horizon, and lay respectively at the top of first polysilicon layer and second polysilicon layer.
2. the method for claim 1 is characterized in that, before forming first polysilicon layer and the second polysilicon layer step, also comprises forming the step of resilient coating to the substrate.
3. the method for claim 1 is characterized in that, after forming first grid and the second grid step to the grid oxic horizon, also comprises:
Formation has the inner layer dielectric layer of pattern on grid oxic horizon, first grid and second grid, and the inner layer dielectric layer with pattern optionally exposes first heavy doping, second heavy doping, first grid and second grid; And
Form electrode to be electrically connected first heavy doping, second heavy doping, first grid and the second grid that is exposed.
4. method as claimed in claim 3 is characterized in that, after the step that forms electrode, also comprises:
Formation has the protective layer of pattern on inner layer dielectric layer and electrode, and the protective layer with pattern exposes the partial electrode of first transistor npn npn that is positioned at pixel region; And
Form the partial electrode that transparency electrode is exposed with the quilt that is electrically connected first transistor npn npn.
5. method as claimed in claim 4 is characterized in that, before the step that forms transparency electrode, also comprises:
Formation has the flatness layer of pattern to inner layer dielectric layer, and the flatness layer with pattern has identical pattern with the protective layer with pattern.
6. thin-film transistor that is positioned on the substrate, this thin-film transistor comprises at least:
Resilient coating is positioned on the substrate;
First polysilicon layer and second polysilicon layer, be positioned on the resilient coating, wherein first polysilicon layer has first grid zone, lightly doped region and first heavily doped region, second polysilicon layer has the second grid zone and second heavily doped region, the first grid region exterior is in regular turn around the lightly doped region and first heavily doped region, and the second grid region exterior is around second heavily doped region;
Drain/source is arranged in first heavily doped region and second heavily doped region;
Light dope is arranged in lightly doped region;
Grid oxic horizon is positioned on first polysilicon layer, second polysilicon layer and the resilient coating;
First grid and second grid are positioned on the grid oxic horizon, and lay respectively at the top in first grid zone and second grid zone.
7. thin-film transistor as claimed in claim 6 is characterized in that, the thickness of second polysilicon layer of first polysilicon layer is about 200～1000 dusts.
8. thin-film transistor as claimed in claim 6 is characterized in that the thickness of grid oxic horizon is about 500～1500 dusts.
9. thin-film transistor as claimed in claim 6 is characterized in that, first grid and second grid are made up of one of them of molybdenum, chromium or titanium/aluminium/titanium.
10. thin-film transistor as claimed in claim 6 is characterized in that the drain/source of first heavily doped region contains phosphorus impurities, the drain/source boron-containing impurities of second heavily doped region.
11. thin-film transistor as claimed in claim 6 is characterized in that, the drain of first heavily doped region has boron impurity, and the drain of second heavily doped region has phosphorus impurities.
12. thin-film transistor as claimed in claim 6 is characterized in that, the drain/source of first heavily doped region contains 1 * 10 19/ cm 3To 1 * 10 22/ cm 3Between impurity.
13. thin-film transistor as claimed in claim 6 is characterized in that, the drain/source of second heavily doped region contains 1 * 10 19/ cm 3To 1 * 10 22/ cm 3Between impurity.
14. thin-film transistor as claimed in claim 6 is characterized in that light dope contains 1 * 10 16/ cm 3To 1 * 10 19/ cm 3Between impurity.
15. thin-film transistor as claimed in claim 6 also comprises:
Inner layer dielectric layer is positioned on first grid, second grid and the grid oxic horizon; And
A plurality of electrodes, it runs through grid oxic horizon and inner layer dielectric layer, and is electrically connected with first grid, second grid and drain/source.
16. thin-film transistor as claimed in claim 15 is characterized in that, the thickness of inner layer dielectric layer is about 2000～7000 dusts.
17. thin-film transistor as claimed in claim 15 is characterized in that, electrode is made up of one of them of molybdenum, chromium or titanium/aluminium/titanium.
18. thin-film transistor as claimed in claim 15 also comprises:
Protective layer is positioned on inner layer dielectric layer and the electrode; And
Transparency electrode is positioned on the protective layer of pixel region, and runs through protective layer and be electrically connected with electrode.
19. thin-film transistor as claimed in claim 18 is characterized in that transparency electrode is made up of indium tin oxide.
20. thin-film transistor as claimed in claim 18 also comprises:
Flatness layer, it is between protective layer and transparency electrode.
CNB031274366A 2003-08-07 2003-08-07 Thin film transistor manufacturing method and its structure Expired - Lifetime CN100395875C (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100446274C (en) * 2005-07-07 2008-12-24 友达光电股份有限公司 Switching element of pixel electrode, and manufacturing method
CN100454562C (en) * 2007-09-29 2009-01-21 昆山龙腾光电有限公司 Thin-film transistor array substrates, manufacturing method and LCD device containing the same
CN105304569A (en) * 2015-09-24 2016-02-03 武汉华星光电技术有限公司 Manufacturing method of CMOS transistor and LTPS array substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100815894B1 (en) * 2001-09-21 2008-03-21 엘지.필립스 엘시디 주식회사 Method of fabricating CMOS Poly Silicon TFT having LDD structure
CN1182586C (en) * 2002-06-13 2004-12-29 统宝光电股份有限公司 Low-temperature polysilicon film transistor with slightly doped drain structure and its making process

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100446274C (en) * 2005-07-07 2008-12-24 友达光电股份有限公司 Switching element of pixel electrode, and manufacturing method
CN100454562C (en) * 2007-09-29 2009-01-21 昆山龙腾光电有限公司 Thin-film transistor array substrates, manufacturing method and LCD device containing the same
CN105304569A (en) * 2015-09-24 2016-02-03 武汉华星光电技术有限公司 Manufacturing method of CMOS transistor and LTPS array substrate
CN105304569B (en) * 2015-09-24 2018-05-11 武汉华星光电技术有限公司 A kind of production method of CMOS transistor and LTPS array base paltes

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