CN100446274C - Switching element of pixel electrode, and manufacturing method - Google Patents
Switching element of pixel electrode, and manufacturing method Download PDFInfo
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- CN100446274C CN100446274C CNB2005100832263A CN200510083226A CN100446274C CN 100446274 C CN100446274 C CN 100446274C CN B2005100832263 A CNB2005100832263 A CN B2005100832263A CN 200510083226 A CN200510083226 A CN 200510083226A CN 100446274 C CN100446274 C CN 100446274C
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Abstract
The present invention provides a picture-element electrode switch element and a manufacturing method thereof. The picture-element electrode switch element is suitable for a display. The manufacturing method comprises the following steps: firstly, a grid is formed above a base plate; then, a grid insulation layer is formed above the grid, and a buffer layer is also formed between the grid and the base plate and / or is positioned between the grid and the grid insulation layer, wherein the buffer layer comprises tantalum silicide, nitrogen tantalum silicide, titanium silicide, nitrogen titanium silicide, tungsten silicide, nitrogen tungsten silicide or nitrogen tungsten carbide; finally, a semiconductor layer is formed above the gird insulation layer, and a source and a drain are formed above a part of the semiconductor layer, wherein the grid is covered by the buffer layer.
Description
Technical field
The present invention relates to a kind of switch element of thin-film transistor, particularly relate to a kind of switch element and manufacture method thereof of pixel electrode.
Background technology
Bottom gate polar form (bottom-gate type) thin-film transistor element has been widely used in the Thin Film Transistor-LCD (TFT-LCD), as the switch element of pixel electrode at present.See also Fig. 1, it shows traditional bottom gate polar form thin-film transistor structure 100.This thin-film transistor structure 100 comprises a substrate 110, a grid 120, a gate insulator 130, a channel layer (channellayer) 140, an ohmic contact layer 150 and one source/drain electrode layer 160/170.
Along with the size increase of TFT-LCD, the metal gate polar curve (metalgate line) that comprises the film crystal tube grid just must meet low-resistance requirement.Because the copper and copper alloy material has quite low resistance, so be intended for the optimal selection of grid material.Yet the tack between copper product and the glass substrate (adhesion) is not good, and copper also can be diffused in the insulating barrier (for example SiO2 layer), and influences the element quality.Person more, because copper product easy deformation, so (for example be plasma enhanced chemical vapor deposition particularly at the plasma process that carries out the film deposition, PECVD) in, copper product can and plasma process in gas reaction and cause copper product rough surface (roughness) and harmful effects such as increase resistance etc.
In No. the 6562668th, United States Patent (USP), people such as Jang have a kind of thin-film transistor structure of announcement.This method is the adhesion layer (adhesion layer) that adopts aluminium oxide or aluminium nitride to be used as to be between copper grid and the glass substrate, and the cap rock of copper grid.
Summary of the invention
In view of this, one of main purpose of the present invention is exactly the adhesive force of promoting between substrate and grid.
Another object of the present invention just provides a kind of diffusion problem that prevents metal gates.
For reaching above-mentioned purpose, the method for one embodiment of the present invention mainly comprises the following steps.
At first, form a grid in substrate top.Afterwards, form a gate insulator in above-mentioned grid top.
Wherein, also comprise form a resilient coating between above-mentioned grid and the aforesaid substrate with and/or between above-mentioned grid and above-mentioned gate insulator.Wherein, above-mentioned resilient coating comprises tantalum silicide (TaSi
x), nitrogen tantalum silicide (TaSi
xN
y), titanium silicide (TiSi
x), nitrogen titanium silicide (TiSi
xN
y), tungsten silicide (WSi
x), nitrogen tungsten silicide (WSi
xN
y) or nitrogen tungsten carbide (WC
xN
y), and above-mentioned resilient coating is as diffused barrier layer.Wherein, above-mentioned grid is covered by above-mentioned resilient coating.
Then, form semi-conductor layer, and form a source/drain in the above-mentioned semiconductor layer of part top in above-mentioned gate insulator top.Afterwards, form a pixel electrode, be electrically connected on this source electrode or drain electrode.
The method of another preferred embodiment of the present invention mainly comprises the following steps.
At first, form a grid in substrate top.Afterwards, form a gate insulator in above-mentioned grid top.
Wherein, also comprise form first resilient coating between above-mentioned grid and the aforesaid substrate with and/or between above-mentioned grid and above-mentioned gate insulator.Wherein, above-mentioned first resilient coating comprises tantalum silicide (TaSi
x), nitrogen tantalum silicide (TaSi
xN
y), titanium silicide (TiSi
x), nitrogen titanium silicide (TiSi
xN
y), tungsten silicide (WSi
x), nitrogen tungsten silicide (WSi
xN
y) or nitrogen tungsten carbide (WC
xN
y), and above-mentioned first resilient coating is as diffused barrier layer.And above-mentioned grid is covered by above-mentioned first resilient coating.
Then, form semi-conductor layer, and form a source/drain in the above-mentioned semiconductor layer of part top in above-mentioned gate insulator top.Afterwards, form a pixel electrode, be electrically connected on this source electrode or drain electrode.
Wherein, comprise that more formation second resilient coating is between above-mentioned semiconductor layer and above-mentioned source/drain electrode.Wherein, above-mentioned second resilient coating comprises tantalum silicide (TaSi
x), nitrogen tantalum silicide (TaSi
xN
y), titanium silicide (TiSi
x), nitrogen titanium silicide (TiSi
xN
y), tungsten silicide (WSi
x), nitrogen tungsten silicide (WSi
xN
y) or nitrogen tungsten carbide (WC
xN
y), and above-mentioned second resilient coating is as diffused barrier layer.
The present invention is with materials such as tantalum silicide, nitrogen tantalum silicide, titanium silicide, nitrogen titanium silicide, tungsten silicide, nitrogen tungsten silicide or nitrogen tungsten carbides, as adhesive force promoting layer or diffused barrier layer, can promote the adhesive force between substrate and grid or prevent the diffusion problem of metal gates.
The present invention can also be applied on top grid type (top-gate type) thin-film transistor element except can being applied in bottom gate polar form (bottom-gate type).
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Fig. 1 is the generalized section of existing thin-film transistor structure.
Fig. 2 A-2D is the technology generalized section according to the thin-film transistor structure of first embodiment of the invention.
Fig. 3 A-3D is the generalized section according to the thin-film transistor structure of second embodiment of the invention.
Fig. 4 A-4E is the generalized section according to the thin-film transistor structure of third embodiment of the invention.
The simple symbol explanation
100,200,300,400～thin-film transistor structure; 110,210,310,410～substrate; 120,220,320,420～grid; 130,230,330,430～gate insulator; 140,240,340,440～channel layer; 150,250,350,450～ohmic contact layer; 160,260,360,460～source electrode; 170,270,370,470～drain electrode; 215,415～material layer; 215 ', 415 '～adhere to promoting layer; 217,417～metal level; 325,425～diffused barrier layer.
Embodiment
First embodiment
According to one embodiment of the present invention, the method comprises following key step.
Shown in Fig. 2 A, use sputtering method to form material layer 215 on substrate 210.Wherein, this material layer 215 comprises tantalum silicide, nitrogen tantalum silicide, titanium silicide, nitrogen titanium silicide, tungsten silicide, nitrogen tungsten silicide, and thickness is approximately between 5 and 200 nanometers.This substrate 210 comprises glass substrate or plastic base.
In other embodiments, can use atomic layer deposition method (Atomic-Layer Deposition) to form material layer 215 on substrate 210.Wherein, this material layer 215 comprises the nitrogen tungsten carbide, and thickness is approximately between 5 and 200 nanometers.Then, use chemical vapour deposition technique, electrochemistry to electroplate (electrochemical plating; ECP) or sputtering method (sputter deposition) form metal level 217 on this material layer 215.
Shown in Fig. 2 B, carry out a photoengraving carving technology, adhere to promoting layer 215 ' and grid 220 in substrate 210 tops and form.This grid 220 comprises the alloy of copper, aluminium, silver or above-mentioned metal, and thickness is approximately between 100 and 500 nanometers.
Shown in Fig. 2 C, first compliance ground forms gate insulator 230 in these grid 220 tops.Then, form the semiconductor layer (not shown) on this gate insulator 230.Wherein, the formation method of this gate insulator 230 comprises chemical vapour deposition technique, plasma enhanced chemical vapor deposition method, physical vaporous deposition or sputtering method.This gate insulator 230 comprise silicon compound, the carbon containing class of silicon compound, the carbon containing hydrogen-oxygen class of silica, silicon nitride, silicon oxynitride, tantalum oxide, aluminium oxide, carbon containing oxygen class silicon compound, fluorinated carbon compound or be the star topology compound at center with silicon or carbon, and the thickness of this gate insulator 230 is approximately between 50 and 500 nanometers.
And this semiconductor layer for example comprises amorphous silicon layer (amorphous silicon layer) and the silicon layer (impurity-doped silicon layer) through mixing that deposits via chemical vapour deposition technique.Afterwards, form channel layer 240 and ohmic contact layer 250 by traditional above-mentioned semiconductor layer of photoetching process patterning.Wherein, this ohmic contact layer 250 for example is the silicon layer of Doped n-type ion (for example P or As) or the silicon layer of doped p type ion (for example B), and thickness is approximately between 10 and 100 nanometers.This channel layer 240 then is unadulterated amorphous silicon layer, and thickness is approximately between 50 and 200 nanometers.
Shown in Fig. 2 D, use chemical vapour deposition technique, electrochemistry galvanoplastic (electrochemicalplating; ECP) or sputtering method (sputter deposition) form a metal level (not shown) on this ohmic contact layer 250, then optionally this metal level of etching therewith ohmic contact layer 250 to the part surface that exposes this channel layer 240, forming source/drain electrode 260/270 of forming by metal above this semiconductor layer, and can obtain thin-film transistor structure 200.Afterwards, form pixel electrode (figure does not show), be electrically connected on this source electrode 260 or drain 270.This thin-film transistor structure 200 promptly becomes the switch element of pixel electrode.This source/drain electrode 260/270 comprises the alloy of copper, aluminium, silver or above-mentioned metal, and thickness is approximately between 100 and 500 nanometers.
Second embodiment
According to one embodiment of the present invention, the method comprises following key step.
As shown in Figure 3A, use chemical vapour deposition technique, electrochemistry galvanoplastic (electrochemicalplating; ECP) or sputtering method (sputter deposition) form a metal level (not shown) on a substrate 310.Then, carry out the photoengraving carving technology, and form grid 320 in substrate 310 tops.This substrate 310 comprises glass substrate or plastic base.This grid 320 comprises the alloy of copper, aluminium, silver or above-mentioned metal, and thickness is approximately between 100 and 500 nanometers.
Shown in Fig. 3 B, use sputtering method, compliance ground forms diffused barrier layer 325 on this grid 320.Wherein, this diffused barrier layer 325 comprises tantalum silicide, nitrogen tantalum silicide, titanium silicide, nitrogen titanium silicide, tungsten silicide or nitrogen tungsten silicide, and thickness is approximately between 5 and 200 nanometers.
In other embodiments, can use atomic layer deposition method (Atomic-Layer Deposition), compliance ground forms diffused barrier layer 325 on substrate 310.Wherein, this diffused barrier layer 325 comprises the nitrogen tungsten carbide, and thickness is approximately between 5 and 200 nanometers.
Shown in Fig. 3 C, compliance ground forms gate insulator 330 in these diffused barrier layer 325 tops.Then, form the semiconductor layer (not shown) on this gate insulator 330.Wherein, the formation method of this gate insulator 330 comprises chemical vapour deposition technique, plasma enhanced chemical vapor deposition method, physical vaporous deposition or sputtering method.This gate insulator 330 comprise silicon compound, the carbon containing class of silicon compound, the carbon containing hydrogen-oxygen class of silica, silicon nitride, silicon oxynitride, tantalum oxide, aluminium oxide, carbon containing oxygen class silicon compound, fluorinated carbon compound or be the star topology compound at center with silicon or carbon, and thickness is approximately between 50 and 500 nanometers.
And this semiconductor layer for example comprises amorphous silicon layer (amorphous silicon layer) and the silicon layer (impurity-doped silicon layer) through mixing that deposits via chemical vapour deposition technique.Afterwards, form channel layer 340 and ohmic contact layer 350 by traditional above-mentioned semiconductor layer of photoetching process patterning.Wherein, this ohmic contact layer 350 for example is the silicon layer of Doped n-type ion (for example P or As) or the silicon layer of doped p type ion (for example B), and thickness is approximately between 10 and 100 nanometers.This channel layer 340 then is unadulterated amorphous silicon layer, and thickness is approximately between 50 and 200 nanometers.
Shown in Fig. 3 D, use chemical vapour deposition technique, electrochemistry galvanoplastic (electrochemicalplating; ECP) or sputtering method (sputter deposition) form the metal level (not shown) on this ohmic contact layer 350, then optionally this metal level of etching therewith ohmic contact layer 350 to the part surface that exposes this channel layer 340, forming source/drain electrode 360/370 of forming by metal above this semiconductor layer, and can obtain thin-film transistor structure 300.Afterwards, form pixel electrode (figure does not show), be electrically connected on this source electrode 360 or drain 370.This thin-film transistor structure 300 promptly becomes the switch element of pixel electrode.This source/drain electrode 360/370 comprises the alloy of copper, aluminium, silver or above-mentioned metal, and thickness is approximately between 100 and 500 nanometers.
The 3rd embodiment
According to one embodiment of the present invention, the method comprises following key step.
Shown in Fig. 4 A, use sputtering method to form material layer 415 on substrate 410.Wherein, this material layer 415 comprises tantalum silicide, nitrogen tantalum silicide, titanium silicide, nitrogen titanium silicide, tungsten silicide or nitrogen tungsten silicide, and thickness is approximately between 5 and 200 nanometers.This substrate 410 comprises glass substrate or plastic base.
In other embodiments, can use atomic layer deposition method (Atomic-Layer Deposition) to form material layer 415 on grid 420.Wherein, this material layer 415 comprises the nitrogen tungsten carbide, and thickness is approximately between 5 and 200 nanometers.
Then, use chemical vapour deposition technique, electrochemistry galvanoplastic (electrochemical plating; ECP) or sputtering method (sputter deposition) form metal level 417 on this material layer 215.
Shown in Fig. 4 B, carry out the photoengraving carving technology, adhere to promoting layer 415 ' and grid 420 in substrate 410 tops and form.This grid 420 comprises the alloy of copper, aluminium, silver or above-mentioned metal, and thickness is approximately between 100 and 500 nanometers.
Shown in Fig. 4 C, use sputtering method, compliance ground forms diffused barrier layer 425 on this grid 420.Wherein, this diffused barrier layer 425 comprises tantalum silicide, nitrogen tantalum silicide, titanium silicide, nitrogen titanium silicide, tungsten silicide or nitrogen tungsten silicide, and thickness is approximately between 5 and 200 nanometers.
In other embodiments, can use atomic layer deposition method (Atomic-Layer Deposition), compliance ground forms diffused barrier layer 425 on grid 420.Wherein, this diffused barrier layer 425 comprises the nitrogen tungsten carbide, and thickness is approximately between 5 and 200 nanometers.
Shown in Fig. 4 D, first compliance ground forms gate insulator 430 in these diffused barrier layer 425 tops.Then, form the semiconductor layer (not shown) on this gate insulator 430.Wherein, the formation method of this gate insulator 430 comprises chemical vapour deposition technique, plasma enhanced chemical vapor deposition method, physical vaporous deposition or sputtering method.This gate insulator 430 comprise silicon compound, the carbon containing class of silicon compound, the carbon containing hydrogen-oxygen class of silica, silicon nitride, silicon oxynitride, tantalum oxide, aluminium oxide, carbon containing oxygen class silicon compound, fluorinated carbon compound or be the star topology compound at center with silicon or carbon, and thickness is approximately between 50 and 500 nanometers.
And this semiconductor layer for example comprises amorphous silicon layer (amorphous silicon layer) and the silicon layer (impurity-doped silicon layer) through mixing that deposits via chemical vapour deposition technique.Afterwards, form channel layer 440 and ohmic contact layer 450 by traditional above-mentioned semiconductor layer of photoetching process patterning.Wherein, this ohmic contact layer 450 for example is the silicon layer of Doped n-type ion (for example P or As) or the silicon layer of doped p type ion (for example B), and thickness is approximately between 10 and 100 nanometers.This channel layer 440 then is unadulterated amorphous silicon layer, and thickness is approximately between 50 and 200 nanometers.
Shown in Fig. 4 E, use chemical vapour deposition technique, electrochemistry galvanoplastic (electrochemicalplating; ECP) or sputtering method (sputter deposition) form the metal level (not shown) on this ohmic contact layer 450, then optionally this metal level of etching therewith ohmic contact layer 450 to the part surface that exposes this channel layer 440, forming source/drain electrode 460/470 of forming by metal above this semiconductor layer, and can obtain thin-film transistor structure 400.Afterwards, form pixel electrode (figure does not show), be electrically connected on this source electrode 460 or drain 470.This thin-film transistor structure 400 promptly becomes the switch element of pixel electrode.This source/drain electrode 460/470 comprises the alloy of copper, aluminium, silver or above-mentioned metal, and thickness is approximately between 100 and 500 nanometers.
Embodiments of the invention are with materials such as tantalum silicide, nitrogen tantalum silicide, titanium silicide, nitrogen titanium silicide, tungsten silicide, nitrogen tungsten silicide or nitrogen tungsten carbides, as adhesive force promoting layer or diffused barrier layer, can promote the adhesive force between substrate and grid or prevent the diffusion problem of metal gates.
Embodiments of the invention can also be applied on top grid type (top-gate type) thin-film transistor element except can being applied in bottom gate polar form (bottom-gate type).
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (18)
1, a kind of switch element of pixel electrode is applicable to flat-panel screens, comprising:
Grid is positioned at substrate top;
Gate insulator is positioned at this grid top;
First resilient coating, between this grid and this substrate with and/or between this grid and this gate insulator, wherein this first resilient coating comprises tantalum silicide, titanium silicide, tungsten silicide or nitrogen tungsten carbide;
Semiconductor layer is positioned at this gate insulator top; And
Source/drain electrode is positioned at this semiconductor layer top of part,
Wherein this grid comprises the alloy of copper, silver, aluminium or above-mentioned metal.
2, the switch element of pixel electrode as claimed in claim 1 also comprises:
Pixel electrode is electrically connected on this source electrode or drain electrode.
3, the switch element of pixel electrode as claimed in claim 1, wherein this grid is covered by this first resilient coating.
4, the switch element of pixel electrode as claimed in claim 1, wherein the thickness of this first resilient coating is between 5～200 nanometers.
5, the switch element of pixel electrode as claimed in claim 1 also comprises: second resilient coating, and between this semiconductor layer and this source/drain electrode.
6, the switch element of pixel electrode as claimed in claim 5, wherein this second resilient coating comprises tantalum silicide, nitrogen tantalum silicide, titanium silicide, nitrogen titanium silicide, tungsten silicide, nitrogen tungsten silicide or nitrogen tungsten carbide.
7, the switch element of pixel electrode as claimed in claim 5, wherein the thickness of this second resilient coating is between 5～200 nanometers.
8, the switch element of pixel electrode as claimed in claim 1, wherein this substrate comprises glass substrate or plastic base.
9, the switch element of pixel electrode as claimed in claim 1, wherein this gate insulator comprise silicon compound, the carbon containing class of silicon compound, the carbon containing hydrogen-oxygen class of silica, silicon nitride, silicon oxynitride, tantalum oxide, aluminium oxide, carbon containing oxygen class silicon compound, fluorinated carbon compound or be the star topology compound at center with silicon or carbon.
10, the switch element of pixel electrode as claimed in claim 1, wherein this source/drain electrode comprises the alloy of copper, silver, aluminium or above-mentioned metal.
11, a kind of manufacture method of switch element of pixel electrode comprises the following steps:
Form the substrate top of grid in part;
Form gate insulator in this grid top;
Form first resilient coating between this grid and this substrate with and/or between this grid and this gate insulator, wherein this first resilient coating comprises tantalum silicide, titanium silicide, tungsten silicide or nitrogen tungsten carbide;
Form semiconductor layer in this gate insulator top; And
Form source electrode and drain in this semiconductor layer top of part,
Wherein this grid comprises the alloy of copper, silver, aluminium or above-mentioned metal.
12, the manufacture method of the switch element of pixel electrode as claimed in claim 11 also comprises: form pixel electrode, be electrically connected on this source electrode or drain electrode.
13, the manufacture method of the switch element of pixel electrode as claimed in claim 11, wherein this grid is covered by this first resilient coating.
14, the manufacture method of the switch element of pixel electrode as claimed in claim 11 also comprises: form second resilient coating between this semiconductor layer and this source/drain electrode.
15, the manufacture method of the switch element of pixel electrode as claimed in claim 14, wherein this second resilient coating comprises tantalum silicide, nitrogen tantalum silicide, titanium silicide, nitrogen titanium silicide, tungsten silicide, nitrogen tungsten silicide or nitrogen tungsten carbide.
16, the manufacture method of the switch element of pixel electrode as claimed in claim 11, wherein this substrate comprises glass substrate or plastic base.
17, the manufacture method of the switch element of pixel electrode as claimed in claim 11, wherein gate insulator comprise silicon compound, the carbon containing class of silicon compound, the carbon containing hydrogen-oxygen class of silica, silicon nitride, silicon oxynitride, tantalum oxide, aluminium oxide, carbon containing oxygen class silicon compound, fluorinated carbon compound or be the star topology compound at center with silicon or carbon.
18, the manufacture method of the switch element of pixel electrode as claimed in claim 11, wherein this source electrode and drain electrode comprise the alloy of copper, silver, aluminium or above-mentioned metal.
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| CNB2005100832263A CN100446274C (en) | 2005-07-07 | 2005-07-07 | Switching element of pixel electrode, and manufacturing method |
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| CN100446274C true CN100446274C (en) | 2008-12-24 |
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| KR101832361B1 (en) * | 2011-01-19 | 2018-04-16 | 삼성디스플레이 주식회사 | Thin film transistor array panel |
| CN102955312B (en) * | 2012-11-14 | 2015-05-20 | 京东方科技集团股份有限公司 | Array substrate and manufacture method thereof and display device |
| CN103531640A (en) * | 2013-11-01 | 2014-01-22 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate, manufacturing method of array substrate and display device |
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| TWI537654B (en) * | 2014-07-25 | 2016-06-11 | China Steel Corp | Copper conductor structure and manufacturing method thereof |
| CN104716202A (en) | 2015-04-03 | 2015-06-17 | 京东方科技集团股份有限公司 | Thin-film transistor and preparation method thereof, array substrate and display device |
| CN107293517B (en) * | 2017-07-06 | 2020-06-02 | 京东方科技集团股份有限公司 | Substrate comprising conductive pattern, preparation method of substrate and display device |
| CN107887275B (en) * | 2017-11-03 | 2019-07-19 | 惠科股份有限公司 | The manufacturing method of low-temperature polysilicon film and transistor |
| CN110391233B (en) * | 2018-04-17 | 2022-10-14 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN110750011A (en) * | 2019-11-15 | 2020-02-04 | Tcl华星光电技术有限公司 | Display panel, preparation method and display device |
| CN110867411B (en) * | 2019-11-28 | 2022-07-19 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN115377208A (en) * | 2021-05-20 | 2022-11-22 | 合肥京东方显示技术有限公司 | Thin film transistor, manufacturing method thereof, array substrate, display panel and device |
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