CN100454562C - Thin-film transistor array substrates, manufacturing method and LCD device containing the same - Google Patents
Thin-film transistor array substrates, manufacturing method and LCD device containing the same Download PDFInfo
- Publication number
- CN100454562C CN100454562C CNB2007101623796A CN200710162379A CN100454562C CN 100454562 C CN100454562 C CN 100454562C CN B2007101623796 A CNB2007101623796 A CN B2007101623796A CN 200710162379 A CN200710162379 A CN 200710162379A CN 100454562 C CN100454562 C CN 100454562C
- Authority
- CN
- China
- Prior art keywords
- layer
- gate
- ion
- film transistor
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000010409 thin film Substances 0.000 title claims description 43
- 239000000758 substrate Substances 0.000 title claims description 40
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000009413 insulation Methods 0.000 claims abstract description 7
- 239000004973 liquid crystal related substance Substances 0.000 claims description 35
- 238000005468 ion implantation Methods 0.000 claims description 27
- 150000002500 ions Chemical class 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 17
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- -1 oxygen ion Chemical class 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 8
- 238000002347 injection Methods 0.000 abstract 2
- 239000007924 injection Substances 0.000 abstract 2
- 238000002161 passivation Methods 0.000 description 24
- 238000010586 diagram Methods 0.000 description 19
- 239000004065 semiconductor Substances 0.000 description 14
- 239000003990 capacitor Substances 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 11
- 239000011521 glass Substances 0.000 description 11
- 230000003071 parasitic effect Effects 0.000 description 11
- 238000003860 storage Methods 0.000 description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 230000008859 change Effects 0.000 description 6
- 239000013256 coordination polymer Substances 0.000 description 6
- 238000002834 transmittance Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910004205 SiNX Inorganic materials 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- SLXKOJJOQWFEFD-UHFFFAOYSA-N 6-aminohexanoic acid Chemical compound NCCCCCC(O)=O SLXKOJJOQWFEFD-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
This invention discloses an array base board of a film transistor including multiple signal lines, multiple grid lines crossly set with the signal lines, a pixel electrode and a film transistor, in which, a grid insulation layer set between the signal line layer and the grid line layer includes an ionic injection region injected by ionic elements. This invention also discloses a method for manufacturing array base boards of film transistors including: forming grid lines and signal lines, forming a grid insulation layer, forming a film transistor, and the source of which is connected with the pixel electrode electrically in the pixel region determined by intercrossing the grid lines and the signal lines and the drain of which is connected with the signal lines electrically, and part of the grid insulation layer are injected with ionic elements to form ionic injection regions, which can reduce dielectric constant of grid insulation layer so as to reduce feed-through voltage and DC bias and increase display effect of LC panels.
Description
Technical Field
The present invention relates to a thin film transistor, and more particularly, to a thin film transistor array substrate and a method of manufacturing the same.
Background
In general, a Liquid Crystal Display (LCD) includes two panels on which electrodes are respectively disposed and a Liquid Crystal layer disposed between the two panels. The transmittance of light is controlled by adjusting the voltage between two electrodes, also referred to as the liquid crystal voltage. In a normally white mode (normallywite: NW), the transmittance of light is inversely proportional to the liquid crystal voltage, i.e., the greater the value of the liquid crystal voltage, the lower the transmittance of light; the smaller the liquid crystal voltage value, the higher the light transmittance.
Generally, the voltage applied to the liquid crystal is the voltage difference between the common electrode line and the pixel electrode, when the Thin Film Transistor (TFT) is turned off, the pixel electrode is not connected to any voltage source and is in a Floating state, and if there is any voltage variation around the pixel electrode, the voltage variation will be coupled to the pixel electrode through a parasitic capacitance or a pixel storage capacitance, resulting in a change in the pixel voltage, so that the actual voltage applied to the liquid crystal deviates from a predetermined value. The voltage variation across the LCD panel is mainly derived from three aspects: the pixel voltage is influenced most by the change of the grid voltage, the change of the source voltage and the change of the voltage of the common electrode wire. The value of this voltage change is referred to as the Feed-through voltage (hereinafter V)FDTo represent the feed-through voltage), more specifically, the calculation formula (1) of the feed-through voltage can be expressed as follows:
wherein, CGSIs the capacitance between the gate and source of the TFT, CLCIs the capacitance value of liquid crystal, CSTStoring a capacitance value, Δ V, for a pixelGIs the difference between the gate voltages of the TFTs when turned on and off. Due to the feed-through voltage VFDIs the main factor for generating DC bias, so reducing the feed-through voltage VFDThe method can reduce the direct current bias voltage of the liquid crystal panel and improve the light transmittance so as to achieve better display effect.
Fig. 1 shows a schematic diagram of a pixel unit of a liquid crystal panel in the prior art. As shown in fig. 1, the pixel unit includes: a glass substrate (not shown), a common electrode line 103, a signal line SL and a gate line GL which cross each other, a pixel area defined by the signal line SL and the gate line GL, a pixel electrode 110 located in the pixel area, and a thin film transistor 111. Wherein, the overlapping area of the pixel electrode 110 and the common electrode line 103 forms a pixel storage capacitor CST. Fig. 2 is a cross-sectional view of the pixel unit shown in fig. 1 taken along line a-a', in fig. 2, the glass substrate 101 is located at the lowest layer, the gate electrode 102 and the common electrode line 103 are located on the glass substrate 101, the gate insulating layer 104 covers the gate electrode 102 and the common electrode line 103, the semiconductor layer 105 is located on the gate insulating layer 104 corresponding to the gate electrode 102, the drain electrode 106 and the source electrode 107 are located on the semiconductor layer 105, the passivation layer 108 is located on the drain electrode 106, the source electrode 107 and the gate insulating layer 104, the passivation layer 108 has a through hole 109, and the pixel electrode 110 is located on the passivation layer 108 and electrically connects the pixel electrode 110 and the source electrode 107 through the through hole 109. The drain 106 is electrically connected to the signal line.
Fig. 3 is a flow chart illustrating a method of manufacturing the thin film transistor array substrate shown in fig. 2. As shown in fig. 3, the manufacturing method may employ the steps of: step 201, providing a glass substrate, and then forming a gate and a common electrode line on the glass substrate; step 202, SiNx, a-Si, n are continuously deposited on the grid electrode and the common electrode line+a-Si to form a gate insulating layer and a semiconductor layer; step 203, forming a source and a drain of the thin film transistorA pole; step 204, depositing a passivation layer, and etching the passivation layer to form a through hole; and step 205, forming a pixel electrode.
Fig. 4 further illustrates a schematic diagram of the formation of the manufacturing method as shown in fig. 3. Wherein fig. 4A is a schematic view of forming gate lines and common electrode lines; fig. 4B is a schematic view of forming a gate insulating layer and a semiconductor layer; FIG. 4C shows a schematic diagram of forming the source and drain of a TFT; FIG. 4D is a schematic illustration of the formation of a passivation layer and vias; and FIG. 4E is a schematic diagram of forming a pixel electrode. In conjunction with fig. 3 and 4, the method for manufacturing the thin film transistor array substrate in the related art may be more specifically expressed as:
in step 205, as shown in fig. 4E, Indium Tin Oxide (ITO) is finally deposited on the passivation layer 108 to form the pixel electrode 110 of the thin film transistor array substrate.
Hereinafter, it is assumed in advance that the dielectric constant of the gate insulating layer of the liquid crystal panel is ∈GWe can analyze and obtain the feed-through voltage VFDAnd dielectric constant εGThe relationship (2) of (c). In general, the dielectric constant of the gate insulating layer 104 is uniformly distributed as shown in FIG. 2, and the pixel stores the capacitanceCSTFormed by a dielectric formed by the pixel electrode 110, the common electrode line 103 and the gate insulating layer 104 and the passivation layer 108 therebetween, which can be equivalent to a capacitance C with the gate insulating layer 104 being a dielectric materialGAnd a capacitor C with a passivation layer 108 as a dielectric materialPIn series, i.e. CST＝CGCP/(CG+CP) (2). Substituting the formula (2) into the formula (1) to obtain a conversion formula (3):
VFD＝{CGS/[CGS+CLC+CG CP/(CG+CP)]}×ΔVG
usually, a liquid crystal capacitor CLCAnd a pixel storage capacitor CSTAll the capacitance values of (A) are parasitic capacitances CGSOf several tens of times the capacitance value of (C), i.e. CLC＞＞CGS，CST＞＞CGS. The above transformation form (3) can be rewritten as formula (4):
VFD＝{CGS/[CLC+CG CP/(CG+CP)]}×ΔVG
the formula (5) for calculating the capacitance of the plate capacitor can be expressed as:
C＝εS/d
combining equations (4) and (5), the feed-through voltage V can be obtainedFDTransformation (6):
wherein, in the formula (6), S1 is to form the parasitic capacitance CGSD1 is the distance between the gate and the source; s2 is forming a pixel storage capacitor CSTD2 is the thickness of the passivation layer 108, epsilonPIs the dielectric constant of the passivation layer 108.
For the numerator of equation (6), the denominator is simultaneously divided by εGEquation (7) can be obtained:
from equation (7), it can be seen that the feed-through voltage VFDDielectric constant epsilon with gate insulating layerGProportional relation, when the dielectric constant is smaller, the feed-through voltage is reduced; as the dielectric constant increases, the feedthrough voltage also increases.
In the prior art, in order to increase the pixel storage capacitance CSTThe dielectric constant of the gate insulating layer 104 of the liquid crystal panel is often set to be large, thereby causing the feed-through voltage VFDThe value increases. As can be seen from the foregoing, the effect of the feedthrough voltage on the pixel voltage is very large, and the display effect is worse as the liquid crystal voltage is larger and the light transmittance is lower. Thus, V is increasedFDAlthough the value can be increasedSTBut at the same time alsoThe dc bias applied to the liquid crystal is increased, resulting in a reduction in display effect.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides a thin film transistor array substrate and a method for manufacturing the same, which reduces parasitic capacitance by improving a gate insulating layer of a TFT thereof, thereby effectively reducing a dc bias voltage.
According to an aspect of the present invention, there is provided a thin film transistor array substrate including a plurality of signal lines, a plurality of gate lines disposed to cross the signal lines, a pixel electrode disposed in a pixel region formed by the signal lines and the gate lines crossing each other, and a thin film transistor disposed near a crossing of the signal lines and the gate lines, the signal lines and the gate lines being disposed on a signal line layer and a gate line layer, respectively, the thin film transistor having a source electrode electrically connected to the pixel electrode and a drain electrode electrically connected to the signal lines, wherein a gate insulating layer is disposed between the signal line layer and the gate line layer, the gate insulating layer having an ion implantation region formed by implanting an ion element, and the ion implantation region being disposed opposite to the source electrode, wherein the implanted ion element lowers a dielectric constant of the ion implantation region.
The gate insulating layer is made of silicon nitride, and the implanted ion element is oxygen ion.
Wherein the ion implantation region is located in a clamping region between a gate and a source of the thin film transistor.
According to still another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate. The manufacturing method comprises the following steps:
depositing a layer of grid line layer and patterning the layer of grid line layer to form a grid line;
depositing a signal line layer, and patterning the signal line layer to form signal lines, wherein the signal lines are arranged to cross the gate lines;
forming a gate insulating layer disposed between the signal line layer and the gate line layer;
forming a thin film transistor having a source electrode electrically connected to a pixel electrode in a pixel region defined by the gate line and the signal line crossing each other and a drain electrode electrically connected to the signal line;
implanting ion elements into a partial region of the gate insulating layer to form an ion implanted region; the ion implantation area is arranged opposite to the source electrode, and the implanted ion elements reduce the dielectric constant of the ion implantation area.
The gate insulating layer is made of silicon nitride, and the implanted ion element is oxygen ion.
The method comprises coating a silicon oxide layer on a gate insulating layer, irradiating and etching a part of the silicon oxide layer to expose a corresponding gate insulating layer, and implanting ion elements into the exposed gate insulating layer to form an ion implantation region. And removing the silicon oxide layer remaining on the gate insulating layer after the ion element implantation process.
According to still another aspect of the present invention, there is provided a liquid crystal display device having the above-described thin film transistor array substrate of the present invention.
By adopting the thin film transistor array substrate and the manufacturing method thereof, the dielectric constant of the corresponding part of the gate insulating layer is reduced by implanting oxygen ions in the part of the region on the gate insulating layer, so as to reduce the feed-through voltage VFDAnd the value of the direct current bias voltage on the liquid crystal is reduced, so that the display effect of the liquid crystal panel is improved. In addition, the ion implantation region formed by implanting ions on the gate insulating layer is only a partial gate insulating layer region, so that the feed-through voltage V can be reducedFDWhile maintaining the value of the pixel storage capacitor CSTHas a large value so that the memory has good capacity for storing leakage current.
Drawings
The various aspects of the present invention will become more apparent to the reader after reading the detailed description of the invention with reference to the attached drawings. Wherein,
FIG. 1 illustrates a schematic diagram of a pixel cell of a prior art liquid crystal panel;
FIG. 2 shows a cross-sectional view of the pixel cell shown in FIG. 1 taken along line A-A';
fig. 3 is a flow chart illustrating a method of manufacturing the thin film transistor array substrate shown in fig. 2;
fig. 4 further illustrates a schematic diagram of the formation of the manufacturing method as shown in fig. 3. Wherein fig. 4A is a schematic view of forming gate lines and common electrode lines; fig. 4B is a schematic view of forming a gate insulating layer and a semiconductor layer; FIG. 4C shows a schematic diagram of forming the source and drain of a TFT; FIG. 4D is a schematic diagram of the formation of a passivation layer; FIG. 4E is a schematic diagram of forming a pixel electrode;
FIG. 5 illustrates a schematic diagram of a pixel cell of a liquid crystal panel in accordance with one or more aspects of the present invention;
FIG. 6 shows a cross-sectional view of the pixel cell shown in FIG. 5 taken along line B-B';
fig. 7 is a flowchart illustrating a method of manufacturing the thin film transistor array substrate shown in fig. 6; while
Fig. 8 further illustrates a schematic diagram of the formation of the manufacturing method shown in fig. 7. Wherein fig. 8A is a schematic view of forming gate lines and common electrode lines; FIG. 8B is a schematic view of forming a gate insulating layer; FIG. 8C is a schematic view of forming a silicon oxide layer; fig. 8D is a schematic view illustrating exposure of a silicon oxide layer in the thin film transistor array substrate according to the present invention; FIG. 8E is a schematic view of the exposed silicon oxide layer being etched to expose a portion of the gate insulating layer; FIG. 8F is a schematic view of implanting ions into the exposed portion of the gate insulating layer and etching away the excess silicon oxide layer; fig. 8G shows a schematic view of forming a semiconductor layer; FIG. 8H is a schematic diagram of source and drain formation; FIG. 8I is a schematic diagram of the formation of a passivation layer and a via; and fig. 8J shows a schematic diagram of forming a pixel electrode.
Detailed Description
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
It will be understood by those skilled in the art that when the symbol C is usedGS、CLC、CSTIn this case, the capacitance between the gate and the source of the thin film transistor array substrate, the liquid crystal capacitance, and the pixel storage capacitance may be respectively represented, or the capacitance values of the three capacitances may be respectively represented.
FIG. 5 illustrates a schematic diagram of a pixel cell of a liquid crystal panel in accordance with one or more aspects of the present invention. The pixel unit includes: a glass substrate (not shown), a common electrode line 303, a thin film transistor 312, a gate line GL and a signal line SL disposed to cross each other, and a pixel area defined by the gate line GL and the signal line SL and a pixel electrode 311 located in the pixel area. Wherein, the overlapping area of the pixel electrode 311 and the common electrode line 303 forms a pixel storage capacitor CSTThe hatched area C shown in fig. 5 is an ion implantation area. Fig. 6 shows a cross-sectional view of the pixel cell shown in fig. 5 taken along the line B-B'. Referring to fig. 5 and 6, a gate electrode 302 and a common electrode line 303 are formed on a glass substrate 301, a gate insulating layer 304 is formed over the gate electrode 302 and the common electrode line 303, an ion implantation region 305 formed by ion implantation is formed in the gate insulating layer 304 and located in a region between the gate electrode 302 and a source electrode 308, a semiconductor layer 306 is formed over the gate insulating layer 304, a drain electrode 307 and a source electrode 308 are formed over the semiconductor layer 306, and passivation is formed over the drain electrode 307 and the source electrode 308Layer 309 and the passivation layer 309 has a via 310 over which is a pixel electrode 311. The pixel electrode 311 is electrically connected to the source 308 through the via 310, and the drain 307 is electrically connected to the signal line.
In the thin film transistor array substrate according to one or more aspects of the present invention, the gate insulating layer 304 is composed of a silicon nitride material. It will be appreciated by those skilled in the art that different materials may be selected according to different manufacturing processes, and the materials used in the above preferred embodiments of the present invention should not be construed as limiting the materials constituting the gate insulating layer, and other materials may be used to form the gate insulating layer. Further, there is an oxygen ion element in the ion implantation region 305 which can lower the dielectric constant, and therefore, the dielectric constant of the ion implantation region 305 is much lower than that of other regions on the gate insulating layer 304. We do not define the formation of parasitic capacitances CGSThe dielectric constant of the gate insulating layer, that is, the dielectric constant of the ion implantation region 305 is ∈G’。
Also, in the thin film transistor array substrate according to one or more aspects of the present invention, the liquid crystal capacitor CLCAnd a pixel storage capacitor CSTAll the capacitance values of (A) are parasitic capacitances CGSOf several tens of times the capacitance value of (C), i.e. CLC＞＞CGS，CST＞＞CGS. The feed-through voltage V can be obtained from equation (1)FDThe modified expression (8) of (a) is:
combining the plate capacitor formula (5) C ═ epsilon S/d, a modified formula (9) of formula (8) can be obtained:
wherein, in the formula (9), εGTo form parasitic capacitance CGSThe dielectric constant of the gate insulating layer (S), i.e., the dielectric constant of the ion implantation region 305, and the parasitic capacitance C is formed in S1GSD1 is the parasitic capacitance C formed by the positive area between the gate and the sourceGSThe distance between the gate and the source; cLCIs the capacitance value of liquid crystal, CSTStoring a capacitance value for the pixel; Δ VGIs the difference between the gate voltages of the TFTs when turned on and off.
Because the facing area S1 between the gate and the source and the distance D1 between the gate and the source are fixed values; and the capacitance C of the liquid crystalLCIs constant, and forms a pixel storage capacitor CSTThe dielectric material of the gate insulating layer 304 and the passivation layer 309 is constant without change, so that the feed-through voltage V is constantFDAnd dielectric constant εGIn a direct relation, i.e. when the dielectric constant is constantSeveral times smaller, the feedthrough voltage decreases accordingly; as the dielectric constant increases, the feedthrough voltage also increases. Since the present invention adopts the ion implantation method to make the ion implantation region 305 have oxygen ion element to reduce the formation of parasitic capacitance CGSHas a dielectric constant epsilon of the gate insulating layerGBased on the proportional relationship between the feedthrough voltage and the dielectric constant, the ion implantation region 305 according to one or more aspects of the present invention reduces the feedthrough voltage V to some extentFDThereby reducing the value of the dc bias voltage on the liquid crystal. It will also be appreciated by those skilled in the art that the present invention utilizes localized ion implantation at reduced feed-through voltage VFDWhile maintaining the value of the pixel storage capacitor CSTHas a large value so that the memory has good capacity for storing leakage current. In addition, when the thin film transistor array substrate is adopted in the liquid crystal display device, oxygen ions are injected into partial areas on the gate insulating layer of the liquid crystal display device, so that the dielectric constant of the corresponding partial gate insulating layer is reduced, the direct current bias value on the liquid crystal is reduced, the display effect of the liquid crystal display device can be greatly improved, and the user experience is enhanced.
Fig. 7 is a flowchart illustrating a method of manufacturing the thin film transistor array substrate shown in fig. 6. As shown in fig. 7, the method for manufacturing a thin film transistor array substrate of the present invention may include the following steps: step 401, providing a glass substrate, and then forming a gate and a common electrode line on the glass substrate; step 402, depositing a layer of SiNx on the grid electrode and the common electrode line to form a grid electrode insulating layer; step 403, depositing a silicon oxide layer on the formed gate insulating layer; step 404, illuminating and etching the silicon oxide layer to expose a part of the gate insulation layer; step 405, performing ion implantation on the partially exposed gate insulating layer to form an ion implantation region; step 406 of depositing a-Si, n on the gate insulation layer+a-Si forming a semiconductor layer; step 407, forming a source electrode and a drain electrode; step 408, depositing a passivation layer and forming a through hole; and step 409, forming a pixel electrode on the passivation layer. FIG. 8 further illustrates the fabrication as shown in FIG. 7The method forms a schematic diagram. Wherein fig. 8A is a schematic view of forming a gate electrode and a common electrode line; FIG. 8B is a schematic view of forming a gate insulating layer; FIG. 8C is a schematic view of forming a silicon oxide layer; fig. 8D is a schematic view illustrating exposure of a silicon oxide layer in the thin film transistor array substrate according to the present invention; FIG. 8E is a schematic view of the exposed silicon oxide layer being etched to expose a portion of the gate insulating layer; FIG. 8F is a schematic view of implanting ions into the exposed portion of the gate insulating layer and etching away the excess silicon oxide layer; fig. 8G shows a schematic view of forming a semiconductor layer; FIG. 8H is a schematic diagram of source and drain formation; FIG. 8I is a schematic diagram of the formation of a passivation layer and a via; and fig. 8J shows a schematic diagram of forming a pixel electrode. Referring to fig. 7 and 8, a method of fabricating a thin film transistor array substrate according to one or more aspects of the present invention may be more specifically expressed as:
in step 409, as shown in fig. 8J, Indium Tin Oxide (ITO) is deposited on the passivation layer 309 to form the pixel electrode 311.
In manufacturing the thin film transistor array substrate according to one or more aspects of the present invention, the implantation of oxygen ions into the exposed region of the gate insulating layer 304 may be performed by ion implantation. It will be appreciated by those skilled in the art that the present invention is not limited to the preferred embodiment described above, but may include other ion implantation methods and other ion elements. These ion elements form a parasitic capacitance CGSThe dielectric constant of the gate insulating layer is remarkably reduced, so that the direct current bias voltage on the liquid crystal is reduced, and the display effect of the liquid crystal panel is improved.
Hereinbefore, specific embodiments of the present invention are described with reference to the drawings. However, those skilled in the art will appreciate that various modifications and substitutions can be made to the specific embodiments of the present invention without departing from the spirit and scope of the invention. Such modifications and substitutions are intended to be included within the scope of the present invention as defined by the appended claims.
Claims (10)
1. A thin film transistor array substrate comprising a plurality of signal lines, a plurality of gate lines arranged to cross the signal lines, pixel electrodes arranged in pixel regions formed by the signal lines and the gate lines crossing each other, and thin film transistors arranged near intersections of the signal lines and the gate lines, the signal lines and the gate lines being arranged on a signal line layer and a gate line layer, respectively, the thin film transistors having gate electrodes, source electrodes electrically connected to the pixel electrodes, and drain electrodes electrically connected to the signal lines, wherein a gate insulating layer is provided between the signal line layer and the gate line layer, characterized in that,
the gate insulating layer has an ion-implanted region formed by implanting an ion element, and the ion-implanted region is disposed opposite to the source electrode, wherein the implanted ion element lowers a dielectric constant of the ion-implanted region.
2. The thin film transistor array substrate of claim 1, wherein the gate insulating layer is made of silicon nitride.
3. The thin film transistor array substrate of claim 1, wherein the implanted ion element is oxygen ion.
4. The thin film transistor array substrate of claim 1, wherein the ion implantation region is located at a clamping region between a gate and a source of the thin film transistor.
5. A method for manufacturing a thin film transistor array substrate, the method comprising:
depositing a layer of grid line layer and patterning the layer of grid line layer to form a grid line;
depositing a signal line layer and patterning the signal line layer to form signal lines, wherein the signal lines are arranged to cross gate lines;
forming a gate insulating layer disposed between the signal line layer and the gate line layer;
forming a thin film transistor having a source electrode electrically connected to a pixel electrode in a pixel region defined by the gate line and the signal line crossing each other and a drain electrode electrically connected to the signal line;
implanting ion elements into partial regions of the gate insulating layer and forming ion implanted regions;
the ion implantation area is arranged opposite to the source electrode, and the implanted ion elements reduce the dielectric constant of the ion implantation area.
6. The method of claim 5, wherein the gate insulation layer is formed of a silicon nitride material.
7. The method of claim 5, wherein the implanted ion element is an oxygen ion.
8. The method of claim 5, wherein a silicon oxide layer is coated on the gate insulating layer, a portion of the silicon oxide layer is irradiated and etched to expose a corresponding portion of the gate insulating layer, and the ion implanted region is formed by implanting an ion element into the exposed portion of the gate insulating layer.
9. The method of claim 8, wherein said silicon oxide layer remaining on said gate insulating layer is removed after said ion implantation process.
10. A liquid crystal display device having the thin film transistor array substrate as claimed in claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101623796A CN100454562C (en) | 2007-09-29 | 2007-09-29 | Thin-film transistor array substrates, manufacturing method and LCD device containing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101623796A CN100454562C (en) | 2007-09-29 | 2007-09-29 | Thin-film transistor array substrates, manufacturing method and LCD device containing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101136415A CN101136415A (en) | 2008-03-05 |
| CN100454562C true CN100454562C (en) | 2009-01-21 |
Family
ID=39160374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101623796A Active CN100454562C (en) | 2007-09-29 | 2007-09-29 | Thin-film transistor array substrates, manufacturing method and LCD device containing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100454562C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593732B (en) * | 2008-05-28 | 2013-09-18 | 统宝光电股份有限公司 | Display unit and formation method thereof as well as electronic device containing same |
| TWI560882B (en) * | 2014-01-17 | 2016-12-01 | E Ink Holdings Inc | Semiconductor structure |
| CN105097557A (en) * | 2015-09-25 | 2015-11-25 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) substrate, TFT switch tube and manufacturing method of TFT switch tube |
| CN109346482B (en) * | 2018-09-30 | 2024-01-05 | 武汉华星光电技术有限公司 | Thin film transistor array substrate, manufacturing method thereof and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1296643A (en) * | 1999-03-10 | 2001-05-23 | 松下电器产业株式会社 | Thin-film transistor, liquid crystal panel, and method for producing the same |
| CN1518056A (en) * | 2003-01-15 | 2004-08-04 | 友达光电股份有限公司 | Manufacturing method of low-temp polycrystal silicon film transistor |
| US20040219723A1 (en) * | 2003-04-16 | 2004-11-04 | Chia-Tien Peng | [low temperature polysilicon thin film transistor and method of manufacturing the same] |
| CN1581449A (en) * | 2003-08-07 | 2005-02-16 | 友达光电股份有限公司 | Thin film transistor manufacturing method and its structure |
| US20050056846A1 (en) * | 2003-09-15 | 2005-03-17 | Industrial Technology Research Institute | Thin film transistor structure for a field emission display and the method for making the same |
| US20050084995A1 (en) * | 2003-10-15 | 2005-04-21 | Kun-Hong Chen | Method of forming a CMOS transistor |
-
2007
- 2007-09-29 CN CNB2007101623796A patent/CN100454562C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1296643A (en) * | 1999-03-10 | 2001-05-23 | 松下电器产业株式会社 | Thin-film transistor, liquid crystal panel, and method for producing the same |
| CN1518056A (en) * | 2003-01-15 | 2004-08-04 | 友达光电股份有限公司 | Manufacturing method of low-temp polycrystal silicon film transistor |
| US20040219723A1 (en) * | 2003-04-16 | 2004-11-04 | Chia-Tien Peng | [low temperature polysilicon thin film transistor and method of manufacturing the same] |
| CN1581449A (en) * | 2003-08-07 | 2005-02-16 | 友达光电股份有限公司 | Thin film transistor manufacturing method and its structure |
| US20050056846A1 (en) * | 2003-09-15 | 2005-03-17 | Industrial Technology Research Institute | Thin film transistor structure for a field emission display and the method for making the same |
| US20050084995A1 (en) * | 2003-10-15 | 2005-04-21 | Kun-Hong Chen | Method of forming a CMOS transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101136415A (en) | 2008-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101957530B (en) | TFT-LCD (Thin Film Transistor-Liquid Crystal Display) array baseplate and manufacturing method thereof | |
| CN101995713B (en) | TFT-LCD array substrate and manufacturing method thereof | |
| US7154569B2 (en) | Liquid crystal display and thin film transistor array panel therefor | |
| KR101414043B1 (en) | Thin film transistor substrate | |
| US8133773B2 (en) | Apparatus and method for reducing photo leakage current for TFT LCD | |
| US8797486B2 (en) | Display panel comprising a pixel electrode including a micro-slit pattern and a control electrode wherein the control electrode overlaps an entire portion of the pixel electrode in a plan view | |
| CN100472305C (en) | Liquid crystal display panel and method of manufacturing the same | |
| US20120161140A1 (en) | Tft array substrate and manufacturing method thereof | |
| CN113394166B (en) | Manufacturing method of array substrate, array substrate and display panel | |
| US8278161B2 (en) | Method for fabricating a thin film transistor array substrate with a thinned protective film over a storage capacitor | |
| US20070024770A1 (en) | Liquid crystal display device and method of fabricating the same | |
| US20050190312A1 (en) | [pixel structure and manufacturing method thereof] | |
| TW536828B (en) | Bottom gate type thin film transistor, its manufacturing method and liquid crystal display device using the same | |
| CN108231850B (en) | Array substrate, preparation method thereof and display panel | |
| WO2014153958A1 (en) | Array substrate, method for manufacturing array substrate and display device | |
| CN102436104B (en) | Pixel structure and manufacturing method thereof | |
| CN100454562C (en) | Thin-film transistor array substrates, manufacturing method and LCD device containing the same | |
| CN100578760C (en) | Making method for thin film transistor array base plate | |
| CN105870132A (en) | TFT (thin film transistor) array substrate and manufacturing method therefor | |
| US7349036B2 (en) | Liquid crystal display storage device and method of fabricating the same | |
| US7646021B2 (en) | Thin film transistor array substrate | |
| US20110217823A1 (en) | Storage capacitor having an increased aperture ratio and method of manufacturing the same | |
| JP2001021920A (en) | Thin-film transistor substrate and liquid crystal display device | |
| JP2005107526A (en) | Ocb mode liquid crystal display | |
| US7359022B2 (en) | Wire structure of display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 215301 No. 1, Longteng Road, Kunshan, Jiangsu Patentee after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301 No. 1, Longteng Road, Kunshan, Jiangsu Patentee before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |