CN1571144A - Self-alignment process for flash memory - Google Patents
Self-alignment process for flash memory Download PDFInfo
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- CN1571144A CN1571144A CN03146464.5A CN03146464A CN1571144A CN 1571144 A CN1571144 A CN 1571144A CN 03146464 A CN03146464 A CN 03146464A CN 1571144 A CN1571144 A CN 1571144A
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000000137 annealing Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 21
- 230000001590 oxidative effect Effects 0.000 claims abstract description 7
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims description 43
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 36
- 150000003377 silicon compounds Chemical class 0.000 claims description 31
- 238000010438 heat treatment Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000012298 atmosphere Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 150000002978 peroxides Chemical class 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 229910021332 silicide Inorganic materials 0.000 abstract 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 2
- 239000013078 crystal Substances 0.000 description 12
- 230000008646 thermal stress Effects 0.000 description 8
- 230000008021 deposition Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 238000001000 micrograph Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 239000003643 water by type Substances 0.000 description 1
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- Non-Volatile Memory (AREA)
Abstract
The invention is a self-aligning manufacture procedure used in flash memory body, for providing a memory body manufacturing method that assures the side wall of gate smooth, strengthens voltage resistance of gate, prolongs service life of flash memory body, and it includes the steps: forming a gate containing metallic silicide layer on a tunneled oxidizing layer, forming source and drain by using the gate as a cover, etching the side wall of metallic silicide, oxidizing and annealing and forming side liner of the side wall nearby the gate.
Description
Technical field
The invention belongs to method for manufacturing memory, particularly a kind of autoregistration processing procedure that is used for fast flash memory bank.
Background technology
On the complicated integrated circuit, dwindling of component size used to such an extent that design is difficult more, therefore, uses and uses autoregistration processing procedure or other technologies usually, to reach required design.
As shown in Figure 1, the gate structure 10a of typical fast flash memory bank comprise substrate 12a, be deposited on tunnel oxide 14a on the substrate 12a, be deposited on tunnel oxide 14a go up float gate polysilicon layer 16a, be deposited on ONO layer 18a on the polysilicon layer 16a, be deposited on ONO layer 18a go up control grid polysilicon layer 20a, be deposited on polysilicon layer 20a go up control grid silicon tungsten layer 22a, be deposited on mask 24a on the silicon tungsten layer 22a, be deposited on side walls limit lining 26a, 28a, be located at source electrode 30a and drain 32a in the substrate 12a.
In the process of making gate structure, need in substrate 12a, to adopt deposition and etched processing procedure to finish the gate lamination, and use the autoregistration processing procedure to form source electrode 30a and drain 32a, after forming side edge lining 26a, 28a, use the autoregistration processing procedure, as United States Patent (USP) the 5th, 907, No. 781 and 6, (process for fabricating an Integrated circuit with a self-alignedcontact) the autoregistration processing procedure that proposes in 444, No. 530 forms source electrode 30a and drain 32a contact.
Owing in the gate structure of known fast flash memory bank, comprise silicon tungsten layer 22a, at follow-up hot processing procedure, during for example heating anneal is handled, the crystal structure of silicon tungsten becomes the hexagonal cubic crystal by four jiaos of cubic crystals, makes silicon tungsten be subjected to the influence of thermal stress and expand to cause critical dimension (Critical Dimension; The distance of increase CD) and shortening and contact hole, the latter further causes low breakdown voltage.Moreover, because the growth again of silicon tungsten crystal block (grain), extruding makes the sidewall of gate structure become coarse and uneven each other, increased internal field (local electrical filed) effect, cause point discharge to cause the damage of gate easily, make that the useful life of fast flash memory bank is of short duration.
Summary of the invention
The purpose of this invention is to provide a kind ofly guarantee that gate sidewalls is level and smooth, increase gate withstand voltage, prolong the fast flash memory bank autoregistration processing procedure that is used for fast flash memory bank in useful life.
Present invention resides on the tunnel oxide formation gate step that forms the gate that contains metal silicon compounds layer, be that shade forms source electrode and drain step, etching metal silicon thing sidewall step, oxidizing annealing treatment step and forms side edge lining step in the next door of gate with the gate.
Wherein:
A kind of autoregistration processing procedure that is used for fast flash memory bank, it comprise in regular turn deposit the formation gate step of the first polysilicon layer, ONO layer, the second polysilicon layer, silicon tungsten layer and mask at tunnel oxide, with the gate be that shade forms source electrode and drain step, cleans the sidewall step, annealing in process step and form side edge lining step in the next door of gate; Clean sidewall step system and clean the sidewall of silicon tungsten layer, with at the etched formation pothole of the sidewall of silicon tungsten layer with the high solution of etching selectivity; Form in the side edge lining step and between silicon tungsten layer and side edge lining, form the gap; The annealing in process step is that oxidizing annealing is handled.
The autoregistration processing procedure that is used for fast flash memory bank is characterized in that the high solution of etching selectivity in the described cleaning sidewall step is the solution of SC-1 alkaline peroxide mixed liquor.
The autoregistration processing procedure that is used for fast flash memory bank is characterized in that described annealing in process step is the processing of the Fast Heating under oxygen radical atmosphere.
In the etching metal silicon thing sidewall step system is the sidewall of use to the high solution etching metal silicon compounds layer of metal silicon compounds layer etching selectivity.
The annealing in process step is that Fast Heating is handled.
The Fast Heating of annealing in process step is treated to Fast Heating processing under oxygen radical atmosphere.
The Fast Heating of annealing in process step is treated to the Fast Heating that feeds hydrogen and oxygen in reative cell and handles.
Air pressure in the reative cell is about 5at to 50at.
Owing to present invention resides on the tunnel oxide formation gate step that forms the gate that contains metal silicon compounds layer, be that shade forms source electrode and drain step, etching metal silicon thing layer sidewall step, oxidizing annealing treatment step and forms side edge lining step in the next door of gate with the gate.The sidewall of etching metal silicon compounds layer, make the etched formation pothole of sidewall of metal silicon compounds layer, with in annealing in process, make and form the gap between metal silicon compounds layer and the side edge lining, thereby the distance between increase metal silicon compounds layer and the side edge lining, when metal silicon compounds layer is subjected to the influence of thermal stress and expands, no longer produce and push and destroy gate, therefore, it is level and smooth that the surface of metal silicon compounds layer keeps, and the distance between unlikely shortening and the contact hole, thereby do not produce the adverse consequences that internal field rises and breakdown voltage reduces.Guarantee that not only gate sidewalls is level and smooth, it is withstand voltage to increase gate, and prolong fast flash memory bank useful life, thereby reach purpose of the present invention.
Description of drawings
Fig. 1, be typical flash memory body structural representation cutaway view.
Fig. 2, form gate, source electrode and drain step schematic diagram for the present invention.
Fig. 3, form side edge lining step schematic diagram for the present invention.
Fig. 4, for make gate distortion schematic diagram with prior art method.
Fig. 5, for make the micrograph of traditional gate with conventional method.
Fig. 6, be the micrograph of the gate made with the present invention.
Embodiment
The present invention includes following steps:
Step 1
As shown in Figure 2, substrate 12 deposition tunnel oxides 14, tunnel oxide 14 be deposited as float gate the first polysilicon layer 16, deposition ONO layer 18 on the first polysilicon layer 16, be deposited as the second polysilicon layer 20 of control grid on the ONO layer 18, on the second polysilicon layer 20 deposition silicon tungsten layer 22, on silicon tungsten layer 22 deposition mask 24, to form gate 10.Also can be and forming the gate lamination that contains metal silicon compounds layer on the tunnel oxide on 14.
Step 2
With gate 10 is that shade forms source electrode 30 and drain 32 in substrate 12.
Step 3
Clean sidewall
Clean the sidewall of silicon tungsten layer 22 or metal silicon compounds layer with the high solution of etching selectivity, preferable system uses SC-1 to clean silicon tungsten layer 22 or metal silicon compounds layer, with the sidewall of etching silicon tungsten layer 22 or metal silicon compounds layer, the critical dimension of control silicon tungsten layer 22 or metal silicon compounds layer; SC-1 is five parts of deionized waters alkaline peroxide mixed liquors that 30% hydrogen peroxide, a 29% ammoniacal liquor form of plusing fifteen.When using the high solution of etching selectivity to clean, the etch-rate of silicon tungsten layer 22 or metal silicon compounds layer each layer than other is fast, therefore, as shown in Figure 3, the etched formation pothole of sidewall of silicon tungsten layer 22 or metal silicon compounds layer.
Annealing in process
In containing the environment of oxygen radical, carry out oxidation rapid thermal treatment (RTP), make gate 10, source electrode 30 and drain 32 activation and form oxide layer and prevent electric leakage in the first polysilicon layer, 16 outer rim of float gate.Heat treated ties up to Fast Heating processing (Rapid Thermal Processing under the oxygen radical atmosphere; RTP), the thermal oxidation under this atmosphere is because be that surface reaction is main mechanism, and can make silicon tungsten layer 22 or metal silicon compounds laminar surface keep smooth and be not easy to make silicon tungsten layer 22 or metal silicon compounds layer expands.When use is quickened heat treated under oxygen radical atmosphere, hydrogen and oxygen are being passed through in the reative cell to the low pressure of 50at (Bristol) about 5at (Bristol) greatly.Make the crystal structure of silicon tungsten layer 22 or metal silicon compounds layer become the hexagonal cubic crystal in the annealing in process by four jiaos of cubic crystals.
Step 5
Form side edge lining 26,28
Make the crystal structure of silicon tungsten layer 22 or metal silicon compounds layer become the hexagonal cubic crystal in the annealing in process by four jiaos of cubic crystals.As shown in Figure 3, after silicon tungsten layer 22 or metal silicon compounds layer become the hexagonal cubic crystal, carry out the deposition of silicon nitride or silicon layer and etching and form side edge lining 26,28 in gate 10 sidewalls.Owing to previous use the high solution of etching selectivity to clean silicon tungsten layer 22 or etching metal silicon compounds layer and in the etched formation pothole of sidewall of silicon tungsten layer 22 metal silicon compounds layers, make silicon tungsten layer 22 or metal silicon compounds layer and side edge serve as a contrast 26, form gap 34 between 28,36, thereby increase silicon tungsten layer 22 or metal silicon compounds layer and side edge lining 26, distance between 28, when silicon tungsten layer 22 or metal silicon compounds layer are subjected to the influence of thermal stress and expand, no longer produce and push and destroy gate 10, therefore, it is level and smooth that the surface of silicon tungsten layer 22 or metal silicon compounds layer keeps, and the distance between unlikely shortening and the contact hole, thereby do not produce the adverse consequences that internal field rises and breakdown voltage reduces.
As shown in Figure 4, in traditional brake structure made from traditional autoregistration processing procedure, its silicon tungsten layer is subjected to the influence of thermal stress and expands, owing to having unnecessary space, the silicon tungsten layer do not accept the volume that the thermal stress influence is expanded, the crystal block mutual extrusion that causes silicon tungsten layer inside makes the critical dimension of silicon tungsten increase and reduces breakdown voltage between gate and the contact hole.
The present invention ties up to the gap 34,36 that forms between silicon tungsten layer 22 and the side edge lining 26,28 as the buffer area, when silicon tungsten layer 22 is subjected to thermal stress influence and when expanding, the expansion of 34,36 buffering silicon tungsten layers 22 by the gap and do not influence the structure of silicon tungsten layer 22 inside.
As shown in Figure 5, in the micrograph of the gate structure that conventional process is made, the surface that can see is squeezed after the silicon tungsten layer is because of the thermal stress expansion makes sidewall is very coarse.
As shown in Figure 6, in the micrograph of the gate structure that the present invention makes, can see that its sidewall surfaces is very level and smooth because of the silicon tungsten layer is not squeezed because of thermal stress expands.Therefore the present invention obviously improves the easy shortcoming of damaging of gate structure that known techniques is made.
Claims (9)
1, a kind of autoregistration processing procedure that is used for fast flash memory bank, it comprise in regular turn deposit the formation gate step of the first polysilicon layer, ONO layer, the second polysilicon layer, silicon tungsten layer and mask at tunnel oxide, be that shade forms source electrode and drain step, annealing in process step and forms side edge lining step in the next door of gate with the gate; It is characterized in that comprising before the described annealing in process step and clean the sidewall step, it is the sidewall that cleans the silicon tungsten layer with the high solution of etching selectivity, with at the etched formation pothole of the sidewall of silicon tungsten layer; Form in the side edge lining step and between silicon tungsten layer and side edge lining, form the gap; The annealing in process step is that oxidizing annealing is handled.
2, the autoregistration processing procedure that is used for fast flash memory bank according to claim 1 is characterized in that the high solution of etching selectivity in the described cleaning sidewall step is the solution of SC-1 alkaline peroxide mixed liquor.
3, the autoregistration processing procedure that is used for fast flash memory bank according to claim 1 is characterized in that described annealing in process step is the processing of the Fast Heating under oxygen radical atmosphere.
4, a kind of autoregistration processing procedure that is used for fast flash memory bank, it is included on the tunnel oxide formation gate step that forms the gate that contains metal silicon compounds layer, be that shade forms source electrode and drain step, annealing in process step and forms side edge lining step in the next door of gate with the gate; It is characterized in that described it is characterized in that comprises etching metal silicon thing sidewall step before the described annealing in process step; The annealing in process step is that oxidizing annealing is handled.
5, the autoregistration processing procedure that is used for fast flash memory bank according to claim 4 is characterized in that described etching metal silicon thing sidewall step is the sidewall of use to the high solution etching metal silicon compounds layer of metal silicon compounds layer etching selectivity in being.
6, the autoregistration processing procedure that is used for fast flash memory bank according to claim 4 is characterized in that described annealing in process step is that Fast Heating is handled.
7, the autoregistration processing procedure that is used for fast flash memory bank according to claim 6 is characterized in that the Fast Heating of described annealing in process step is treated to Fast Heating processing under oxygen radical atmosphere.
8, the autoregistration processing procedure that is used for fast flash memory bank according to claim 6 is characterized in that the Fast Heating of described annealing in process step is treated to the Fast Heating processing that feeds hydrogen and oxygen in reative cell.
9, the autoregistration processing procedure that is used for fast flash memory bank according to claim 8 is characterized in that the air pressure in the described reative cell is about 5at to 50at.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031464645A CN1306596C (en) | 2003-07-15 | 2003-07-15 | Self-alignment process for flash memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031464645A CN1306596C (en) | 2003-07-15 | 2003-07-15 | Self-alignment process for flash memory |
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| Publication Number | Publication Date |
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| CN1571144A true CN1571144A (en) | 2005-01-26 |
| CN1306596C CN1306596C (en) | 2007-03-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031464645A Expired - Fee Related CN1306596C (en) | 2003-07-15 | 2003-07-15 | Self-alignment process for flash memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730344A (en) * | 2012-10-12 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | Method for forming silicon oxide side wall of gate of metal tungsten silicide |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143611A (en) * | 1998-07-30 | 2000-11-07 | Micron Technology, Inc. | Semiconductor processing methods, methods of forming electronic components, and transistors |
| US6180454B1 (en) * | 1999-10-29 | 2001-01-30 | Advanced Micro Devices, Inc. | Method for forming flash memory devices |
| KR100355238B1 (en) * | 2000-10-27 | 2002-10-11 | 삼성전자 주식회사 | Method for fabricating cell of flash memory device |
| CN1402334A (en) * | 2001-08-09 | 2003-03-12 | 旺宏电子股份有限公司 | Method for mfg. semiconductor internal storage module with gate stacked dielectric layer |
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2003
- 2003-07-15 CN CNB031464645A patent/CN1306596C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730344A (en) * | 2012-10-12 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | Method for forming silicon oxide side wall of gate of metal tungsten silicide |
| CN103730344B (en) * | 2012-10-12 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | The method forming the monox lateral wall of metallic silicon tangsten silicide grid |
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| Publication number | Publication date |
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| CN1306596C (en) | 2007-03-21 |
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