CN1567807A - A frequency domain filter and method for implementing frequency domain filter - Google Patents
A frequency domain filter and method for implementing frequency domain filter Download PDFInfo
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Abstract
The invention discloses a frequency domain filter, including: control module, memory cell array, filter coefficient memory, data switching module, rotary factor table-look-up module, output data combining module and at least a high-speed universal operating unit; the high-speed universal operating unit can make time division multiplex by the memory cell array and data switching module and provides resources for completing the data operation processing, such as FFT (fast Fourier transform algorithm), IFFT (inverse fast Fourier transform algorithm) and frequency domain filtering operation. And the same time, it also discloses a method of realizing the frequency domain filtering. It overcomes the disadvantages of traditional frequency filtering structure and provides a project for realizing perfect high-efficiency filter based on IFFT and having filtering characteristic able to dynamically change.
Description
Technical field
The present invention relates to Digital Signal Processing, be meant the method for a kind of frequency domain filter and realization frequency domain filtering especially.
Background technology
In present digital information processing system, the each side such as shaping of the filtering that filter is widely used in disturbing, the extraction of useful signal, signal.For discrete digital signal general, linear time invariant system, at present main time domain Conlution Integral and the frequency domain two kinds of filters of type that multiply each other that use are handled it.For the constant filter of filtering characteristic, the filter of time domain Conlution Integral is saved computational resource because the circuit way of realization of lookup table mode is efficiently arranged very much, so obtained using widely in chip design.But in some occasion, the shape of the unit impulse response of filter need change dynamically, thereby makes the filter of time domain convolution form be difficult to design, and the resource that needs is also too much.In this case, can time-domain signal be converted to frequency-region signal with fast Fourier transform (FFT), can finish filtering after simply multiplying each other with the filter frequency domain coefficient again, by inverse fast fourier transform (IFFT) filtered frequency-region signal is converted to time-domain signal output then.
Be called " method and apparatus of broadband and narrowband wireless communication simultaneously " at a key name, publication number is in the Chinese invention patent application of CN 1141104A, discloses a frequency domain filtering scheme based on the positive inverse transformation of Fourier.As shown in Figure 1, the input signal of module is code division multiple access (CDMA) carrier signal in a broadband and frequency modulation (FM) signal of several arrowbands, this scheme is directly to carry out fast fourier transform 41 after above-mentioned two signals are mixed, carry out the detection 42 of FM signal power then at frequency domain, and, will do not carried out inverse fast fourier transform 44 again and be reduced to the code division multiple access carrier wave time-domain signal that does not comprise FM signal by the signal of filtering with of the trapper filtering 43 of detected FM signal with frequency domain.
Owing to directly signal is carried out the positive and negative conversion process of fast Flourier in this scheme, this will cause through near the data the head and the tail of the data segment behind the Fourier transform through the saltus step of phase place takes place after the Filtering Processing, thereby seriously influenced filter effect, and it is will make the phase place generation of filtered signal non-linear, thereby very big to the demodulation performance influence of cdma system; In addition, because the computing of positive inverse-Fourier transform time-delay is very big, thereby cause the group delay of whole filter also very big, and in the cellular radio communication system of code division multiple access, the time-delay of signal processing conference have a strong impact on indexs such as the radius of society of wireless communication system and power control, so need take measures necessary to come control and treatment time-delay effectively; Simultaneously, this programme can't be revised dynamically from the outside to the filter frequency domain coefficient.
Be called " method of optimizing the performance of mobile radio system transmitter " in another name, publication number is in the Chinese invention patent application of CN 1354609A, also discloses a frequency domain filtering scheme based on the positive inverse transformation of Fourier, as shown in Figure 2.The described scheme of this patent application be a kind of utilization comprise discrete Fourier transform (DFT) computing, frequency domain filtering, discrete fourier inverse transformation (IDFT) computing, overlap handle sampling point piece and over-sampling some handle the method for the performance of operation optimization mobile radio system multicarrier transmitters.Wherein, the order of magnitude for the order of magnitude of given input sample frequency, given output sampling frequency rate and given desired frequency resolution is chosen to select as far as possible subtly to overlap percentage and oversample factor with the length L DFT of DFT and the length L IDFT of IDFT.
This scheme at first according to frequency domain resolution requirement, the input signal bandwidth of DFT and the information such as output signal bandwidth of IDFT, is determined the length of the positive inverse transformation of discrete Fourier, the percentage and the oversample factor of overlapping; Carry out frequency offset processing according to each carrier signal that corresponding overlapping percentage overlaps after extracting through frequency converter 7,8, each channel center frequency adjustment is correct; Then carry out zero padding shifting processing 1, data length is carried out the normalization adjustment; Carry out DFT computing 2 again, at frequency domain carrier signal is carried out the molding filtration computing 3 of broadband signal then, frequency domain data with each carrier wave merges zero padding simultaneously to adjust data length 4 again, carry out IDFT computing 5 then, to the time domain data that recovers the processing 6 that the data addition merges that overlaps, obtain final filtered time domain data at last.
Because this scheme is the application that merges moulding at the signal of multicarrier, so there are some shortcomings aspect the frequency domain filtering realization.At first, because the processing that overlaps is to select the overlap-add mode for use, and has the restriction of signal bandwidth, so limited to the optimization of filtering group delay index; And, suppress circuit so need to introduce extra phase hit owing to do not improve the problem of phase hit fully; Secondly, length, the speed of the positive and negative transform operation of discrete fourier of unlike signal have very big-difference, can't carry out the reuse plan of computing module, cause resource to use too much, realize that difficulty increases, cost significantly rises; At last, this scheme also can't realize revising dynamically from the outside to the filter frequency domain coefficient.
The time-delay of frequency domain filtering processing procedure is all bigger generally speaking, and the problem such as non-linear that will occur signal filtering weak effect that head and the tail locate, phase place through the data segment behind the segmented Fourier transform, thereby make the design of frequency domain filtering and application be subjected to certain restriction, but, if increase the overlapping and the folded processing of reciprocal cross to time domain data in the frequency domain filtering processing procedure after, above problem just can be significantly improved.The principle of the folded treatment technology of overlapping and reciprocal cross, as shown in Figure 3: if the time-domain signal S1 of input will carry out the fast fourier transform that computing length is N, and requiring the overlapping length in the overlapping processing procedure is L, so can be from first data point of S1, on S1, get the data segment that a segment length is N data every (N-L) individual data, L data wherein counting from end in each data segment are identical with preceding L data of next data segment, and the length that promptly overlaps is L.Like this, can in sequence S1 be divided into several length is that N, overlapping length are the data segment of L, thereby finished the overlapping of time-domain signal S1 is handled.Because the length of S1 is not restriction in theory, thus the overlapping processing procedure of F1 data segment before we can consider to get, more a plurality of data segments the overlapping processing procedure can the rest may be inferred.
Above-mentioned F1 the data segment that overlaps after handling carries out fast fourier transform, frequency domain filtering, inverse fourier transform respectively, carries out the folded processing of reciprocal cross as described below again through corresponding F1 the time domain dateout section that obtains after the above-mentioned processing.
The folded method of handling of multiple reciprocal cross is arranged in the prior art, wherein a kind of is exactly need to be carried out folded each data segment handled of reciprocal cross directly carry out stack combinations according to the order in the overlapping processing procedure, form the process frequency domain filtering data afterwards that hope obtains, this method is called the overlap-add method, just has been to use this kind method in the above-mentioned prior art two; Except that above-mentioned overlap-add method, also has a kind of more effective overlapping treatment technology at present, as shown in Figure 3, exactly each need be carried out each L/2 data of folded F1 the data segment front and back ends of handling of reciprocal cross rejects, (N-L) remaining in each data segment individual data are proposed, make up according to the order in the overlapping processing procedure, form the process frequency domain filtering processing data afterwards that hope obtains.As can be seen from Figure 3, after this overlapping, the folded processing of reciprocal cross, the filtering data of output has shifted to an earlier date L/2 data sampling point than the input data that overlap before handling, and just makes the group delay of frequency domain filtering reduce the corresponding time; Simultaneously, owing in the folded processing procedure of reciprocal cross, rejected each L/2 of front and back ends data of each data segment, thus avoided the data output at data segment edge, make filter effect have greatly improved.Along with the increase of overlapping length L, the performance of filtering is just good more, but simultaneously the resource of realization is increased greatly, and cost raises.So, when improving filtering performance, also must solve the resource problem of realization effectively.
Summary of the invention
In view of this, the method that main purpose of the present invention is to provide a kind of frequency domain filter and realizes frequency domain filtering when effectively improving filtering performance and reducing the filter time-delay, also can reduce the realization cost greatly.
Further purpose of the present invention is to provide the method for above-mentioned frequency domain filter and realization frequency domain filtering, can convenient, fast, dynamically revise the filtering characteristic of frequency domain filter.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of frequency domain filter comprises that control module, memory cell array, filter coefficient storage, data switching module, twiddle factor table look-up module, dateout merge module and at least one high-speed universal operating unit; Wherein,
The time domain data that need carry out frequency domain filtering is connected to described memory cell array by data/address bus, this memory cell array will export described dateout through the time domain data that frequency domain filtering is handled to by data/address bus and merge module, the final time domain data of output after gain is adjusted;
Be connected by read/write, address signal line between described control module and the memory cell array;
Described control module connects the time domain data synchronizing signal of outside input;
Described control module dateout merging controls signal to described dateout and merges module, controls the gating and the merging of filtered time domain dateout;
Described control module output twiddle factor is tabled look-up and is controlled signal to described twiddle factor table look-up module, control its Fourier just/table look-up synchronously during inverse transformation and export corresponding twiddle factor to the high speed universal operating unit;
Described control module dateout switch-over control signal is to described data switching module, control it to gatings of memory cell array I/O data and to the switching of computing of high-speed universal operating unit Fourier and frequency domain filtering operational data, all link to each other between memory cell array and data switching module and data switching module and the high-speed universal operating unit by BDB Bi-directional Data Bus;
Described control module output state controls signal to described high-speed universal operating unit, controls the switching of its Fourier computing and frequency domain filtering compute mode.
Described memory cell array is made of at least two memory cell.
Described memory cell array is an array ram.
Described memory cell is the RAM group that is made of at least 2 RAM.
Described filter coefficient storage is made of at least one RAM.
Described high-speed universal operating unit is a butterfly processing element.
Described data switching module is made of input selector, outlet selector, input splitter, output splitter and two input and output switch units at least at least; Described input and output switch unit equates on number with memory cell in the memory cell array, and it is corresponding one by one, and each input and output switch unit connects by the BDB Bi-directional Data Bus memory cell corresponding with it respectively, one circuit-switched data output of each input and output switch unit all is connected to described input selector, and a circuit-switched data input of each input and output switch unit all is connected to described output splitter; The data output end of input selector connects described input splitter; The two paths of data output of input splitter connects described high-speed universal operating unit; The two paths of data input of outlet selector connects described high-speed universal operating unit, and the data output end of outlet selector connects described output splitter.
Described control module is further exported synchronous control signal to described filter coefficient storage, controls it and is in write-protect during use, in idle period of time cancellation write-protect, can carry out the renewal of filter coefficient.
A kind of method that realizes frequency domain filtering may further comprise the steps:
Each section time domain data that respectively needs is carried out frequency domain filtering overlaps and is stored in each memory cell of a memory cell array;
The time domain data of each section overlapping of said memory cells array stores is carried out Fourier transformation computation, frequency domain filtering computing, inverse fourier transform computing respectively in different time sections in same high-speed universal operating unit, and will be stored in again in each memory cell of memory cell array through the time domain data after the above-mentioned Filtering Processing;
Select to read the time domain data after the Filtering Processing in above-mentioned each memory cell that is stored in memory cell array successively, carry out simultaneously that reciprocal cross is folded to be handled, merge output and obtain final time domain data; And,
To one section time domain data before the storage of memory cell array one memory cell is finished, high-speed universal operating unit to the overlapping of memory cell array previous storage unit storage the last period time domain data the inverse fourier transform computing finish.
Described frequency domain filtering method, further comprising further gains to adjust to the time domain data that reciprocal cross is folded after handling handles.
Described frequency domain filtering method comprises that further the filter factor to described frequency domain filtering computing upgrades.
Described frequency domain filtering method, when one section overlapping time domain data of a cell stores in the memory cell array was carried out Fourier transformation computation, frequency domain filtering computing and inverse fourier transform computing in high-speed universal operating unit, read and the writing of operation result of its operational data is alternating in two memories of memory cell carried out simultaneously.
The present invention is directed near filter effect difference of data segment head and the tail and the bigger problem of filter time-delay in the common frequency domain filtering scheme, increased folded processing of overlapping, reciprocal cross of data, by suitably increasing overlapping length, can effectively improve the effect of filtering and the time-delay of reduction filter; The present invention passes through time division multiplexing, with a small amount of even a high-speed universal operating unit, as butterfly processing element, just can finish data operations such as a plurality of fast fourier transform through data segments that overlap to handle, inverse fast fourier transform, frequency domain filtering computing handles, saved a large amount of arithmetic elements, thereby greatly reduce the resource user demand, make realization convenient, realize that cost reduces greatly.Simultaneously, the present invention also provides a filter coefficient storage, can revise the coefficient of filter convenient, fast, dynamically, can well be used in some need the system of adaptive-filtering characteristic.
Description of drawings
Fig. 1 is the technical scheme schematic diagram of prior art one;
Fig. 2 is the technical scheme schematic diagram of prior art two;
Fig. 3 is overlapping, the folded treatment technology principle schematic of reciprocal cross;
Fig. 4 is a dynamic frequency domain filtering handling principle schematic diagram of the present invention;
Fig. 5 is a dynamic frequency domain filter implementation structure schematic diagram of the present invention;
Fig. 6 is the flow chart of data processing figure of a RAM group among the embodiment among the present invention
Fig. 7 is the data switching module structural representation in the dynamic frequency domain filter of the present invention;
Fig. 8 is the overall sequential chart of the data processing of one embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention express clearlyer, the present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Among the present invention signal is carried out principle that dynamic frequency domain filtering handles as shown in Figure 4, may further comprise the steps:
Step 401: with the time-domain signal of input, i.e. input traffic, the processing that overlaps makes it be divided into a plurality of data segments that carry out overlapping value according to certain overlapping percentage.
Step 402: will carry out fast fourier transform respectively through each data segment that overlaps after handling.
Step 403: will finish the frequency domain filtering computing through the frequency domain filter multiplication that provides in each section frequency domain data that obtains after the fast fourier transform and the filter coefficient storage.Wherein, the coefficient of frequency domain filter is placed in the filter coefficient storage, and this memory can carry out real-time update by software or other counting circuits, realizes on-the-fly modifying of frequency domain filter characteristic.
Step 404: each data segment that will finish frequency domain filtering carries out inverse fast fourier transform respectively, reverts to the time domain data section.
Step 405: each time domain data section is carried out the folded processing of reciprocal cross, obtain the time domain output stream.
In above-mentioned overlapping and the folded processing procedure of reciprocal cross, along with the increase of overlapping length L, required calculation resources etc. also increase greatly, thereby cause cost to raise.For addressing this problem, must improve the efficient of computing, and effectively the multiplexing of height be carried out in computing and control unit.Owing to before carrying out Fourier transformation computation, need carry out the storage of time domain data, so can make and wait for that the time domain data memory period carries out Fourier transformation computation as much as possible with the speed raising of fast Flourier computing when carrying out the storage of time domain data.In the general wide-band communication system, the transmission rate of base band time domain data is often more than several megahertzes, so, can with after tens of times of the message transmission rate frequencys multiplication as the arithmetic speed of Fourier transform, thereby various resources such as arithmetic element are fully utilized.
Based on computing module than input of the time domain data of low rate and Fourier transform at a high speed, can design a kind of function admirable, dynamic frequency domain filtering scheme cheaply, its implementation structure is as shown in Figure 5.
One of main feature of the present invention has been to use a memory cell array, this array by at least 2 independently memory cell constitute, for the intermediate data through the data segment after overlap handling and Fourier computing, filtering operation provides memory space, this memory cell array can be random access memory (RAM) (RAM) array.With the array ram is example, and each memory cell in the array ram is called a RAM group, and each RAM group is made of at least 2 RAM, and its function is to finish the stored on-site of data operation.At one time, can only be one among two RAM and be in read states that another is in the state of writing, the data that RAM that is in read states is responsible for needs are calculated are read in the mode of data flow, give computing unit; Result of calculation then can store on the same group another into and be in the RAM of the state of writing.
In addition, the present invention utilizes the characteristics of High-speed IC's Chip, has used the universal operating unit of a high speed, as butterfly processing element, this unit can carry out time division multiplexing by said memory cells array and a kind of data switching module provided by the invention, for other computings provide resource.
Simultaneously, the present invention also provide one can be by the filter coefficient storage of external control, its function is dynamically to revise the filtering characteristic of frequency domain filter, and makes outside renewal to filter coefficient realize synchronous with the filtering operation process.
With the memory cell array is that array ram is an example, and as shown in Figure 5: a kind of dynamic frequency domain filter provided by the invention comprises that control module 501, memory cell array 502, filter coefficient storage 503, data switching module 504, dateout merge module 506, twiddle factor table look-up module 507 and at least one high-speed universal operating unit 505; Control module 501 has 6 tunnel control signal output ends, connect described memory cell array 502, filter coefficient storage 503, data switching module 504, high-speed universal operating unit 505, dateout merging module 506 and twiddle factor table look-up module 507 respectively, control module 501 also has one road external control signal input port.
Wherein, control signal 10 provides the read-write control and the gating control signal of memory cell array, the read-write of processing such as the input of control data, output, overlapping, reciprocal cross are folded, butterfly computation, frequency domain filtering; Control signal 11 is that dateout merges control signal, controls gating, the merging of the final time domain dateout of different memory cell; Control signal 12 is synchronous control signals of filter coefficient storage, carries out the write-protect of memory between the memory coefficient operating period, cancels write-protect in idle condition, can carry out the renewal of coefficient; Control signal 13 is the twiddle factor control signals of tabling look-up, and makes tabling look-up of twiddle factor synchronous with the Fourier computing, and when the positive and negative conversion of Fourier the corresponding twiddle factor of control output; Control signal 14 is state control signals of high-speed universal operating unit, realizes the butterfly computation state of this unit and the switching controls between the frequency domain filtering compute mode; Control signal 15 is data switch-over control signals, by gating control to the inputoutput data of memory cell and high-speed universal operating unit, realized the time division multiplexing of high-speed universal operating unit, and realized input switching controls butterfly computation, frequency domain filtering operational data to a plurality of memory cell data computings; External control signal 16 is synchronizing signals that outside time domain data is imported, and makes the sequential of control module and outer input data synchronous.
At first, control module 501 is sent control signal 10 to array ram 502, by of the control of this control signal to each memory cell write address operation, finishing overlapping shown in Figure 3 in time domain data 1 is input to the input process 2 of array ram 502 through input data bus handles, and each time domain data section that produces in the overlapping processing procedure is assigned to each memory cell in the array ram 502 one by one, promptly in the RAM group; Required memory space in all processing procedures of each data segment is provided by the RAM at this data segment place group.
Then, according to control module 501 to array ram 502, twiddle factor table look-up module 507, high-speed universal operating unit 505, the control signal 10 that data switching module 504 is sent respectively, 13,14,15, storage data and high-speed universal operating unit 505 in each RAM group, below be example with the butterfly processing element, 4 parallel multipliers and 6 adders can be arranged in this unit, carry out exchange at a high speed by data switching module 504, soon data are read from the RAM group and are sent into data switching module 504 by BDB Bi-directional Data Bus 5, in data switching module 504, after data are switched, needs are carried out the data of butterfly computation and carry out butterfly computation through BDB Bi-directional Data Bus 6 input butterfly processing elements 505 and the twiddle factor table look-up module 507 synchronous corresponding twiddle factors of exporting 7.Be transferred to data switching module 504 through the data after the butterfly computation processing through BDB Bi-directional Data Bus 6 and distribute, be written to corresponding RAM group in the array ram 502 through BDB Bi-directional Data Bus 5 again.According to the principle of fast Flourier computing, repeatedly repeat above process, the time domain data of former input all can be converted to frequency domain data corresponding with it, promptly finished fast fourier transform.
Then, the control signal of sending according to control module 501 10,12,14,15, corresponding filter coefficient 9 is synchronously sent into butterfly processing element 505 in frequency domain data in the corresponding RAM group and the filter coefficient storage 503, carries out the phase multiplication in this unit, finishes filtering operation.Result behind the filtering operation is admitted in the array ram 502 corresponding RAM group through data switching module 504 and stores, and prepares to carry out inverse fast fourier transform and handles.
Then, the control signal of sending according to control module 501 10,13,14,15, storage data in each RAM group are carried out exchange at a high speed by data switching module 504 and butterfly processing element 505, soon data are read BDB Bi-directional Data Bus 5 and are sent into data switching module 504 from the RAM group, in data switching module 504 after data are switched, the data of needs being carried out butterfly computation through the carrying out of BDB Bi-directional Data Bus 6 input butterfly processing elements 505 and twiddle factor table look-up module 507 output synchronously the corresponding twiddle factor 7 of conjugation after handling carry out butterfly computation.Be transferred to data switching module 504 through the data after the butterfly computation processing through BDB Bi-directional Data Bus 6 and distribute, be written to corresponding RAM group in the array ram 502 through BDB Bi-directional Data Bus 5 again.Repeatedly repeat above process, the frequency domain data of need conversion all can be converted to time domain data corresponding with it, promptly finished inverse fast fourier transform.
According to the control signal 10,11 that control module 501 is sent, the required dateout 3 of the folded processing of output reciprocal cross from corresponding RAM group; The different data segment that each memory cell is read merges in the module 506 in dateout to be handled through reciprocal cross as shown in Figure 3 is folded, and after the gain of carrying out corresponding inverse fast fourier transform result is adjusted, can obtain final time domain dateout 4, thereby reach the purpose of frequency domain filtering.
Figure 6 shows that the flow chart of data processing figure of two RAM in the RAM group.If the computational length of the Fourier transform that need carry out is 2
NIndividual data point, then the positive and negative conversion of Fourier all need be carried out the butterfly computation processing of N level.By flow chart as shown in Figure 6, the computational length of the Fourier transform that promptly need carry out with N=8 is that 256 data points are example, in a RAM group, by to two RAM operation of read-write by turns, can finish required calculation process at high speed.At last, when the data when this flow process finishes are exported, just RAM2 is carried out read operation, and the RAM1 of this moment has handled with regard to the input that can descend one piece of data.By carrying out above-mentioned flow process repeatedly, can realize high speed processing, and can effectively improve the overlapping ratio that overlaps and handle data flow.
In the dynamic frequency domain filter implementation structure schematic diagram shown in Fig. 5, about the detailed description of data switching module, by 3 memory cell independently, promptly 3 RAM groups constitute example, as shown in Figure 7 with connected array ram 502.
As shown in Figure 7, data switching module 504 is made of input selector 702, output splitter 703, input splitter 704, outlet selector 705 and two input and output switch units 701 at least at least.The number of input and output switch unit 701 equates with the number of memory cell array stores unit in the data switching module 504, and corresponding one by one with the memory cell in the memory cell array.Below describing is that array ram 502 is an example with described memory cell array all, 3 input and output switch units 701 are then arranged in the data switching module 504, and each input and output switch unit 701 respectively with array ram 502 in RAM group corresponding one by one, its effect be make with its RAM that is connected group and selector between carry out exchanges data, and guarantee that two RAM in its RAM that connects group are in the correct state that reads or writes.Input selector 702 is multiselect one modules, when 3 input and output switch units 701 are arranged in the data switching module 504, input selector 702 can be one three and select a module, and can the rest may be inferred, below is one three with input selector 702 to select a module be that example describes.The effect of this input selector 702 is according to the residing time-multiplexed state of universal operating unit, from the dateout that 3 RAM by the input/output module transmission organize, select the dateout of one of them RAM group by control signal 15, be transferred to input splitter 704, input splitter 704 judges that according to control signal 15 these data need carry out these data being given corresponding arithmetic element in the high-speed universal operating unit 505 after butterfly computation still need carry out the frequency domain filtering computing again.With high-speed universal operating unit 505 is that butterfly processing element is an example, outlet selector 705 is alternative modules, its effect is for the dateout after handling through butterfly processing element 505, at first need to judge current high-speed universal operating unit 505 residing compute modes according to control signal 15, again the frequency domain filtering dateout and the butterfly computation dateout of its output are carried out the selection of alternative, obtain required dateout, give output splitter 703 this transfer of data.Output splitter 703 is judged the time-multiplexed state of high-speed universal operating unit 505 present located according to control signal 15, organizes the input and output switch unit 701 that is connected this data allocations for the RAM that is carrying out accordingly reading and writing data again.These data are switched through the input and output of input and output switch unit 701 again, give the RAM that is responsible for storage in the current RAM group with data, finish the storage of data.Above-mentioned data switching module is controlled by above-mentioned control signal 15 respectively the switching sequence of time-multiplexed Data Control and compute mode.
The above-mentioned description to the data handover module all is to be array ram with the memory cell array, and array ram is organized the explanation that constitutes example and carry out by 3 RAM, not being array ram but constituting when memory cell array by the memory cell of other types, or the number of the RAM in array ram group is 2 or greater than 3 o'clock, the method that above-mentioned data are switched is suitable for too, just the structure of data switching module will be done correspondingly and change, to be fit to the needs that data are switched.In addition, during the structure of above-mentioned data switching module was formed, each submodule was all simpler, and just whole circuit structure need adapt to the interface requirement of array ram and time-multiplexed universal operating unit.
Based on dynamic frequency domain filter implementation structure schematic diagram shown in Figure 5, the overall sequential of data processing as shown in Figure 8 in the present invention's one specific embodiment.Point-like figure among Fig. 8 is represented time domain input data, positive inverse transformation of ordinate diagrammatic representation Fourier and frequency domain filtering computing, the filtered time domain dateout of horizontal line diagrammatic representation.In this specific embodiment, the time domain data transmission rate of input is 2.4576 megahertzes, and need carry out computational length is the fast fourier transform realization frequency domain filtering of 256 data points, and the overlapping length requirement of data is 140 data points.The time domain data transmission rate is carried out after 25 times of the frequencys multiplication speed as butterfly computation, i.e. 61.44 megahertzes.
As shown in Figure 8: when frequency domain filtering is handled beginning, RAM group 1 begins first data segment of preceding 256 data points that comprise the 1st data point of input time domain data stream is handled, be about to this section time domain data and deposit in the RAM group 1, be i.e. point-like figure in 801; After the storage of this section input time domain data is finished, the storage transfer of data in the RAM group 1 is carried out the butterfly computation of Fourier transform in the high-speed universal operating unit 505 by data switching module 504, twiddle factor module 507 is synchronously tabled look-up at this moment, provide computing required twiddle factor, operation result is deposited back in the RAM group 1; After butterfly computation disposes, high-speed universal operating unit 505 switches to the compute mode of frequency domain filtering, the also synchronous output filter coefficient of filter coefficient storage 503 this moment, carry out the computing of frequency domain filtering with the temporary butterfly computation frequency domain data afterwards in the RAM group 1 that is transferred to by data switching module 504 in the high-speed universal operating unit 505, operation result is deposited back in the RAM group 1; After filtering operation disposes, high-speed universal operating unit 505 is switched back the butterfly computation state again, frequency domain data after the filtering temporary in the RAM group 1 is carried out inverse fourier transform, obtain time domain data, operation result is deposited back in the RAM group 1, and the computing of positive inverse transformation of above Fourier and frequency domain filtering is by the ordinate diagrammatic representation in 801; The data instant of finishing after the above-mentioned processing merges module 506 by dateout, and the dateout in the RAM group 1 is selected, exported, and finishes the data output of reciprocal cross poststack, and dateout is by the horizontal line diagrammatic representation in 801.In like manner, data segment 802,803,804,805 ... processing mode identical with above-mentioned processing mode, the data of each data segment output i.e. horizontal line part of all data segments just can be synthesized the filtered output time domain data of complete process.
Processing and realization are to the time division multiplexing of High Speed General unit because overlap, so can be in the 117th data point input RAM group 1 of input time domain data stream with this data point after, the 2nd segment data that comprises 256 data points of this data point stores in the RAM group 2 promptly the point-like figure in 802 into; And in the 233rd data point input RAM group 1 of input time domain data stream, RAM group 2 with this data point after, the 3rd segment data that comprises 256 data points of this data point stores in the RAM group 3 promptly the point-like figure in 803 into; Before the time domain data input of RAM group 2 finished, the High Speed General computing module finished to the processing of storage data in the RAM group 1, can begin immediately the storage data in the RAM group 2 are handled; Simultaneously, because the data in the RAM group 1 dispose, can receive new data stores, so in the 349th data point input RAM group 2 of input time domain data stream, RAM group 3 with this data point after, the 4th segment data that comprises 256 data points of this data point stores in the RAM group 1 promptly the point-like figure in 804 again into; In like manner, before the time domain data input of RAM group 3 finished, the processing of storage data finished in 505 pairs of RAM groups 2 of High Speed General computing module, can begin immediately the storage data in the RAM group 3 are handled; Simultaneously, because the data in the RAM group 2 dispose, can receive new data stores, so in the 465th data point input RAM group 3 of input time domain data stream, RAM group 1 with this data point after, the 5th segment data that comprises 465 data points of this data point stores in the RAM group 2 promptly the point-like figure in 805 again into; And the like, carry out repeatedly in the array ram 3 RAM groups by turns, just the length that can realize overlapping is the overlapping processing of 140 data points, and, because according to this data processing method, 3 RAM groups and the Filtering Processing that high-speed universal operating unit can be rotated are repeatedly finished normal filtering operation, thereby have also been realized the time division multiplexing of high-speed universal operating unit.
In the present embodiment, positive inverse transformation of fast Flourier and frequency domain filtering computing that all data segments overlap after handling can be finished with same butterfly processing element by time-multiplexed method, realize resource thereby saved circuit widely; And, only just realized that by 3 individual memory cells overlapping percentage is 55% overlapping and the folded processing of reciprocal cross, can satisfy the performance requirement that unit impulse response is the filter on 140 rank fully; Simultaneously, this embodiment has also reduced by 70 data point sampling times, i.e. 28.5 microseconds with the group delay of frequency domain filter.
Circuit implementing scheme of the present invention and application should be including, but not limited to above-mentioned specific embodiments.Fourier transform described in the present invention is a fast fourier transform of using 2-base algorithm, in actual applications, also can use other fast fourier transformation algorithm, as basic 4 algorithms etc., the internal structure of butterfly processing element correspondingly also has corresponding adjustment; Simultaneously, described high-speed universal operating unit can be a butterfly processing element, also can be other arithmetic element; Employed overlapping, the folded treatment technology of reciprocal cross can be processing methods shown in Figure 3 among the present invention, also can be the folded processing methods of overlap-add mode or other overlapping, reciprocal cross; In addition, can be according to the difference of time domain data transmission rate, difference, the difference of overlapping percentage and the difference of butterfly computation speed that frequency domain resolution requires, change the length and the overlapping length of fast fourier transform, or increase or reduce the quantity of memory set in the memory cell array, also can increase the quantity of high-speed universal operating unit, so that at the balance point of realizing being satisfied the demands more between cost and the filter effect.Circuit implementing scheme of the present invention can be realized by dedicated IC chip, also can use programmable logic device to realize; Can be applied in the reception that comprises communication system signal, in the multiple Digital Signal Processing occasion in being transmitted in.
In sum, the present invention is the basis that circuit is realized with integrated circuit (IC) chip device (as ASIC or FPGA) at a high speed, saving resources of chip as far as possible, reducing under the prerequisite that realizes cost, solved the weak point of legacy frequencies filter structure, provide one perfect based on the positive inverse transformation of fast Flourier (FFT/IFFT) but, the implementation of the absolute filter of the filtering characteristic dynamic change of filter.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1, a kind of frequency domain filter is characterized in that: comprise that control module, memory cell array, filter coefficient storage, data switching module, twiddle factor table look-up module, dateout merge module and at least one high-speed universal operating unit; Wherein,
The time domain data that need carry out frequency domain filtering is connected to described memory cell array by data/address bus, this memory cell array will export described dateout through the time domain data that frequency domain filtering is handled to by data/address bus and merge module, the final time domain data of output after gain is adjusted;
Be connected by read/write, address signal line between described control module and the memory cell array;
Described control module connects the time domain data synchronizing signal of outside input;
Described control module dateout merging controls signal to described dateout and merges module, controls the gating and the merging of filtered time domain dateout;
Described control module output twiddle factor is tabled look-up and is controlled signal to described twiddle factor table look-up module, control its Fourier just/table look-up synchronously during inverse transformation and export corresponding twiddle factor to the high speed universal operating unit;
Described control module dateout switch-over control signal is to described data switching module, control it to gatings of memory cell array I/O data and to the switching of computing of high-speed universal operating unit Fourier and frequency domain filtering operational data, all link to each other between memory cell array and data switching module and data switching module and the high-speed universal operating unit by BDB Bi-directional Data Bus;
Described control module output state controls signal to described high-speed universal operating unit, controls the switching of its Fourier computing and frequency domain filtering compute mode.
2, frequency domain filter according to claim 1 is characterized in that: described memory cell array is made of at least two memory cell.
3, frequency domain filter according to claim 1 is characterized in that: described memory cell array is an array ram.
4, frequency domain filter according to claim 2 is characterized in that: described memory cell is the RAM group that is made of at least 2 RAM.
5, frequency domain filter according to claim 1 is characterized in that: described filter coefficient storage is made of at least one RAM.
6, frequency domain filter according to claim 1 is characterized in that: described high-speed universal operating unit is a butterfly processing element.
7, frequency domain filter according to claim 1 is characterized in that: described data switching module is made of input selector, outlet selector, input splitter, output splitter and two input and output switch units at least at least; Described input and output switch unit equates on number with memory cell in the memory cell array, and it is corresponding one by one, and each input and output switch unit connects by the BDB Bi-directional Data Bus memory cell corresponding with it respectively, one circuit-switched data output of each input and output switch unit all is connected to described input selector, and a circuit-switched data input of each input and output switch unit all is connected to described output splitter; The data output end of input selector connects described input splitter; The two paths of data output of input splitter connects described high-speed universal operating unit; The two paths of data input of outlet selector connects described high-speed universal operating unit, and the data output end of outlet selector connects described output splitter.
8, frequency domain filter according to claim 1; it is characterized in that: described control module is further exported synchronous control signal to described filter coefficient storage; control it and be in write-protect during use; in idle period of time cancellation write-protect, can carry out the renewal of filter coefficient.
9, a kind of method that realizes frequency domain filtering is characterized in that may further comprise the steps:
Each section time domain data that respectively needs is carried out frequency domain filtering overlaps and is stored in each memory cell of a memory cell array;
The time domain data of each section overlapping of said memory cells array stores is carried out Fourier transformation computation, frequency domain filtering computing, inverse fourier transform computing respectively in different time sections in same high-speed universal operating unit, and will be stored in again in each memory cell of memory cell array through the time domain data after the above-mentioned Filtering Processing;
Select to read the time domain data after the Filtering Processing in above-mentioned each memory cell that is stored in memory cell array successively, carry out simultaneously that reciprocal cross is folded to be handled, merge output and obtain final time domain data; And,
To one section time domain data before the storage of memory cell array one memory cell is finished, high-speed universal operating unit to the overlapping of memory cell array previous storage unit storage the last period time domain data the inverse fourier transform computing finish.
10, frequency domain filtering method according to claim 9 is characterized in that: the time domain data after the folded processing of reciprocal cross is further gained to adjust handle.
11, frequency domain filtering method according to claim 9 is characterized in that further comprising that the filter factor to described frequency domain filtering computing upgrades.
12, frequency domain filtering method according to claim 9, it is characterized in that: when one section overlapping time domain data of a cell stores in the memory cell array was carried out Fourier transformation computation, frequency domain filtering computing and inverse fourier transform computing in high-speed universal operating unit, read and the writing of operation result of its operational data is alternating in two memories of memory cell carried out simultaneously.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031465927A CN100518043C (en) | 2003-07-08 | 2003-07-08 | A frequency domain filter and method for implementing frequency domain filter |
| RU2006103625/09A RU2308153C2 (en) | 2003-07-08 | 2004-07-05 | Frequency filter and method for filtration in frequency area |
| PCT/CN2004/000749 WO2005004345A1 (en) | 2003-07-08 | 2004-07-05 | A frequency-domain filter and method for realizing frequency-domain filtering |
| BRPI0412405-7A BRPI0412405B1 (en) | 2003-07-08 | 2004-07-05 | Frequency domain filtering and method for frequency domain filtering |
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| CNB031465927A CN100518043C (en) | 2003-07-08 | 2003-07-08 | A frequency domain filter and method for implementing frequency domain filter |
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| CN100518043C CN100518043C (en) | 2009-07-22 |
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| CN (1) | CN100518043C (en) |
| BR (1) | BRPI0412405B1 (en) |
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| WO (1) | WO2005004345A1 (en) |
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| CN101826853A (en) * | 2009-03-03 | 2010-09-08 | 美国博通公司 | The method and system of unconstrained frequency domain adaptive filtering |
| CN101931381A (en) * | 2009-06-19 | 2010-12-29 | 富士通株式会社 | Digital signal processing device and digital signal processing method |
| CN101478525B (en) * | 2009-02-04 | 2011-03-30 | 北京天碁科技有限公司 | Method for multi-carrier separation and multi-carrier separation apparatus |
| CN103270697A (en) * | 2010-12-21 | 2013-08-28 | 日本电气株式会社 | Digital filter circuit and digital filter control method |
| CN107942298A (en) * | 2017-11-03 | 2018-04-20 | 西安电子科技大学 | The low velocity target detection device and method of a kind of user's configurable parameter |
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| US4951269A (en) * | 1986-10-30 | 1990-08-21 | Fujitsu Limited | Echo canceller with short processing delay and decreased multiplication number |
| DE4328139A1 (en) * | 1993-08-21 | 1995-02-23 | Philips Patentverwaltung | Circuit arrangement for echo cancellation |
| US5612978A (en) * | 1995-05-30 | 1997-03-18 | Motorola, Inc. | Method and apparatus for real-time adaptive interference cancellation in dynamic environments |
| US5606735A (en) * | 1995-06-29 | 1997-02-25 | Harris Corporation | Slope equalizer using baseband detection |
| JP4499240B2 (en) * | 2000-03-23 | 2010-07-07 | 富士通株式会社 | Signal processing filter system |
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- 2004-07-05 WO PCT/CN2004/000749 patent/WO2005004345A1/en active Application Filing
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| CN101478525B (en) * | 2009-02-04 | 2011-03-30 | 北京天碁科技有限公司 | Method for multi-carrier separation and multi-carrier separation apparatus |
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| CN109716664A (en) * | 2016-10-10 | 2019-05-03 | 华为技术有限公司 | Comb filtering noise cancellation method, device and frequency domain adaptive balancer |
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| CN107979355A (en) * | 2017-12-22 | 2018-05-01 | 西安烽火电子科技有限责任公司 | A kind of FIR filter and its filtering method |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2005004345A1 (en) | 2005-01-13 |
| CN100518043C (en) | 2009-07-22 |
| BRPI0412405B1 (en) | 2018-02-14 |
| RU2308153C2 (en) | 2007-10-10 |
| BRPI0412405A (en) | 2006-09-05 |
| RU2006103625A (en) | 2006-06-10 |
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