CN1555603A - 一种基于伴随式的乘积码迭代译码方法及装置 - Google Patents

一种基于伴随式的乘积码迭代译码方法及装置 Download PDF

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Publication number
CN1555603A
CN1555603A CNA028181204A CN02818120A CN1555603A CN 1555603 A CN1555603 A CN 1555603A CN A028181204 A CNA028181204 A CN A028181204A CN 02818120 A CN02818120 A CN 02818120A CN 1555603 A CN1555603 A CN 1555603A
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CN
China
Prior art keywords
decoding
syndrome
soft
value
module
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Pending
Application number
CNA028181204A
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English (en)
Inventor
李宗旺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Linkair Communications Inc
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Linkair Communications Inc
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Publication date
Application filed by Linkair Communications Inc filed Critical Linkair Communications Inc
Publication of CN1555603A publication Critical patent/CN1555603A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1134—Full parallel processing, i.e. all bit nodes or check nodes are processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2909—Product codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

本发明提供了一种基于伴随式的乘积码迭代译码方法及装置，通过一系列高速并行算法处理，即：优化的二维快速排序处理、基于查表的q－模式搜索处理、和外部信息值的快速计算处理，以使硬件高速实现乘积码的迭代译码，从而实现高速数据通信。

Description

PCT国内申请，说明书已公开。

Claims (1)

  1. PCT国内申请，权利要求书已公开。
CNA028181204A 2002-07-01 2002-07-01 一种基于伴随式的乘积码迭代译码方法及装置 Pending CN1555603A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2002/000457 WO2004004132A1 (fr) 2002-07-01 2002-07-01 Procede et appareil de decodage iteratif pour code de produit fonde sur une formule adjointe

Publications (1)

Publication Number Publication Date
CN1555603A true CN1555603A (zh) 2004-12-15

Family

ID=29783999

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA028181204A Pending CN1555603A (zh) 2002-07-01 2002-07-01 一种基于伴随式的乘积码迭代译码方法及装置

Country Status (3)

Country Link
CN (1) CN1555603A (zh)
AU (1) AU2002320749A1 (zh)
WO (1) WO2004004132A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104022786A (zh) * 2014-05-21 2014-09-03 上海宏光经济信息发展中心青岛电子技术部 乘积码译码方法
CN114050898A (zh) * 2021-11-08 2022-02-15 南京理工大学 基于hls和ldpc码构建的qkd协商方法
CN117976021A (zh) * 2024-04-01 2024-05-03 陕西中安数联信息技术有限公司 多数据块联合ldpc编码的数据存储方法与系统

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9391641B2 (en) * 2013-04-26 2016-07-12 SK Hynix Inc. Syndrome tables for decoding turbo-product codes

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2712760B1 (fr) * 1993-11-19 1996-01-26 France Telecom Procédé pour transmettre des bits d'information en appliquant des codes en blocs concaténés.
FR2756996A1 (fr) * 1996-12-10 1998-06-12 Philips Electronics Nv Systeme et procede de transmission numerique comportant un code produit combine a une modulation multidimensionnelle
FR2778289B1 (fr) * 1998-05-04 2000-06-09 Alsthom Cge Alcatel Decodage iteratif de codes produits
JP2002526965A (ja) * 1998-09-28 2002-08-20 アドバンスト ハードウェア アーキテクチャーズ，インコーポレイテッド ターボプロダクト符号復号器

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104022786A (zh) * 2014-05-21 2014-09-03 上海宏光经济信息发展中心青岛电子技术部 乘积码译码方法
CN104022786B (zh) * 2014-05-21 2017-09-01 上海宏光经济信息发展中心青岛电子技术部 乘积码译码方法
CN114050898A (zh) * 2021-11-08 2022-02-15 南京理工大学 基于hls和ldpc码构建的qkd协商方法
CN117976021A (zh) * 2024-04-01 2024-05-03 陕西中安数联信息技术有限公司 多数据块联合ldpc编码的数据存储方法与系统

Also Published As

Publication number Publication date
AU2002320749A1 (en) 2004-01-19
WO2004004132A1 (fr) 2004-01-08

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