AU2002320749A1 - Iterative decoding method and apparatus for product code based on adjoint formula - Google Patents
Iterative decoding method and apparatus for product code based on adjoint formulaInfo
- Publication number
- AU2002320749A1 AU2002320749A1 AU2002320749A AU2002320749A AU2002320749A1 AU 2002320749 A1 AU2002320749 A1 AU 2002320749A1 AU 2002320749 A AU2002320749 A AU 2002320749A AU 2002320749 A AU2002320749 A AU 2002320749A AU 2002320749 A1 AU2002320749 A1 AU 2002320749A1
- Authority
- AU
- Australia
- Prior art keywords
- decoding method
- product code
- code based
- iterative decoding
- adjoint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1134—Full parallel processing, i.e. all bit nodes or check nodes are processed in parallel
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2909—Product codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2948—Iterative decoding
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2002/000457 WO2004004132A1 (en) | 2002-07-01 | 2002-07-01 | Iterative decoding method and apparatus for product code based on adjoint formula |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2002320749A1 true AU2002320749A1 (en) | 2004-01-19 |
Family
ID=29783999
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2002320749A Abandoned AU2002320749A1 (en) | 2002-07-01 | 2002-07-01 | Iterative decoding method and apparatus for product code based on adjoint formula |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN1555603A (en) |
AU (1) | AU2002320749A1 (en) |
WO (1) | WO2004004132A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9391641B2 (en) * | 2013-04-26 | 2016-07-12 | SK Hynix Inc. | Syndrome tables for decoding turbo-product codes |
CN104022786B (en) * | 2014-05-21 | 2017-09-01 | 上海宏光经济信息发展中心青岛电子技术部 | Product code coding method |
CN114050898A (en) * | 2021-11-08 | 2022-02-15 | 南京理工大学 | QKD negotiation method constructed based on HLS and LDPC codes |
CN117976021B (en) * | 2024-04-01 | 2024-06-11 | 陕西中安数联信息技术有限公司 | Data storage method and system for multi-data block combined LDPC coding |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2712760B1 (en) * | 1993-11-19 | 1996-01-26 | France Telecom | Method for transmitting bits of information by applying concatenated block codes. |
FR2756996A1 (en) * | 1996-12-10 | 1998-06-12 | Philips Electronics Nv | DIGITAL TRANSMISSION SYSTEM AND METHOD COMPRISING A PRODUCT CODE COMBINED WITH MULTI-DIMENSIONAL MODULATION |
FR2778289B1 (en) * | 1998-05-04 | 2000-06-09 | Alsthom Cge Alcatel | ITERATIVE DECODING OF PRODUCT CODES |
WO2000019616A2 (en) * | 1998-09-28 | 2000-04-06 | Advanced Hardware Architectures, Inc. | Turbo product code decoder |
-
2002
- 2002-07-01 WO PCT/CN2002/000457 patent/WO2004004132A1/en not_active Application Discontinuation
- 2002-07-01 CN CNA028181204A patent/CN1555603A/en active Pending
- 2002-07-01 AU AU2002320749A patent/AU2002320749A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO2004004132A1 (en) | 2004-01-08 |
CN1555603A (en) | 2004-12-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |