CN1553672A - Data packet multiplexing receiving controlled apparatus and data receiving method - Google Patents
Data packet multiplexing receiving controlled apparatus and data receiving method Download PDFInfo
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- CN1553672A CN1553672A CNA031318088A CN03131808A CN1553672A CN 1553672 A CN1553672 A CN 1553672A CN A031318088 A CNA031318088 A CN A031318088A CN 03131808 A CN03131808 A CN 03131808A CN 1553672 A CN1553672 A CN 1553672A
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Abstract
This invention is relative to a data package multiplex receiving controlled device and its method for receiving data. It comprises: the PHY process module, the receiving control module, the PROA response module, the CPU setting up module and the up stream buffer module. Design the data length counter in the PHY process module. The PHY process module identifies the packet header, the packet tail, and distinguishes if the AbortSequence coding is at the packet tail to decide if the abandoned messages are saved into up stream buffer. The data of each channel packet and the relevant messages are stored into the up stream module. The up stream module sends the state information about data storage to the PRPA response module, through thresholding , direct indication or address enquiry the state is reported to the master controller.
Description
Technical field
The present invention relates to data communication field, specifically, relate to the packet up direction multiplexing receiving slave device circuit arrangement of a link layer (Link Layer) device, the method for particularly a kind of packet multiplexing receiving slave device and Data Receiving to a plurality of physical layers (PHY Layer) device.
Background technology
In recent years, the fast development of Internet impels the IP technology all to obtain huge progress on network configuration, transmittability still are business development.IP is a network layer protocol, and SDH and WDM are the physical layer tranmission techniques, needs a data link layer between two-layer, and data link layer is responsible for the conversion of signals that physical layer provides is become the needed signal of network layer.At present, most popular IP tranmission techniques has three kinds, i.e. IP overATM, IP over SDH/SONET and IP over WDM.
Wherein, IP over SDH/SONET is with the physical transfer network of SDH network as the IP packet, and it uses link and PPP (Point-to-Point Protocol, peer-peer protocol) agreement that the IP packet is encapsulated.IP grouping is inserted into message segment in the PPP frame simply according to the RFC1662 standard, and then is mapped in the SDH synchronous payload by the service adapter of the SDH channel layer IP packet after encapsulation.Downward then, through SDH transport layer and section layer, add corresponding expense, payload is packed in the SDH frame, arrive photosphere at last, in optical fiber, transmit.
IP over SDH also claims Packet over SDH (POS), and it has kept IP towards connectionless characteristic.Abroad, usually IP over SDH is called IP over SONET/SDH.SONET is meant Synchronous Optical Network (Synchronous Optical Network), it at first grows up in the U.S., form by a whole set of graduate standard digital transfer structure, being suitable for various net loads through adaptation processing (Payload refers to can be used in the network bit stream part of telecommunication service) transmits on physical medium.1998, CCITT (present ITU-T) has accepted the notion of SONET, and rename into SDH (SynchronousDigital Hierarchy), make it to become and be not only applicable to Optical Fiber Transmission and simultaneously also be applicable to the current techique of microwave and satellite transmits, and promote it and become worldwide standard on the Digital Transmission system.SONET and SDH standard are slightly variant, but both basic principles are identical, and standard is also compatible.
SDH is based on the time-multiplexed net that semipermanent connects of finishing under the configuration of webmaster.In IP overSDH, SDH only has a kind of working method, and promptly SDH only may support IP network with link mode.SDH supports IP network as link, because it can not participate in the IP network addressing, its effect just couples together the mode of router with point-to-point, improves the transfer rate between the point-to-point, it can not improve the performance of IP network on the whole, and it is still a router net in essence this IP network.The raising of IP network overall performance will depend on whether router technology has breakthrough.Gigabit router has breakthrough technically, but the breakthrough of technology has caused the raising of equipment complexity.Because this disruptive technology can not be widely used in the ordinary router at present, unless the whole routers of the whole network all adopt gigabit router (IP over SDH), otherwise just can not improve the level of IP network on the whole.In addition, SDH relies on webmaster to finish the configuration of semipermanent connection end to end, and it is inconceivable that a big net relies on webmaster to finish configuration fully.So gigabit router (IP over SDH) only may be on main line usefulness, in order to dredge high-rate data stream.
Packet Over Sonet (POS) Level 2 agreements are about packet (HDLC in the data packet transmission system, PPP, Frame Relay) multiplexing agreement, it has stipulated the interface relationship between 1 link layer (Link Layer) device and a plurality of physical layer (PHY Layer) device.
Fig. 1 is the structure chart of fundamental relation between physical layer device and the link layer device, this transmission system comprises 1 link layer device and 1 physical layer device that 4 passages are arranged, main interface signal between physical layer device and the link layer device has totally 12 kinds of RFCLK, PRPA, RVAL, DRPA, RADR, RENB, RERR, REOP, RSOP, RMOD, RPRTY and RDAT, and packet is transferred to the link layer device from physical layer device under the control of these signals.
Understand for convenient, introduce the implication of above-mentioned 12 kinds of interface signals below.
The RFCLK signal is the clock signal of link layer device and physical layer device interface, the rising edge link layer device of RFCLK signal will from the physical layer device packet leave in the memory cell of link layer device.
There is signal in PRPA inquiry channel data bag, after physical layer device is received inquire address from the link layer device, related physical layer device clockwise link layer device when the next one sends this signal, in order to tell link layer device physics layer memory cell whether packet is arranged.The PRPA signal comprises three kinds of situations, and when having packet, this signal is a high level; When receiving invalid inquire address, this signal is a high resistant; When not having packet, keep low level.
RVAL transmits channel data and is surrounded by the effect signal, when packet transmits, whether the data of this signal indication current physical layer channel transfer to the interface bus are as RERR, REOP, RSOP, RMOD, RPRTY and RDAT, effective.The RVAL signal comprises three kinds of situations, and when the packet of current physical layer channel transfer was effective, this signal was a high level; When the REND signal is height or physical layer when receiving invalid inquire address, this signal is a high resistant; When the packet of current physical layer channel transfer was invalid, promptly physical layer FIFO had been empty, and this signal keeps low level.
There is direct index signal in DRPA channel data bag, each passage of physical layer can have a DRPA[x] holding wire (x represents channel number) links to each other with the link layer device, the DRPA signal is a high level, represent that this passage memory cell has packet, the DRPA signal is a low level, represents that this passage memory cell does not have packet.
The RADR signal is 5 bit address buses between link layer device and the physical layer device, is to be used for the link layer device physical layer device is inquired about, and when address that physical layer device obtains being complementary, just gives the link layer device with the PRPA signal feedback.The RADR signal comprises two kinds of outputs, and a kind of is the address of the physical layer device inquired about, and another kind is inserted in the 1F signal between the address of physical layer device between being.
The RENB signal is the transfer of data enable signal, and is effective when low level; Represent when this signal is effective that the link layer device carries out transfer of data with physical layer, otherwise represent that then data/address bus is in idle condition, can handle at any time and wait the packet sent out.
The RERR signal is a misdata bag index signal, and what represent current transmission during for high level when it is error data packets, must be dropped; When it represents that the packet of current transmission does not have mistake during for low level.Only it is just effective when the last character of transfer data packets.
The REOP signal is the transfer data packets end signal, and what represent current transmission during for high level when it is the last character or the byte of packet.
The RSOP signal is the transfer data packets commencing signal, and what represent current transmission during for high level when it is first word of packet.
The RMOD signal is a transfer data packets byte index signal, when it represents that the most-significant byte of 16 position datawires is effective during for high level; When it represents that 16 position datawires are all effective during for low level.Only it is just effective when the last character of transfer data packets.
The RPRTY signal is a data/address bus parity check index signal, and it is that the packet on the data bus is done parity check, can be configured to odd or even parity check, and when to have only RENB be low, the data of RPRTY just effectively.
The RDAT signal is the data/address bus that is used for transmitting from the packet of physical layer device, and physical layer device sends to corresponding data in the memory cell of link layer device by this data/address bus.
Fig. 2 has provided link layer device and the sequential relationship of physical layer device between byte level transmission means lower interface signal.Before clock 1, the DRPA[0 of physical layer device] signal is high, tells its memory cell of link layer device to have the data of a packet or its storage to surpass predetermined threshold value.The link layer device is put the low data of will carrying out at clock 2 with the RENB signal and is transmitted, physical layer device detects the RENB signal when low at clock 3, data at data/address bus after the RVAL signal put height and show all are effective, physical layer device is put height with the RSOP signal simultaneously, and what represent this bat transmission is first word of packet.At clock 13 physical layer devices the REOP signal is put height, what represent this bat transmission is the last character or the byte of packet.Clock 14 physical layer devices are put the RVAL signal low, and the data after the expression on data/address bus all are invalid.Because packet is different in size, the link layer device will detect RVAL at clock 15 and know just that for low this time transmission finishes, clock 14 is called the fixed cycle (Dead Cycle), POS Level 2 agreement regulation link layer devices can detect the RVAL one-period again, both at clock 16 RENB are put height and finish this secondary data transmission.
More than be to the basic description of link layer device and physical layer device input/output interface in POS Level 2 agreements, this agreement has only been stipulated the interface mode between physical layer device and the link layer device, sequential characteristics etc., do not provide its inner concrete structure, and the conversion between passage and the passage, agreement does not stipulate whether the fixed cycle (Dead Cycle) will be arranged yet, and in addition, the applicant does not find the document of the specific implementation method of relevant pos interface standard yet by retrieval.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of packet multiplexing receiving slave device and data receive method, can realize the up direction packet multiplexing from the physical layer to the link layer, finishes the exchanges data between user and the wideband data.
The invention discloses a kind of packet multiplexing receiving slave device, comprise the PHY processor module, receive control module, address decoding and latch module, PRPA respond module, CPU configuration module and up buffer module;
Described PHY processor module, identification packet packet header, whether packet bag tail and data packet byte number surpass control informations such as predetermined threshold value, then with packet and relevant information, deposit in the up buffer module corresponding address;
Described reception control module, the channel selecting signal that receiver address decoding and latch module are sent here, the control signal of detection main controller is put into packet and the relevant information that is stored in related channel program in the up buffer module on the POS-PHY bus;
Described address decoding and latch module with the signal interpretation on the address bus, as the foundation of selecting up buffer memory cell, are lived the transmission channel address latch before the transmission data;
Described PRPA respond module, channel selecting signal and each memory cell data bag store status signal of up buffer module that receiver address decoding and latch module are sent here produce the PRPA signal and return to main controller, the effective address inquiry of response main controller;
Described CPU configuration module, this module can be visited and prepare to cpu i/f, and the long word joint number and the shortest word joint number of packet can be set, and the corresponding relation of passage and external address can be set;
Described up buffer module, by channel address relevant informations such as packet and packet packet header, packet bag tail are deposited in the memory cell, the channel selecting signal that receiver address decoding and latch module are sent here reads data in the respective memory unit address by receiving control module.
Described up buffer module can be further divided into passage write control logic submodule, the memory cell submodule, and synchronous logic submodule and passage are read the control logic submodule;
Described passage write control logic submodule is pressed memory unit address with packet and relevant information write storage unit submodule;
Described memory cell submodule comprises and the identical buffer of physical layer device passage number, the packet and the relevant information that are used to store the corresponding physical layer device; Described buffer can adopt RAM to constitute;
Described synchronous logic submodule will be write logical pointer and read logical pointer and do synchronous conversion in cross clock domain, to produce the store status signal;
Described passage is read the control logic submodule, by memory unit address packet and relevant information read from the memory cell submodule, and will be through the output of the store status signal synchronously.
The invention also discloses a kind of packet demultiplexing receiving slave device and carry out the method for Data Receiving, may further comprise the steps at least:
(1) the data length register is designed in the PHY processor module, PHY processor module identification packet packet header, packet bag tail, and debate knowledge at packet bag tail whether Abort Sequence coding is arranged, whether will abandon information with decision and deposit in the up buffer module appropriate address;
(2) each channel data bag data and corresponding information deposit up buffer module in;
(3) up buffer module is given PRPA respond module with the state information of storage, through threshold process, perhaps directly indicates or the process address lookup, reports state to main controller.
Described packet demultiplexing method of reseptance is characterized in that step (3) also comprises the steps:
(a) the PRPA respond module judges that whether the byte number of the packet that storage one complete data packet or memory space can store that whether has living space memory cell has surpassed CPU configuration module predetermined threshold value, produces PRPA and DRPA[x then] signal;
(b) address decoding and latch module become corresponding channel address to the address decoding on the address wire TADR, give the criterion of PRPA respond module as output PRPA signal multiselect one; A timeticks before data packet transmission pins the address on the address wire TADR simultaneously, gives the reception control module after passage decoding, as the foundation that writes channel data;
(c) when main controller and controlled device reach receive agreement after, the reception control module of controlled device detects the TENB signal that main controller sends, and reads packet data and relevant information in the up buffer module by corresponding channel address then.
Described packet demultiplexing method of reseptance, the described predetermined threshold value of step (a) comprises the shortest threshold value of setting data bag and the longest threshold value.
Described data receive method, when the PHY processor module detects current data packet less than the shortest threshold value, the information that just will abandon deposits up buffer module in; When the PHY processor module detects current data packet greater than threshold value, the information that also will abandon deposits up buffer module 10 in, will abandon greater than the data packet byte of threshold value afterwards.
Described data receive method comprises also in the step (2) that up buffer module will carry out the adjustment of asynchronous read and write pointer.
Described data receive method, step (3) back is further comprising the steps of: read to enable and channel address, each timeticks by receiving the control module input, up buffer module is given the reception control module from memory cell read data packet data and relevant information.
Described data receive method, transmission means are divided into two kinds: byte level load mode and packet level load mode.
Described data receive method is in the byte level load mode, by DRPA[x] signal is directly to the state of each channel data storage of main controller indication controlled device; In packet level load mode, by address decoding and latch module input channel address decoding, the PRPA respond module is responded the state of each channel data storage of controlled device through multiselect one to main controller by the PRPA signal.
Described data receive method is done parity check to packet data when step (c) is carried out, if the result on gained parity check result and the TPRTY holding wire is inconsistent, just produces warning information and reports the configuration module to CPU.
Described data receive method, main controller and controlled device increase an interface signal, make external physical layer device be increased to 32.
The invention provides packet multiplexing receiving slave device, satisfy POS level 2 interface standards, support HDLC, PPP, the multiplex protocol of several data bags such as Frame Relay.The present invention adopts sheet internal channel conversion transmission back-to-back in addition, eliminates the bandwidth that the fixed cycle (Dead Cycle) takies.In addition, POS level2 interface standard is supported 31 physical layer devices of 1 link layer device butt joint, and the present invention increases an interface signal, and it is selected to make this interface can be used as 32 physical layer devices.The present invention can adopt FPGA or application-specific integrated circuit (ASIC) to realize.
Description of drawings
The structure chart of Fig. 1 POS level 2 interface protocol physical layer devices and link layer device fundamental relation;
Fig. 2 physical layer device and link layer device are at the timing diagram of byte level transmission means interface signal;
Fig. 3 packet multiplexing receiving slave of the present invention device circuit structure diagram;
The up buffer module circuit structure diagram of Fig. 4 the present invention;
Transmission time sequence figure back-to-back in Fig. 5 byte level transmission means of the present invention sheet;
Fig. 6 packet level of the present invention transmission means sequential chart;
Fig. 7 the present invention is as the 32nd PHY device sequential chart.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
Fig. 1 is the structure chart of fundamental relation between POS level 2 interface protocol physical layer devices and the link layer device.The link layer device is a main controller, and physical layer device is a controlled device.Physical layer device has 4 passages among the figure, and just chip integration has become 4 PHY devices.If carry out byte level transmission, DRPA[4:1] signal indicates the store status of these 4 channel data bags respectively.If carry out the transmission of packet level, main controller is by RADR[4:0] inquire address, controlled device PRPA signal is responded the store status of channel data bag at following 1 timeticks.All signals of interface are all sampled at the rising edge of clock RFCLK, thereby for physical layer device and the necessary homology of link layer device clock, it can be sent by main controller, also can be introduced by system.The data-bus width of interface is 16, thereby to need the whole word of RMOD signal designation data bus when the packet tail transmits still be that most-significant byte is effective.
Fig. 2 is physical layer device and the sequential relationship of link layer device between byte level transmission means lower interface signal.Carrying out single data to transmit RADR[4:0 because be to list] address bus can fix on the fixed level.DRPA[0] signal is indicated the memory state of controlled device data in storage unit bag, and whether the data on the data/address bus are effective in the transmission of RVAL signal indication current data.At clock 13, it is high signal that controlled device is sent out REOP to main controller, and on the expression data/address bus is packet the last character or byte.At this moment, RMOD and RERR signal are just effective.The RMOD signal is that the most-significant byte data are effective on the high expression data/address bus, the RMOD signal on the low expression data/address bus 16 all effective; The RERR signal should be dropped for the current packet that transmits of high expression, and the RERR signal should be retained for the current packet that transmits of low expression.
Fig. 3 packet multiplexing receiving slave of the present invention device circuit structure diagram.Packet multiplexing receiving slave device circuit comprises PHY processor module 1,2,3,4, receives control module 14, address decoding and latch module 11, PRPA respond module 12, CPU configuration module 13 and up buffer module 10.
Because length of data package can not be pre-estimated, come to the packet computational length so can not on the interface corresponding, design the numeration module with main controller.The present invention with the data packet length Counter Design in PHY processor module 1,2,3,4, PHY processor module 1,2,3,4 is responsible for identification packet packet header byte simultaneously, packet bag trail byte, and whether the 7D-7E digital coding is arranged in the identification of packet bag tail, determine whether the information of abandoning is deposited in the up buffer module 10 corresponding addresses.Can visit CPU configuration module 13 by cpu i/f, short, the longest threshold value of setting data bag.When PHY processor module 1,2,3,4 detects current data packet less than threshold value, the information that just will abandon deposits up buffer module 10 in; When PHY processor module 1,2,3,4 detects current data packet greater than threshold value, the information that also will abandon deposits up buffer module 10 in, will abandon greater than the data packet byte of threshold value afterwards.
For up buffer module 10, each passage deposits packet data and corresponding information in.Owing to be cross clock domain work, up buffer module 10 will carry out the adjustment of asynchronous read and write pointer, and specifically we introduce in detail in conjunction with Fig. 4.The memory cell that up buffer module is 10 li can be given PRPA respond module 12 with the state information of storage,, or is directly referred to not or through address lookup, reports state to main controller through threshold process by PRPA respond module 12.Read to enable and channel address by receiving control module 14 inputs, each timeticks, up buffer module 10 can be given and receive control module 14 from memory cell read data packet data and relevant information.
PRPA respond module 12 is from the state information of up buffer module 10 input storage, judge that then whether memory cell has the byte number of a complete data packet or packet whether to surpass 13 predetermined threshold value of CPU configuration module, produces PRPA and DRPA[x then] (x represents channel number) signal.In the byte level load mode, by DRPA[x] signal is directly to the state of each channel data storage of main controller indication controlled device; In packet level load mode, by address decoding and latch module 11 input channel address decodings, PRPA respond module 12 is responded the state of each channel data storage of controlled device through multiselect one to main controller by the PRPA signal.
Address decoding on 11 couples of address wire RADR of address decoding and latch module becomes corresponding channel address, gives the criterion of PRPA respond module 12 as output PRPA signal multiselect one.Simultaneously a timeticks before data packet transmission (the both timeticks of RENB before by high step-down) pins the address on the address wire RADR, gives after passage decoding and receives control module 14, as the foundation of fetch channel data.
After main controller and controlled device were reached delivery protocol, the reception control module 14 of controlled device detected the RENB signal that main controllers send, and is read the packet data and the relevant information of 10 li of up buffer modules then by corresponding channel address; Then packet packet header, packet bag tail and the information that whether abandons are mapped with corresponding data packet byte; Do parity check for simultaneously 16 bit data bag data; Send packet relevant information and data to main controller by RSOP, REOP, RERR, RMOD, RPRTY and RDAT signal at last.
Fig. 4 is the up buffer module circuit structure diagram of the present invention.It is divided into passage write control logic submodule 203, memory cell submodule 201, and synchronous logic submodule 202 and passage are read control logic submodule 204.
Memory cell submodule 201 comprises the buffer identical with the controlled device port number, and it presses channel address storage respective channel packet data and relevant information, can adopt RAM to realize.
Logical pointer is write in passage write control logic submodule 203 control store unit, by the control of PHY processor, packet data and relevant information is write in the appropriate address of respective channel; The read pointer after clock synchronization that passage write control logic submodule 203 inputs are simultaneously sent here by synchronous logic submodule 202, whether line buffer produces on the data and overflows in the judgement, then to 13 reports of CPU configuration module.
Passage is read control logic submodule 204 control store unit and is read logical pointer, by receiving control module 14 controls, packet data and relevant information is read from the appropriate address of respective channel; Passage is read the write pointer after clock synchronization that 204 inputs of control logic submodule are sent here by synchronous logic submodule 202 simultaneously, produce the situation of each passage memory cell data bag storage, give PRPA respond module 12 as producing the foundation of responding main controller inquiry PRPA signal these signals; Relatively read and write pointer, whether line buffer produces under the data and overflows in the judgement, then to 13 reports of CPU configuration module.
Because up buffer module 10 is operated in the cross clock domain, in order to eliminate the not stationary state of logic that asynchronous clock domain produces, the present invention sets up synchronous logic submodule 202 to do the clock synchronization logic.Be specially the read pointer of reading clock generating with the register secondary sampling of writing clock control, give passage write control logic submodule 203 read pointer synchronously; The same sampling with the register secondary of reading clock control write the write pointer of clock generating, gives passage with synchronous write pointer later and reads control logic submodule 204.
Fig. 5 is transmission time sequence figure back-to-back in the byte level transmission means sheet of the present invention.Because length of data package is uncertain, so when transfer of data, main controller will detect the RVAL signal of controlled device and determine whether this data transfer finishes.Detect the RVAL signal of controlled device by high step-down as main controller, the RENB signal can be drawn high by low then, as the clock 14 of Fig. 2, or because the data channel switching, need to insert an empty reason layer address cycle, this clock cycle is called the fixed cycle (Dead Cycle).If but the several passages of controlled device are integrated in the same IC, when controlled device and main controller transfer of data are switched at these several passages, whether need the fixed cycle (Dead Cycle), the POS-PHY interface protocol is not done regulation.In order to improve bandwidth, supporting pieces internal channel conversion of the present invention transmission back-to-back.As Fig. 5, passage 1 and passage 2 are in an IC, and passage 3 and passage 4 are in another IC.Main controller and controlled device passage 1 carry out transfer of data before the clock 1, think the switch data passage at clock 4 main controllers, thereby on address wire RADR, provide the address of passage 2, controlled device detects the variation of channel address at clock 5, do not need the fixed cycle wait of (Dead Cycle), immediately passage is switched to passage 2, finish sheet internal channel conversion transmission back-to-back.Therefore memory cell at clock 7 passages 3 has stored enough packets into, with DRPA[3] signal puts height.Main controller is want data transmission channel is switched to passage 3 at clock 9, and the RENB signal was drawn high the end of by, provides empty reason layer address IF simultaneously on address wire; The IC at passage 2 places is driven into high-impedance state with all output signal RDAT, RVAL, RSOP, REOP, RMOD, RERR and RPRTY etc. after clock 10 detects; Clock 11, the IC at passage 3 places detects the channel selecting address, and all output signals are driven into fixed level.Data/address bus outside the sheet is driven into high-impedance state and another IC is driven into data/address bus outside the sheet logic conflict that fixed level causes simultaneously for fear of an IC, needs a fixed cycle (DeadCycle) so the present invention is switched at the sheet outer tunnel.
Fig. 6 is a packet level transmission means sequential chart of the present invention.Before clock 1, the multiplexing receiving slave device of main controller and the present invention passage A carries out transfer of data.At clock 1, clock 3 and clock 5, multiplexing receiving slave device passage A, B and C respond the inquiry of main controller, drive the PRPA signal respectively.At clock 7, multiplexing controlled device is drawn high the REOP signal by low, and expression this moment is corresponding on data/address bus RDAT to be last data of packet.At clock 8, multiplexing receiving slave device is put the RVAL signal low by height, indicate to finish this data transfer to main controller.Main controller finishes this data transfer with the RENB signal by low drawing high, so clock 8 is a fixed cycle (Dead Cycle) after clock 9 detects RVAL and is height.Respond high level PRPA signal in clock 3 channel B, represent that this passage can carry out transfer of data to main controller.At clock 10, channel B latch address, clock 11 detect the RENB signal for after low, and data are got.
Fig. 7 is that the present invention is as the 32nd PHY device sequential chart.Because the width of inquire address is 5 in POS level 2 interface protocols, and address bus 1F is an empty reason layer address, and all controlled devices should not respond.Therefore 1 link layer device in theory can external 31 physical layer devices.And in the present invention, use for reference SCI-PHY interface protocol thinking, whether be empty reason layer address owing to introduced the RVALID signal if being used to distinguish the 1F signal, therefore the query context of physical layer device can be increased to 32.If main controller is supported external 32 PHY devices, can couple together by corresponding RVALID signal with controlled device.CPU configuration module 13 can be set, and whether configuration the present invention can make the 32nd PHY device.Among Fig. 7, clock 5 RVALID are high, and the 1F passage is selected during as the 32nd PHY, and it can be done data and transmits therefore to respond high level PRPA signal indication.At clock 11, multiplexing controlled device pins the address.Clock 12 detects RENB for after low, and data are delivered on the data/address bus.
Claims (13)
1. a packet multiplexing receiving slave device is characterized in that, comprises the PHY processor module, receives control module, address decoding and latch module, PRPA respond module, CPU configuration module and up buffer module;
Described PHY processor module, identification packet packet header, whether packet bag tail and data packet byte number surpass control informations such as predetermined threshold value, then with packet and relevant information, deposit in the up buffer module corresponding address;
Described reception control module, the channel selecting signal that receiver address decoding and latch module are sent here, the control signal of detection main controller is put into packet and the relevant information that is stored in related channel program in the up buffer module on the POS-PHY bus;
Described address decoding and latch module with the signal interpretation on the address bus, as the foundation of selecting up buffer memory cell, are lived the transmission channel address latch before the transmission data;
Described PRPA respond module, channel selecting signal and each memory cell data bag store status signal of up buffer module that receiver address decoding and latch module are sent here produce the PRPA signal and return to main controller, the effective address inquiry of response main controller;
Described CPU configuration module, this module can be visited and prepare to cpu i/f, and the long word joint number and the shortest word joint number of packet can be set, and the corresponding relation of passage and external address can be set;
Described up buffer module, by channel address relevant informations such as packet and packet packet header, packet bag tail are deposited in the memory cell, the channel selecting signal that receiver address decoding and latch module are sent here reads data in the respective memory unit address by receiving control module.
2. packet multiplexing receiving slave device according to claim 1 is characterized in that described up buffer module is further divided into passage write control logic submodule, the memory cell submodule, and synchronous logic submodule and passage are read the control logic submodule;
Described passage write control logic submodule is pressed memory unit address with packet and relevant information write storage unit submodule;
Described memory cell submodule comprises and the identical buffer of physical layer device passage number, the packet and the relevant information that are used to store the corresponding physical layer device;
Described synchronous logic submodule will be write logical pointer and read logical pointer and do synchronous conversion in cross clock domain, to produce the store status signal;
Described passage is read the control logic submodule, by memory unit address packet and relevant information read from the memory cell submodule, and will be through the output of the store status signal synchronously.
3. packet multiplexing receiving slave device according to claim 1 is characterized in that, described buffer can adopt RAM to constitute.
4. a packet demultiplexing receiving slave device carries out the method for Data Receiving, it is characterized in that, may further comprise the steps at least:
(1) the data length register is designed in the PHY processor module, PHY processor module identification packet packet header, packet bag tail, and debate knowledge at packet bag tail whether Abort Sequence coding is arranged, whether will abandon information with decision and deposit in the up buffer module appropriate address;
(2) each channel data bag data and corresponding information deposit up buffer module in;
(3) up buffer module is given PRPA respond module with the state information of storage, through threshold process, perhaps directly indicates or the process address lookup, reports state to main controller.
5. packet demultiplexing method of reseptance as claimed in claim 4 is characterized in that step (3) also comprises the steps:
(a) the PRPA respond module judges that whether the byte number of the packet that storage one complete data packet or memory space can store that whether has living space memory cell has surpassed CPU configuration module predetermined threshold value, produces PRPA and DRPA[x then] signal;
(b) address decoding and latch module become corresponding channel address to the address decoding on the address wire TADR, give the criterion of PRPA respond module as output PRPA signal multiselect one; A timeticks before data packet transmission pins the address on the address wire TADR simultaneously, gives the reception control module after passage decoding, as the foundation that writes channel data;
(c) when main controller and controlled device reach receive agreement after, the reception control module of controlled device detects the TENB signal that main controller sends, and reads packet data and relevant information in the up buffer module by corresponding channel address then.
6. packet demultiplexing method of reseptance as claimed in claim 5 is characterized in that, the described predetermined threshold value of step (a) comprises the shortest threshold value of setting data bag and the longest threshold value.
7. data receive method as claimed in claim 6 is characterized in that, when the PHY processor module detects current data packet less than the shortest threshold value, the information that just will abandon deposits up buffer module in; When the PHY processor module detects current data packet greater than threshold value, the information that also will abandon deposits up buffer module 10 in, will abandon greater than the data packet byte of threshold value afterwards.
8. data receive method as claimed in claim 4 is characterized in that, comprises also in the step (2) that up buffer module will carry out the adjustment of asynchronous read and write pointer.
9. data receive method as claimed in claim 4, it is characterized in that, step (3) back is further comprising the steps of: read to enable and channel address, each timeticks by receiving the control module input, up buffer module is given the reception control module from memory cell read data packet data and relevant information.
10. as claim 5 or 9 described data receive methods, it is characterized in that transmission means is divided into two kinds: byte level load mode and packet level load mode.
11. data receive method as claimed in claim 10 is characterized in that, in the byte level load mode, by DRPA[x] signal is directly to the state of each channel data storage of main controller indication controlled device; In packet level load mode, by address decoding and latch module input channel address decoding, the PRPA respond module is responded the state of each channel data storage of controlled device through multiselect one to main controller by the PRPA signal.
12. data receive method as claimed in claim 5, it is characterized in that, do parity check to packet data when step (c) is carried out,, just produce warning information and report configuration module to CPU if the result on gained parity check result and the TPRTY holding wire is inconsistent.
13. data receive method as claimed in claim 5 is characterized in that, main controller and controlled device increase an interface signal, make external physical layer device be increased to 32.
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| CNB031318088A CN100486240C (en) | 2003-06-02 | 2003-06-02 | Data packet multiplexing receiving controller and data receiving method |
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| CNB031318088A CN100486240C (en) | 2003-06-02 | 2003-06-02 | Data packet multiplexing receiving controller and data receiving method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106911715A (en) * | 2017-04-05 | 2017-06-30 | 数据通信科学技术研究所 | A kind of communication control unit and communication control method that Read-write Catrol is separate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106911715A (en) * | 2017-04-05 | 2017-06-30 | 数据通信科学技术研究所 | A kind of communication control unit and communication control method that Read-write Catrol is separate |
| CN106911715B (en) * | 2017-04-05 | 2019-07-19 | 数据通信科学技术研究所 | A kind of communication control unit and communication control method separating Read-write Catrol |
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| CN100486240C (en) | 2009-05-06 |
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