CN100336340C - Multi-channel network management apparatus and method for transmission equipment - Google Patents
Multi-channel network management apparatus and method for transmission equipment Download PDFInfo
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- CN100336340C CN100336340C CNB031321089A CN03132108A CN100336340C CN 100336340 C CN100336340 C CN 100336340C CN B031321089 A CNB031321089 A CN B031321089A CN 03132108 A CN03132108 A CN 03132108A CN 100336340 C CN100336340 C CN 100336340C
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Abstract
The present invention discloses a multi-channel network management apparatus which belongs to the field of data communication. The present invention comprises a central processing unit control part, an SDH spending processing part and a multiplex-demultiplex FPGA processing part, wherein the central processing unit control part comprises an embedded type processor, a program memory and an external memory. The embedded type processor finishes the collection and the sending of serial data to control other parts, the multiplex-demultiplex FPGA processing part comprises a data frame head receiving processing detection and clock detection module, a multiplex processing module, a demultiplex processing module, an asynchronous FIFO receiving module and an asynchronous FIFO sending module; the SDH spending processing part comprises a plurality of spending processors. The aim of the present invention is to overcome the defects of the prior art of low management efficiency, insufficient data reliability and high system cost to realize the management of a plurality of network elements in an SDH device. The data reliability is improved, the manageability of the device is improved, and the integral cost of the system is reduced.
Description
Technical field
The present invention relates to the data communication field, relate in particular to synchronous digital transmission equipment (SDH:SynchronousDigital Hierarchy) multichannel network management device and method.
Background technology
Along with developing rapidly of data communication, people are also more and more higher to the requirement of transfer of data, and the SDH system also constantly is being widely used.In the SDH system, be a crucial technology contents for the management of synchronous digital transmission equipment.In the synchronous digital transmission equipment management, the management of single network element (can realize the equipment of basic service function) self mainly realizes by the intrasystem interface of SDH, as intrasystem Ethernet interface, based on HDLC (high level data LCP: the modes such as serial port of agreement High-Level Data Link Control).But, just need transmit management information by means of the expense in the data link (content of non-net load is mainly used in network operation in the data flow) for the management of a plurality of network elements.This mode usually with optical channel (passage that is used for optical signal transmission) as the hardware transmission medium, use expense in the optical channel to carry out information transmission between a plurality of network elements.In fact, utilizing expense to carry out the information transmission is mature technique comparatively at present.More for the method that the processing of expense is adopted, method commonly used is by overhead processor (this processor is positioned at the optical interface position) expense to be taken out, by the serial link bus information is sent to flush bonding processor then and handle, the The data HDLC agreement in the serial link guarantees the reliability that data content transmits.But this method requires the processor interface of the integrated support HDLC of flush bonding processor agreement, for the equipment that comprises a plurality of light directions (light direction: an optical channel is just represented a light direction), if each direction all needs to handle, will adopt the flush bonding processor of supporting a plurality of HDLC protocol interfaces.If the HDLC protocol interface of flush bonding processor can't satisfy the demands, can also on the flush bonding processor external bus, increase the hdlc controller of a multichannel.Hdlc controller is notified the inside FIFO of flush bonding processor to hdlc controller in the mode of interrupting, and (push-up storage: First In First Out) carry out read-write operation, (direct memory access (DMA): mode Direct Memory Access) is carried out the processing of the transmitting-receiving of data perhaps to use DMA.But, no matter adopt which kind of mode, all can't avoid the problem of serious packet loss, this problem causes very big influence for the transmission of long data bag.For example, when hdlc controller adopts the interrupt mode deal with data, the data that common hdlc controller receives at first are stored in the memory of chip internal, after data volume reaches certain byte, will produce an interrupt signal notice flush bonding processor and carry out data sampling.After flush bonding processor receives interrupt signal, can interrupt current operation, enter interrupt handling routine, interrupt handling routine control flush bonding processor reads the data in the hdlc controller internal storage, if data packets for transmission is longer, then can frequently produce interrupt request singal, flush bonding processor is easy to produce misoperation like this, cause data to make mistakes, the immediate problem that brings is exactly the manageability that has reduced whole network.
Summary of the invention
The objective of the invention is to overcome the easy lost data packets of prior art existence, the shortcoming that the transmission network manageability is poor, hardware cost is higher, to propose a kind of enhancing data transmission security and transmission network manageability, can effectively reduce the apparatus and method of hardware cost simultaneously.
For achieving the above object, the present invention has constructed a kind of transmission equipment multichannel network management device, it is characterized in that, comprise CPU control part, SDH overhead processing part, it is characterized in that, also comprise multiplexing and demultiplexing FPGA (field programmable gate array: processing section Field Programmable Gate Array);
Described CPU control part comprises flush bonding processor, program storage, external memory storage; Described flush bonding processor is finished serial data collection and transmission, and the debit of its interface comprises serial data signal, reference clock signal, start mark signal to signal, and above-mentioned signal all derives from described multiplexing and demultiplexing FPGA processing section; Originating party comprises serial data signal and the reference clock signal that derives from described multiplexing and demultiplexing FPGA processing section, start mark signal etc. to signal; Described flush bonding processor is also handled the data of being gathered simultaneously, and described multiplexing and demultiplexing FPGA processing section and described SDH overhead processing part are controlled, and comprises basic function configuration, state information searching etc.;
Described program storage is stored all programs of whole device, described external memory stores working procedure and ephemeral data.
Described multiplexing and demultiplexing FPGA processing section comprises receiving data frames head processing detection and clock detection module, multiplexing process module, demultiplexing processing module, receives the asynchronous FIFO module, sends the asynchronous FIFO module; The data that described receiving data frames head processing detects and the clock detection module sends described SDH overhead processing part carry out the detection of serial data frame head and passage detects, data are after testing undertaken being transferred to described multiplexing process module after the clock synchronization by described reception asynchronous FIFO module, described multiplexing process module is carried out multiplexing and the also conversion of string, sends to the flush bonding processor of described CPU control part then; At other direction, flush bonding processor carries out demultiplexing with transfer of data to described demultiplexing processing module to be handled and goes here and there and conversion, data after the processing are sent to described transmission data processing module after described transmission asynchronous FIFO module is carried out clock synchronization, by described transmission data processing module with data passes to described SDH overhead processing part;
Described SDH overhead processing part comprises several overhead processors, carry out the parsing of Overhead and the Overhead multiplex process again in the optical channel, described overhead processor takes out expense from the SDH data format, send to described receiving data frames head with serial mode and handle detection and clock detection module, receive the serial data of described transmission data processing module simultaneously, this serial data is multiplexed in the corresponding expense again.
Described flush bonding processor uses inner multichannel communication controller to finish serial data collection and transmission.
The invention allows for a kind of transmission equipment multichannel network management method, it is characterized in that, comprise the step that receives and send both direction:
Receive direction:
The optical interface of step 1:SDH overhead processing part changes the light signal that receives into the signal of telecommunication, send to overhead processor, described overhead processor solves corresponding data path overhead byte from the SDH frame, and then by every road serial-port overhead byte is transmitted to multiplexing and demultiplexing FPGA processing section;
Step 2: described multiplexing and demultiplexing FPGA at first detects valid data in every road serial-port and the serial-port processing section, after detecting valid data, carry out simultaneous operation, make the serial data on every road synchronous with flush bonding processor sampling reference clock with multichannel communication controller, deposit data in internal register simultaneously, finish string and conversion; Carry out multiplexing operation then,, and this high-speed serial signals sent to described flush bonding processor the low-speed serial signal multiplexing of the multichannel high-speed serial signals to a tunnel;
Step 3: described flush bonding processor is gathered the high-speed serial data that send described multiplexing and demultiplexing FPGA processing section, and the data that sample are deposited in the memory of flush bonding processor outside, finish the reception of whole frame data when flush bonding processor after, the resolution data header content, whether the header judgment data according to data is the information of this network element, if the information of this network element, will do a nearly step according to the information of datagram header back and handle, as operations such as net element business configuration, information inquiries; If the information of non-network element then transmit again;
Sending direction:
Step 1: described flush bonding processor is determined the purpose network element, and non-the network element data that need are transmitted is medium to be sent at the transmission buffer memory with the storage that this network element need report; Described multiplexing and demultiplexing FPGA processing section produces and sends the marking signal that the notice flush bonding processor sends data according to the operating position that the low-speed serial path sends spatial cache, receive the flush bonding processor certification mark signal of described multiplexing and demultiplexing FPGA processing section transmission when flush bonding processor after, with sending in the serial-port of one one of the data in the transmission buffer memory;
Step 2: in the effective while of marking signal, described multiplexing and demultiplexing FPGA processing section begins to sample and is derived from the serial data signal of described flush bonding processor, and with the conversion of signals that samples for parallel, wait for synchronous again process;
Step 3: described overhead processor receives the serial data that sends over from described multiplexing and demultiplexing FPGA processing section, serial data is multiplexed into the position of agreement regulation in the SDH frame, light path in correspondence is forwarded to miscellaneous equipment, or is forwarded to access network element; Described overhead processor uses and the clock of line side synchronised receives and send overhead byte.
Apparatus and method of the present invention mainly realize the multichannel network management function of SDH (Synchronous Digital Hierarchy) by the multichannel communication controller that utilizes flush bonding processor, and can effectively improve the efficiency of management to multiterminal equipment, particularly effective especially to big data packet transmission.Can effectively realize in the SDH equipment management by apparatus and method of the present invention, and can improve the reliability of data, improve the manageability of equipment, save unnecessary chip, reduce the whole cost of system a plurality of network elements.
Description of drawings
Fig. 1 is a transmission equipment multichannel network management device structure chart of the present invention.
Fig. 2 is a transmission equipment multichannel network management method flow chart of the present invention.
Fig. 3 is a multiplexing and demultiplexing FPGA processing section workflow diagram in the device of the present invention.
Fig. 4 is a flush bonding processor part workflow diagram schematic diagram in the device of the present invention.
Embodiment
Below in conjunction with accompanying drawing technical solutions according to the invention are further described.
Transmission equipment multichannel network management device of the present invention has mainly used the flush bonding processor MPC860 of motorola inc, utilizes its multichannel communication controller (QMC:QUICC Multichannel Controlle) to realize network management path.
The concrete structure of transmission equipment multichannel network management device of the present invention mainly comprises three parts as shown in Figure 1: CPU control part, multiplexing and demultiplexing FPGA processing section, SDH overhead processing part.Elaborate the function of each several part below according to diagram.
1, SDH overhead processing part.This part is mainly finished the parsing of Overhead and the Overhead multiplex process again in the optical channel, and the expense here is meant in the SDH frame data path byte as Data transmission.The work of this part uses special-purpose overhead processor to finish, overhead processor takes out specific expense from the SDH frame, the reference clock (being provided by overhead processor) of use and system synchronization sends data with serial mode, usually the transfer sequence of serial data is consistent with the transmission sequence of SDH frame in channel, is sorted to high byte by low byte.Is example with the D1 that defines in the SDH frame to the D3 overhead byte, at first transmits the D1 byte, transmits the D2 byte then, transmits the D3 byte at last, goes round and begins again; On the another one light direction, overhead processor receives serial data, and the reference clock of reception data need use the clock with system synchronization equally, and each byte is multiplexed into respectively in the corresponding expense of SDH frame.For guaranteeing reliability of data transmission, the data of transmitting in the expense are used the HDLC agreement usually.Because the multichannel communication controller in the flush bonding processor of the present invention can be supported a plurality of logical channels, therefore in Fig. 1, use 1 ~ n overhead processor to carry out the overhead processing of 1 ~ n light direction.Though the maximum n=64 of Zhi Chiing in theory, but because the system resource of flush bonding processor not only is used for this function operations, also have other action needs to take resource, therefore in actual applications, generally can't realize 64 whole channel application, during actual the use, general no more than 32 of logical channel number.
2, multiplexing and demultiplexing FPGA processing section.This part is core of the present invention, mainly uses fpga logic to realize that logic realizes every function in the mode of module.The receiving data frames head handles detection and the clock detection module is finished detection of serial data frame head and passage measuring ability; The multiplexing process module finish multiplexing and string and and and go here and there translation function; The demultiplexing processing module is finished the demultiplexing function; Receive the asynchronous FIFO module and send the asynchronous FIFO module and solve the nonsynchronous problem of clock.From the method that realizes, the FPGA function treatment is divided into reception and sends two chief components.Relative SDH overhead processing part, at receive direction, multiplexing and demultiplexing FPGA processing section receives the data that a plurality of overhead processors send, two holding wires are arranged between the interface of each overhead processor and multiplexing and demultiplexing FPGA processing section, one is the serial data signal line, other one is clock signal, provides by overhead processor.Receive the data of overhead processor transmission when multiplexing and demultiplexing FPGA processing section after, at first can detect the serial data frame head in multiplexing and demultiplexing FPGA processing section receiving data frames head processing detection and clock detection module, after detecting effective header signal, can enter into next functional module handles, also want the clock signal of sense channel whether to exist in addition, if can't detect clock signal, just represent that this passage does not use.After finishing the operation of this module, valid data can enter into and receive the asynchronous FIFO module.In this functional module, data can realize that low-speed serial arrives the conversion of high-speed serial signals, and and then the signal that comes out from this module can enter the multiplexing process module.The multiplexing process module will be multiplexed into the order of multi-path serial signal according to predefined in one road serial signal, also will produce the start mark signal of flush bonding processor sampling usefulness in this module.Through behind the top all operations, start mark signal and serial data signal can send to flush bonding processor simultaneously.At sending direction, multiplexing and demultiplexing FPGA processing section produces start mark signalisation flush bonding processor and sends data, the demultiplexing processing module that the data of sending from flush bonding processor at first enter multiplexing and demultiplexing FPGA processing section, the demultiplexing processing module is with take out the asynchronous FIFO that each signal be sent to each passage correspondence of the signal in the different time-gap in the serial data according to prior agreement, the function of described asynchronous FIFO and receive direction is in full accord, and the data of coming out from asynchronous FIFO are finished forwarding to each channel data by sending data processing module.Described multiplexing and demultiplexing FPGA also will finish the processing section the automatic measuring ability of each passage, when the channel serial data circuit occurs unusual, or when being in unused state, then can notify flush bonding processor to stop processing to this channel information, close this passage, can reduce like this taking of flush bonding processor resource, improve the operating efficiency of flush bonding processor.
Particularly, each module is mainly finished following operation:
Serial data frame head detecting operation: this operation is actual to be exactly the frame head that detects the HDLC data in the link, the reference clock signal that the signal that this operation is brought mainly due to the reference clock signal and the overhead processor of the use of multichannel communication controller uses is asynchronous, if not carrying out frame head detects, empty problem might appear overflowing or reading in the data cached memory space in multiplexing and demultiplexing FPGA processing section, will cause data transmission fault, thereby reduce the reliability of passage, therefore need the frame head that receive data-signal be detected.
Multiplexing and de-multiplex operation: because the multichannel communication controller of flush bonding processor adopts with the byte is the time slot operations pattern of unit, the bit wide of eight of each Time Slot Occupancies just, the multi-path serial circuit need be multiplexed into respectively in each time slot, also will finish an inverse process simultaneously, the serial signal demultiplexing that will send from flush bonding processor is the multi-path serial data.
String and and and go here and there conversion operations: this operation mainly is to operate the operation of carrying out for finishing multiplexing and demultiplexing, because the synchronised clock of multi-path serial circuit is asynchronous with the synchronised clock of flush bonding processor side, need twice simultaneous operation, use the parallel work-flow ratio to be easier to realize function in synchronizing process, therefore will go here and there and change and and string conversion.
Frame start mark signal: the multichannel communication controller of flush bonding processor needs a frame start mark signal when receiving and send serial data, this frame start mark signal is used to refer to the beginning of valid data in the serial-port.Receive and send serial data start mark signal and conciliate the generation of multiplexing process module in the multiplexing process module of multiplexing and demultiplexing FPGA processing section respectively.
Passage detecting operation: owing to might occur in the system the not situation on same veneer of overhead processor and multichannel communication controller in actual applications, therefore when the veneer that has an overhead processor when certain piece is pulled down from system, the physical channel time slot corresponding will be in idle condition, but this moment, flush bonding processor still continued to handle this part time slot, can take the resource of flush bonding processor.In order to economize on resources, set up a passage measuring ability in the present invention.This function needs hardware to cooperate software to detect the situation on the throne of veneer in real time, if veneer is not on the throne, need software to reset the register relevant of flush bonding processor, reduce the width of flush bonding processor time slot, thereby save the resource of flush bonding processor with this function.
3, CPU control part.This part is finished the multichannel processing capacity, and the data message of a plurality of time slots in the serial transmission line is taken out, and at first deposits in the memory of flush bonding processor inside, and then analyzes after delivering in the external memory storage.If belong to the data of current network, flush bonding processor will be operated accordingly according to the content of data, as to other veneer configuration in the current network system, obtains the operating state of other veneer in the system etc.If the data of receiving not are the data of this network element, flush bonding processor need forward data again.CPU control part is except comprising flush bonding processor, also should comprise the more requisite peripheral components of flush bonding processor normal running, as store the program storage of whole device program, the external memory storage of working procedure and storage ephemeral data (comprising received serial data of multichannel communication controller and data to be sent).Flush bonding processor uses inner multichannel communication controller to finish serial data collection and transmission.Special-purpose interface is arranged between multiplexing and demultiplexing FPGA processing section and the flush bonding processor, and this interface is divided into receives and sends out two groups of signals.The debit to signal serial data signal line (signal derives from multiplexing and demultiplexing FPGA processing section), reference clock signal line (signal derives from multiplexing and demultiplexing FPGA processing section), start mark holding wire (signal derives from multiplexing and demultiplexing FPGA processing section) are arranged; Originating party has serial data signal line (signal derives from flush bonding processor), reference clock signal line (signal derives from multiplexing and demultiplexing FPGA processing section), start mark holding wire (signal derives from multiplexing and demultiplexing FPGA processing section) to signal.Flush bonding processor also will be handled the data that sample, simultaneously described multiplexing and demultiplexing FPGA processing section and described overhead processing part are controlled, comprised operations such as inquiry multiplexing and demultiplexing FPGA processing section and the configuration of overhead processor basic function, multiplexing and demultiplexing FPGA processing section and overhead processor state information.
Transmission equipment multichannel network management method of the present invention mainly comprises following step as shown in Figure 2.
Step 1: at receive direction, the light signal that optical interface receives changes the signal of telecommunication into, send to overhead processor, overhead processor solves corresponding data path overhead byte from the SDH frame, here the maximum directions of expense that allow to receive can be the individual directions of n (n≤32 that suggestion is used), and then by serial-port overhead byte are transmitted to multiplexing and demultiplexing FPGA processing section and handle; At sending direction, overhead processor receives the serial data that sends over from multiplexing and demultiplexing FPGA processing section, serial data is multiplexed into the position of the agreement regulation in the SDH frame, light path in correspondence is transmitted, or to miscellaneous equipment, or to access network element (access network element: the node that is used to connect network management terminal).Overhead processor uses and the clock of line side synchronised receives and send overhead byte, system for a plurality of light directions, each direction all can have reference clock separately, and these reference clocks can be asynchronous, provides a solution at the problem that may occur among the present invention.
Step 2: the processing of multiplexing and demultiplexing FPGA processing section comprises reception in fact and sends both direction.At receive direction, the function that multiplexing and demultiplexing FPGA at first realizes the processing section is the detection to valid data in the detection of every road serial-port and the serial-port, after detecting valid data, through a simultaneous operation process, make the serial data and the flush bonding processor sampling reference clock on every road synchronous, deposit data in internal register simultaneously, finish string and conversion, next be exactly multiplexing operation, be a process with the low-speed serial signal multiplexing of the multichannel high-speed serial signals to a tunnel, high-speed serial signals can send to flush bonding processor.Sending direction is the process of a demultiplexing, at first multiplexing and demultiplexing FPGA processing section produces the marking signal that the notice embedded processing sends data according to the operating position that the low-speed serial path sends spatial cache, in the effective while of marking signal, multiplexing and demultiplexing FPGA processing section begins to sample and is derived from the serial data signal of flush bonding processor, and with the conversion of signals that samples for parallel, wait for synchronous again process, the simultaneous operation process can send to overhead processor according to the reference clock of low-speed serial path with data.
Step 3: flush bonding processor plays crucial effects in whole device, and it will finish operations such as serial data collection, transmission and processing, finishes these action needs and realizes by the software control flush bonding processor.
The workflow of multiplexing and demultiplexing FPGA processing section describes in detail as shown in Figure 3, below will be from receiving and send the implementation procedure that two aspects are set forth this part respectively.
Receive direction:
Step 1: multiplexing and demultiplexing FPGA processing section receives the HDLC data of multichannel, with four the tunnel is example, the frame head that data-signal is carried out on every road respectively detects, and the channel reference clock signal detects, the channel reference clock detection is exactly that whether existence to passage detects, after finishing, detection will in the register of passage correspondence, write content corresponding, it is on the throne to write " 0 " expression passage, writing " 1 " expression passage does not exist, just can this passage not handled when the content of reading when processor is " 1 ", the main purpose of doing like this is in order to save the resource of processor.
Step 2: if the data that detect in the low-speed serial passage have header signal (header signal is 0x7E), data can send among separately the asynchronous serial FIFO, after the data in the asynchronous FIFO reach a location number, can produce the operation that asynchronous FIFO is read, in the storage to of the reading shift register, this operation is actual to be a string and transfer process.
Step 3: after the operation above finishing, multiplexing and demultiplexing FPGA processing section need produce reception marking signal notice flush bonding processor and carry out data sampling, four circuit-switched data signals are multiplexed in the flush bonding processor reception serial link time slot corresponding according to the mode of byte (is that just each byte takies a time slot because the multichannel communication controller is according to byte mode time slot to be distributed according to byte mode) simultaneously.Flush bonding processor can detect the serial data that multiplexing and demultiplexing FPGA processing section sends according to receiving marking signal.
Sending direction:
Step 1: (marking signal is an example with above-mentioned four-way at first to need multiplexing and demultiplexing FPGA processing section to produce a transmission marking signal at sending direction, each passage takies the time slot of a byte, and will to have four bytes be valid data in this mark back like this.After finishing four bytes transmission, if also will transmit data, just need produce marking signal once more) notice flush bonding processor transmission serial data stream, simultaneously multiplexing and demultiplexing FPGA processing section also can send the marking signal data flow that flush bonding processor sends out of sampling according to this, and the data that multiplexing and demultiplexing FPGA processing section samples at first leave in the inner shift register.
Step 2: then multiplexing and demultiplexing FPGA processing section splits in some registers (passage should corresponding register) with the content of top shift register according to different passages, and each register all is 24.
Step 3: multiplexing and demultiplexing FPGA judges the processing section state of each independent asynchronous FIFO, after soon empty state occurring, data in the corresponding 24 bit length registers of top each passage can be sent on the data link, just write data among the asynchronous serial FIFO, multiplexing and demultiplexing FPGA processing section sends to the data in the asynchronous FIFO of correspondence in the corresponding low-speed serial passage more simultaneously, after all data move into asynchronous FIFO in the register in addition, if flush bonding processor also has data to need to send, multiplexing and demultiplexing FPGA processing section will produce a marking signal again and notify flush bonding processor to continue to send data.
Flush bonding processor part workflow schematic diagram describes in detail as shown in Figure 4:
Step 1: flush bonding processor at first needs the initialization operation through software, and the initialization of the inner main register of embedded processing and the initialization of relevant interface are finished in this step operation.Next be the initialization to multichannel communication controller function register, related register has detailed description in the user's manual of flush bonding processor.There is any to particularly point out, in the initialization of multichannel communication controller function register, need to define the width of sampled data, with four time slots, 8 positions of each time slot are long to be example, it is long to need width with sampled data to be defined as 32 positions so, and effectively which cycle of back begins the valid data signal of sampling but also will be defined in the start mark signal.
Step 2: at the receive direction of flush bonding processor, it can constantly detect the start mark signal, after sampling the start mark signal, can carry out the sampling of data according to previously defined valid data original position, and the data that sample are deposited in the memory of flush bonding processor outside, (HDLC frame format data are to be start mark with 0x7E when flush bonding processor is finished a whole frame, be the frame end mark equally with 0x7E, it is by using the physical channel of SDH that the mode that realizes management was mentioned in the front, adopt the HDLC agreement to finish the transmission of respectively holding the equipment room control information) after the reception of data, just can begin the processing of data.The first step of data processing is the resolution data header content, whether the header judgment data according to data is the information of this network element, if the information of this network element will be done a nearly step according to the information of datagram header back and handle, as operations such as net element business configuration, information inquiries; If the information of non-network element just needs to transmit again.
Step 3: at the sending direction of flush bonding processor, data have two sources, and the content that this network element data of right and wrong need be transmitted is the data that this network element need report in addition.These two classes data needed through a routing algorithm before sending, and determined the purpose network element that sends, finish this operation after, data will be stored in that to send buffer memory medium to be sent.After sending embedded processing certification mark signal, can be with one sends in the serial-port of data that sends in the buffer memory.
Claims (8)
1, a kind of transmission equipment multichannel network management device comprises CPU control part, SDH overhead processing part, it is characterized in that, also comprises multiplexing and demultiplexing FPGA processing section;
Described CPU control part comprises flush bonding processor, program storage, external memory storage; Described flush bonding processor has the multichannel communication controller, finishes serial data collection and transmission, and described multiplexing and demultiplexing FPGA processing section and described SDH overhead processing part are controlled, and comprises basic function configuration, state information searching etc.; Described program storage is stored all programs of whole device, described external memory stores working procedure and ephemeral data;
Described multiplexing and demultiplexing FPGA processing section comprises receiving data frames head processing detection and clock detection module, multiplexing process module, demultiplexing processing module, receives the asynchronous FIFO module, sends the asynchronous FIFO module; The data that described receiving data frames head processing detects and the clock detection module sends described SDH overhead processing part carry out the detection of serial data frame head and passage detects, data are after testing undertaken being transferred to described multiplexing process module after the clock synchronization by described reception asynchronous FIFO module, described multiplexing process module is carried out multiplexing and the also conversion of string, sends to the flush bonding processor of described CPU control part then; At other direction, described flush bonding processor carries out demultiplexing with transfer of data to described demultiplexing processing module to be handled and goes here and there and conversion, data after the processing are sent to described transmission data processing module after described transmission asynchronous FIFO module is carried out clock synchronization, by described transmission data processing module with data passes to described SDH overhead processing part;
Described SDH overhead processing part comprises several overhead processors, carries out the parsing of Overhead and the Overhead multiplex process again in the optical channel.
2, transmission equipment multichannel network management device according to claim 1, it is characterized in that, the debit of described flush bonding processor interface comprises serial data signal, reference clock signal, start mark signal to signal, and above-mentioned signal all derives from described multiplexing and demultiplexing FPGA processing section.
3, transmission equipment multichannel network management device according to claim 1, it is characterized in that the originating party of described flush bonding processor interface comprises serial data signal and the reference clock signal, the start mark signal that derive from described multiplexing and demultiplexing FPGA processing section to signal.
4, transmission equipment multichannel network management device according to claim 1, it is characterized in that, parsing and Overhead that described SDH overhead processing part is carried out Overhead specifically comprise to the multiplex process again in the optical channel, described overhead processor takes out expense from the SDH data format, send to described receiving data frames head with serial mode and handle detection and clock detection module, receive the serial data of described transmission data processing module simultaneously, this serial data is multiplexed in the corresponding expense again.
5, a kind of transmission equipment multichannel network management method is characterized in that, comprises the step that receives and send both direction:
Receive direction:
The optical interface of step 1:SDH overhead processing part changes the light signal that receives into the signal of telecommunication, send to overhead processor, described overhead processor solves corresponding data path overhead byte from the SDH frame, and then by every road serial-port overhead byte is transmitted to multiplexing and demultiplexing FPGA processing section;
Step 2: described multiplexing and demultiplexing FPGA processing section is at first detected valid data in described every road serial-port and the serial-port, after detecting valid data, carry out simultaneous operation, make the serial data on every road synchronous with flush bonding processor sampling reference clock with multichannel communication controller, deposit data in internal register simultaneously, finish string and conversion; Carry out multiplexing operation then,, and this high-speed serial signals sent to described flush bonding processor the low-speed serial signal multiplexing of the multichannel high-speed serial signals to a tunnel;
Step 3: described flush bonding processor is gathered the high-speed serial data that send described multiplexing and demultiplexing FPGA processing section, and the data that sample are deposited in the memory of flush bonding processor outside, finish the reception of whole frame data when flush bonding processor after, the resolution data header content, whether the header judgment data according to data is the information of this network element, if the information of this network element, will do a nearly step according to the information of datagram header back and handle, as operations such as net element business configuration, information inquiries; If the information of non-network element then transmit again;
Sending direction:
Step 1: described flush bonding processor is determined the purpose network element, and non-the network element data that need are transmitted is medium to be sent at the transmission buffer memory with the storage that this network element need report; Described multiplexing and demultiplexing FPGA processing section produces and sends the marking signal that the notice flush bonding processor sends data according to the operating position that the low-speed serial path sends spatial cache, receive the flush bonding processor certification mark signal of described multiplexing and demultiplexing FPGA processing section transmission when described flush bonding processor after, with sending in the serial-port of one one of the data in the transmission buffer memory;
Step 2: in the effective while of marking signal, described multiplexing and demultiplexing FPGA processing section begins to sample and is derived from the serial data signal of described flush bonding processor, and with the conversion of signals that samples for parallel, wait for synchronous again process;
Step 3: described overhead processor receives the serial data that sends over from described multiplexing and demultiplexing FPGA processing section, serial data is multiplexed into the position of agreement regulation in the SDH frame, light path in correspondence is forwarded to miscellaneous equipment, or is forwarded to access network element; Described overhead processor uses and the clock of line side synchronised receives and send overhead byte.
6, transmission equipment multichannel network management method according to claim 5 is characterized in that, described receive direction step 2 further may further comprise the steps:
(1) described multiplexing and demultiplexing FPGA processing section receives the HDLC data of multichannel, and the frame head that data-signal is carried out on every road respectively detects, and the channel reference clock signal detects, and detects will write content corresponding in the register of passage correspondence after finishing;
(2) if the data that detect in the low-speed serial passage have header signal, step (1) is stored in data in the register and can sends in separately the reception asynchronous FIFO module, after the data in the described reception asynchronous FIFO module reach a location number, can produce the operation that described reception asynchronous FIFO module is read, in the storage to of the reading shift register;
(3) described multiplexing and demultiplexing FPGA processing section generation reception marking signal notifies described flush bonding processor to carry out data sampling, simultaneously step (2) stores a multichannel data signal in the shift register into and is multiplexed into described flush bonding processor according to the mode of byte and receives in the serial link time slot corresponding, and described flush bonding processor detects the serial data that described multiplexing and demultiplexing FPGA processing section sends according to receiving marking signal.
7, transmission equipment multichannel network management method according to claim 6 is characterized in that, the header signal in the described step (2) is 0x7E.
8, transmission equipment multichannel network management method according to claim 5 is characterized in that, described sending direction step 2 further may further comprise the steps:
(1) described multiplexing and demultiplexing FPGA processing section is according to this transmission marking signal data flow that described flush bonding processor sends out of sampling, and the data that sampled at first leave in the inner shift register;
(2) described multiplexing and demultiplexing FPGA processing section splits the content of above-mentioned shift register in some registers according to different passages;
(3) described multiplexing and demultiplexing FPGA processing section judges that each sends the state of asynchronous FIFO module, after soon empty state occurring, data in the corresponding 24 bit length registers of above-mentioned each passage are sent on the data link of asynchronous FIFO module, described multiplexing and demultiplexing FPGA processing section sends to data in the transmission asynchronous FIFO module of correspondence in the corresponding low-speed serial passage more simultaneously, after all data move into and send the asynchronous FIFO module in the register, if described flush bonding processor also has data to need to send, described multiplexing and demultiplexing FPGA processing section produces a marking signal again and notifies described flush bonding processor to continue to send data.
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| CN1314230C (en) * | 2005-05-18 | 2007-05-02 | 烽火通信科技股份有限公司 | Method for transferring alarm information of net element in use for optical transmission network |
| CN101237318B (en) * | 2007-01-29 | 2011-12-28 | 中兴通讯股份有限公司 | Multi-channel data transmission synchronization device |
| WO2010145076A1 (en) * | 2009-06-18 | 2010-12-23 | 深圳粤和通科技有限公司 | Sonet/sdh interface device |
| CN101631335B (en) * | 2009-08-19 | 2011-12-28 | 中兴通讯股份有限公司 | Method and device for inserting overhead into optical channel data unit frame (ODUk) |
| JP6120958B2 (en) * | 2012-07-05 | 2017-04-26 | ゼットティーイー コーポレーションＺｔｅ Ｃｏｒｐｏｒａｔｉｏｎ | Business overhead processing method, apparatus and system |
| CN103888293B (en) * | 2014-02-25 | 2017-01-18 | 电子科技大学 | Data channel scheduling method of multichannel FC network data simulation system |
| CN109488886B (en) * | 2017-09-11 | 2024-01-23 | 清华大学 | Data line concentration system of detector in oil and gas pipeline and time sequence control method |
| CN109274697B (en) * | 2018-11-22 | 2021-11-12 | 湖南有马信息技术有限公司 | Data frame escape method, system and related device |
| CN114089946B (en) * | 2022-01-20 | 2022-04-19 | 深圳云豹智能有限公司 | FIFO device and data processing system |
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