CN1542970A - Semiconductor structure reducing external diffusion of buried layer contact tape, method for making the same and forming method for semiconductor storage device - Google Patents
Semiconductor structure reducing external diffusion of buried layer contact tape, method for making the same and forming method for semiconductor storage device Download PDFInfo
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- CN1542970A CN1542970A CNA031224733A CN03122473A CN1542970A CN 1542970 A CN1542970 A CN 1542970A CN A031224733 A CNA031224733 A CN A031224733A CN 03122473 A CN03122473 A CN 03122473A CN 1542970 A CN1542970 A CN 1542970A
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Abstract
A semiconductor structure of reducing diffusion to a buried layer contact belt includes a transistor composed of a gate and doped zones at both sides of the gate, a buried layer contact belt connecting to one of the two doped zones, a trench adjacent to said belt, a trench capacitor formed on the bottom of said trench including a built-in electropad, a capacitor dielectric layer and an electropad, a wire on the trenched capacitor composed of a ring isolation layer and a first conduction layer surrounded by it, a conduction layer formed on the sidewall of the said trench, a second conduction layer surrounded by it and a shallow ridge isolation structure at the other side of the trench corresponding to the belt which is connected with the sidewall conduction layer in the trench, the doped concentration of it is lower than that of the second conduction layer.
Description
Technical field
The invention relates to that a kind of contact zones that form are to reach the electrical memory assembly improvement manufacture method that contacts, particularly relevant for a kind of method that prevents the buried regions contact zones to outdiffusion (Buried Strap outdiffusion) between slot type capacitor and transistor.
Background technology
At present the memory capacity of DRAM has reached 64 megabits even more than 256 megabits, require under the more and more higher situation in the assembly integration, memory cell and transistorized size are also constantly significantly dwindled, and higher to produce memory capacity, processing speed is DRAM faster.The process technique of the three-dimensional capacitor that uses just at present, the area that capacitor took on the semiconductor-based end can significantly reduce, so the three-dimensional capacitor to be used in memory capacity widely be the above DRAM of 64 megabits.
General groove type capacitance and transistorized structure, as shown in Figure 1, deep trench (DT; Deep Trench) capacitor C comprises embedded electrode plate 15, capacitance dielectric layer 16 and battery lead plate 17, is formed with conductor structure on it, comprises ring-type insulating barrier 18 and filling first conductive layer 19 wherein, then forms a conductive layer 13 again; And transistor 1 comprises gate 10 and be positioned at the N+ doped region that gate two is surveyed; Then form the shallow trench isolation structure 14 that is filled with dielectric layer at groove with respect to this transistorized opposite side.
Above-mentioned slot type capacitor contacts with the electrical of semiconductor transistor, is to form a buried regions contact zones (BS between the N+ of transistor 1 doped region and groove; Buried Strap) 12, as both electric connections.Because these contact zones are formed under the substrate base, therefore on substrate surface, has more space to make the higher memory cell of integration.Moreover, because making as yet at many surface components, these contact zones do not form the assembly in the time of can avoiding making on the deface.
Yet the structure of above-mentioned buried regions contact zones 12 is owing to directly contact with the conductive layer 13 of capacitor C, and above-mentioned conductive layer is generally the polysilicon of doping, and therefore the problem of outdiffusion (outdiffusion) is very easily arranged.
Summary of the invention
Purpose of the present invention promptly provides a kind of method that can overcome the minimizing buried regions contact zones outdiffusion of known shortcoming, to adapt to the needs on the present semiconductor industry.
The present invention mainly is by forming earlier a sidewall conductive layer on the first half sidewall of groove type capacitance, it is characterized by low concentration (being lower than second conductive layer that it surrounds) or even unadulterated conductive layer, effectively to prevent the problem of buried regions contact zones outdiffusion.
For reaching above-mentioned purpose, the invention provides a kind of semiconductor structure that reduces the outdiffusion of buried regions contact zones, it comprises: a transistor, the doped region that comprises gate and be positioned at above-mentioned gate both sides; One buried regions contact zones are connected to one of above-mentioned two doped regions mutually; One groove is adjacent with these buried regions contact zones; One groove type capacitance is formed at the bottom of this groove, comprises embedded electrode plate, capacitance dielectric layer and battery lead plate; One conductor structure is positioned on this groove type capacitance, and this conductor structure comprises ring-type insulating barrier and first conductive layer that is surrounded by the ring-type insulating barrier; One sidewall conductive layer is formed at the sidewall of this groove; One second conductive layer is surrounded by this sidewall conductive layer; And a shallow trench isolation structure, be positioned at the opposite side of this groove with respect to these buried regions contact zones; Wherein the sidewall conductive layer in these buried regions contact zones and the groove is joined, and the doping content of this sidewall conductive layer is lower than this second conductive layer.
The present invention also provides a kind of method that reduces the outdiffusion of buried regions contact zones, and its step comprises: provide a semiconductor-based end that is formed with a bed course structure and a groove, and this channel bottom is formed with a groove type capacitance; On the sidewall of this groove, form a ring-type insulating barrier; In this ring-type insulating barrier area surrounded, form one first conductive layer; Form a sidewall conductive layer on this trenched side-wall; And form one second conductive layer in this sidewall conductive layer area surrounded, wherein the doping content of this sidewall conductive layer is lower than this second conductive layer.
According to the method for minimizing buried regions contact zones of the present invention outdiffusion, when being used to form semiconductor memory system, its step comprises: provide a semiconductor-based end that is formed with a bed course structure and a groove, and this channel bottom is formed with a groove type capacitance; On the sidewall of this groove, form a ring-type insulating barrier; In this ring-type insulating barrier area surrounded, form one first conductive layer; Form a sidewall conductive layer on this trenched side-wall; Form one second conductive layer in this sidewall conductive layer area surrounded, wherein the doping content of this sidewall conductive layer is lower than this second conductive layer; With light shield develop and etching step in a side of this groove, after defining the zone of shallow trench isolation structure and removing, insert dielectric material and form shallow trench isolation structure; And forming by gate and be positioned at the transistor that the doped region of gate both sides is formed at this groove with respect to the opposite side of this shallow trench isolation structure.
Description of drawings
Fig. 1 is the profile of the buried regions contact zones of known techniques;
Fig. 2 A～2F is the processing procedure profile of embodiments of the invention;
Fig. 3 is the profile that reduces the semiconductor memory system of buried regions contact zones outdiffusion according to embodiments of the invention.
Symbol description:
1～transistor, 2～groove type capacitance
10～gate, 12～buried regions contact zones
13～conductive layer, 14～shallow isolating trough structure
100～semiconductor-based the end, 110～oxide layer
120～nitration case, 105～groove
115～embedded electrode plate, 116～capacitance dielectric layer
117～battery lead plate, 125～gate
135～buried regions contact zones, 155～shallow isolating trough structure
140～ring-type insulating barrier, 150～the first conductive layers
160 '～sidewall conductive layer, 170～the second conductive layers
Embodiment
Shown in Fig. 2 A～2F, it shows the processing procedure profile according to the method for minimizing buried regions contact zones of the present invention outdiffusion.
Shown in Fig. 2 A, semiconductor substrate 100 at first is provided, be formed with bed course structure on it, comprise silicon nitride layer 120 and silicon oxide layer 110.This cushion layer structure is in the process of follow-up making shallow isolating trough structure (STI), as cmp (chemical mechanical polishing; CMP) stop layer.Then, define the position of groove with patterned light blockage layer (not shown) after, form a groove 105 in this semiconductor-based end 100 with etching step.Above-mentioned etching step for example is to use anisotropic etching, reactive ion etching (RIE) for example, and its etching gas can use and for example comprise Cl
2, HBr, O
2, N
2, NF
3, SF
6And CF
4Deng mist.
Then, the lower part formation at groove 105 comprises buried electrode plate 115, the capacitance dielectric layer 116 of compliance formation and the capacitor C of battery lead plate 117.Above-mentioned buried electrode plate 115 is a N+ type doped region, be arranged in the substrate of groove 105 bottoms, 117 of the battery lead plates polysilicons for mixing, 116 of capacitance dielectric layers are the layered structure of silica-silicon nitride (ON) for example, or are the layered structure of silica-silicon-nitride and silicon oxide (ONO).The formation of above-mentioned capacitor can be undertaken by conventional approaches, and the dielectric layer that a N+ type mixes, for example arsenic silex glass (Arsenic Silicon Glass are formed on sidewall and bottom that its detailed step is included in groove 105; ASG) after, the photoresist of inserting a set degree of depth is in groove 105, at the dielectric layer that removes not the doping that is covered by photoresist with wet etching, then remove photoresist, and compliance deposits an insulating barrier, tetraethoxysilane (TEOS) for example, be diffused in follow-up hot processing procedure in order to the ion that prevents to mix in the groove 105 sidewalls substrate on every side of the dielectric layer covering that is not doped, then the ion in the dielectric layer that mixes is driven in substrate, form N+ type doped region as buried electrode plate 115 with hot processing procedure.Then, remove the dielectric layer of insulating barrier and doping, compliance deposits sidewall and the bottom of a dielectric layer in groove again, as capacitance dielectric layer 116, and deposits a conductive layer and fills up groove 105, with as battery lead plate 117.
After finishing above-mentioned capacitance structure, shown in Fig. 2 B, compliance deposits an insulating barrier, for example behind silica or the silicon oxynitride, removes the insulating barrier of cushion layer structure and electric capacity top to form a ring-type insulating barrier 140 with etching mode.Above-mentioned ring-type insulating barrier for example can use thermal oxidation method or cooperate anisotropic etching to form with chemical vapour deposition technique.Above-mentioned anisotropic etching for example is a reactive ion etching (RIE), can use to comprise CHF
3, Ar, O
2, C
4F
8, CO etc. mist.Greater than horizontal direction, so it has high selectivity to above-mentioned anisotropic etching for the removing speed of vertical direction, can keep material on the sidewall and remove material on the horizontal direction simultaneously.In the present embodiment, the thickness of ring-type insulating barrier 140 is preferably 200～300nm.Then, deposition one first conductive layer 150 fills up groove 105 shown in Fig. 2 C, and etch-back makes this first conductive layer 150 to both allocations.Above-mentioned first conductive layer 150, ring-type insulating barrier 140 promptly constitute conductor structure.
Next, shown in Fig. 2 D, compliance deposits a conductive layer 160, for example behind the polysilicon of Can Zaing, removes the conductive layer of cushion layer structure and conductor structure top to form just like the sidewall conductive layer 160 ' shown in Fig. 2 E in the anisotropic etching mode.Above-mentioned anisotropic etching for example is a reactive ion etching (RIE), can use to comprise CHF
3, Ar, O
2, C
4F
8, CO etc. mist.The polysilicon of the doping that above-mentioned sidewall conductive layer is preferable, its preferred concentration are second conductive layer that is lower than follow-up formation, and scope is at 0～1E14 atoms/cm
3Between, that is to say that above-mentioned sidewall conductive layer also can be the polysilicon layer of undoped.
Then, shown in Fig. 2 F, fill up second conductive layer 170 in sidewall conductive layer 160 ' area surrounded, this second conductive layer is generally the polysilicon of doping, and its concentration is higher than above-mentioned sidewall conductive layer.Then, make ions diffusion to substrate 100, form buried regions contact zones 135 with the thermal diffusion processing procedure.Be doped in the relative higher concentration ion in second conductive layer 170, because the thermal diffusion effect, after containing the relatively low sidewall conductive layer 160 ' of ion concentration, diffuse to by second conductive layer 170 and to form above-mentioned buried regions contact zones 135 in the substrate on every side 100.
Then, can use cmp that this second conductive layer 170 is polished, as described above, this moment, above-mentioned cushion layer structure was promptly as the stop layer of cmp.
Method as above-mentioned minimizing buried regions contact zones outdiffusion, when being applied to the formation of semiconductor memory system, as shown in Figure 3, can be after finishing above-mentioned steps, with light shield develop and etching step in a side of this groove, after defining the zone of shallow trench isolation structure and removing, insert dielectric material again, for example silica and form shallow trench isolation structure 155.Forming by gate 125 and be positioned at the transistor that the doped region N+ of gate both sides is formed at this groove then with respect to the opposite side of this shallow trench isolation structure.Above-mentioned shallow trench isolation structure and transistorized formation can be used industry technology commonly used, do not belong to major technology feature of the present invention, therefore will not give unnecessary details.
According to the foregoing description, reduce the semiconductor structure of buried regions contact zones outdiffusion, as shown in Figure 3, comprising: a transistor that has gate 125 and be positioned at the doped region N+ of above-mentioned gate both sides; The one buried regions contact zones 135 that one of are connected to mutually among the above-mentioned two doped region N+; One with these buried regions contact zones 135 adjacent grooves 105; One is formed at the groove type capacitance C of the bottom of this groove, and it comprises embedded electrode plate 115, capacitance dielectric layer 116 and battery lead plate 117; One is positioned at the conductor structure on this groove type capacitance, comprises ring-type insulating barrier 140 and first conductive layer 150 that is surrounded by the ring-type insulating barrier; One is formed at the sidewall conductive layer 160 ' of the sidewall of this groove; One second conductive layer 170 that is surrounded by this sidewall conductive layer; And a shallow trench isolation structure 155, be positioned at the opposite side of this groove with respect to these buried regions contact zones 135; Wherein these buried regions contact zones 135 join with the sidewall conductive layer 160 ' in the groove, and the doping content of this sidewall conductive layer 160 ' is lower than this second conductive layer 170.
According to the structure and the method for minimizing buried regions contact zones of the present invention outdiffusion, by on the sidewall of the first half of groove type capacitance, form a concentration be lower than second conductive layer or even unadulterated sidewall conductive layer, and can reduce the outdiffusion of buried regions contact zones; In addition, according to the present invention, the distance between first conductive layer and second conductive layer reduces, and also can reduce resistance (resistance) between the two, thereby can promote the semiconductor subassembly performance.
Claims (25)
1. semiconductor structure that reduces the outdiffusion of buried regions contact zones, it is characterized in that: described semiconductor structure comprises:
One transistor, the doped region that comprises gate and be positioned at above-mentioned gate both sides;
One buried regions contact zones are connected to one of above-mentioned two doped regions mutually;
One groove is adjacent with these buried regions contact zones;
One groove type capacitance is formed at the bottom of this groove, comprises embedded electrode plate, capacitance dielectric layer and battery lead plate;
One conductor structure is positioned on this groove type capacitance, and this conductor structure comprises ring-type insulating barrier and first conductive layer that is surrounded by the ring-type insulating barrier;
One sidewall conductive layer is formed at the sidewall of this groove;
One second conductive layer is surrounded by this sidewall conductive layer;
One shallow trench isolation structure is positioned at the opposite side of this groove with respect to these buried regions contact zones;
Wherein the sidewall conductive layer in these buried regions contact zones and the groove is joined, and the doping content of this sidewall conductive layer is lower than this second conductive layer.
2. the semiconductor structure of minimizing buried regions contact zones according to claim 1 outdiffusion is characterized in that: the polysilicon of this first conductive layer for mixing.
3. the semiconductor structure of minimizing buried regions contact zones according to claim 1 outdiffusion is characterized in that: this ring-type insulating barrier is a silicon nitride.
4. the semiconductor structure of minimizing buried regions contact zones according to claim 1 outdiffusion is characterized in that: the polysilicon of this second conductive layer for mixing.
5. the semiconductor structure of minimizing buried regions contact zones according to claim 1 outdiffusion is characterized in that: the polysilicon concentration of this sidewall conductive layer is lower than 1E14atom/cm
3
6. the semiconductor structure of minimizing buried regions contact zones according to claim 1 outdiffusion is characterized in that: this sidewall conductive layer is unadulterated polysilicon.
7. method that reduces the outdiffusion of buried regions contact zones comprises:
Provide a semiconductor-based end that is formed with a bed course structure and a groove, and this channel bottom is formed with a groove type capacitance;
On the sidewall of this groove, form a ring-type insulating barrier;
In this ring-type insulating barrier area surrounded, form one first conductive layer;
Form a sidewall conductive layer on this trenched side-wall;
Form one second conductive layer in this sidewall conductive layer area surrounded, wherein the doping content of this sidewall conductive layer is lower than this second conductive layer.
8. the method for minimizing buried regions contact zones according to claim 7 outdiffusion, wherein this bed course structure comprises a nitration case and an oxide layer.
9. the method for minimizing buried regions contact zones according to claim 7 outdiffusion, the wherein polysilicon of this first conductive layer for mixing.
10. the method for minimizing buried regions contact zones according to claim 7 outdiffusion, wherein this ring-type insulating barrier is a silicon nitride.
11. the method for minimizing buried regions contact zones according to claim 7 outdiffusion, the wherein polysilicon of this second conductive layer for mixing.
12. the method for minimizing buried regions contact zones according to claim 7 outdiffusion, wherein the polysilicon concentration of this sidewall conductive layer is lower than 1E14atom/cm
3
13. the method for minimizing buried regions contact zones according to claim 7 outdiffusion, wherein this sidewall conductive layer is unadulterated polysilicon.
14. the method for minimizing buried regions contact zones according to claim 7 outdiffusion also comprises with the surface rubbing of cmp with this second conductive layer.
15. the method for minimizing buried regions contact zones according to claim 7 outdiffusion, wherein this groove type capacitance comprises a capacitance dielectric layer, embedded electrode plate and battery lead plate.
16. the method for minimizing buried regions contact zones according to claim 7 outdiffusion also comprises forming the buried regions contact zones and this sidewall conductive layer is joined.
17. a method that forms semiconductor memory system, its step comprises:
Provide a semiconductor-based end that is formed with a bed course structure and a groove, and this channel bottom is formed with a groove type capacitance;
On the sidewall of this groove, form a ring-type insulating barrier;
In this ring-type insulating barrier area surrounded, form one first conductive layer;
Form a sidewall conductive layer on this trenched side-wall;
Form one second conductive layer in this sidewall conductive layer area surrounded, wherein the doping content of this sidewall conductive layer is lower than this second conductive layer;
With light shield develop and etching step in a side of this groove, after defining the zone of shallow trench isolation structure and removing, insert dielectric material and form shallow trench isolation structure;
Forming by gate and be positioned at the transistor that the doped region of gate both sides is formed at this groove with respect to the opposite side of this shallow trench isolation structure.
18. the method for formation semiconductor memory system according to claim 16 also comprises forming the buried regions contact zones between this transistorized doped region and this sidewall conductive layer.
19. the method for formation semiconductor memory system according to claim 16, wherein this groove type capacitance comprises a capacitance dielectric layer, embedded electrode plate and battery lead plate.
20. the method for formation semiconductor memory system according to claim 16, wherein this bed course structure comprises a nitration case and an oxide layer.
21. the method for formation semiconductor memory system according to claim 16, the wherein polysilicon of this first conductive layer for mixing.
22. the method for formation semiconductor memory system according to claim 16, wherein this ring-type insulating barrier is a silicon nitride.
23. the method for formation semiconductor memory system according to claim 16, the wherein polysilicon of this second conductive layer for mixing.
24. the method for formation semiconductor memory system according to claim 16, wherein the polysilicon concentration of this sidewall conductive layer is lower than 1E14atom/cm
3
25. the method for formation semiconductor memory system according to claim 16, wherein this sidewall conductive layer is unadulterated polysilicon.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03122473 CN1264221C (en) | 2003-04-28 | 2003-04-28 | Semiconductor structure reducing external diffusion of buried layer contact tape, method for making the same and forming method for semiconductor storage device |
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| CN 03122473 CN1264221C (en) | 2003-04-28 | 2003-04-28 | Semiconductor structure reducing external diffusion of buried layer contact tape, method for making the same and forming method for semiconductor storage device |
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| CN1542970A true CN1542970A (en) | 2004-11-03 |
| CN1264221C CN1264221C (en) | 2006-07-12 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687662A (en) * | 2019-10-18 | 2021-04-20 | 南亚科技股份有限公司 | Semiconductor element and method for manufacturing the same |
| CN113517232A (en) * | 2021-07-08 | 2021-10-19 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method |
-
2003
- 2003-04-28 CN CN 03122473 patent/CN1264221C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687662A (en) * | 2019-10-18 | 2021-04-20 | 南亚科技股份有限公司 | Semiconductor element and method for manufacturing the same |
| CN112687662B (en) * | 2019-10-18 | 2024-03-15 | 南亚科技股份有限公司 | Semiconductor element and method for manufacturing the same |
| CN113517232A (en) * | 2021-07-08 | 2021-10-19 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method |
| CN113517232B (en) * | 2021-07-08 | 2023-09-26 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method |
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| Publication number | Publication date |
|---|---|
| CN1264221C (en) | 2006-07-12 |
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