CN1532689A - Processor and method by using batten check to switch instruction mode - Google Patents
Processor and method by using batten check to switch instruction mode Download PDFInfo
- Publication number
- CN1532689A CN1532689A CNA031072771A CN03107277A CN1532689A CN 1532689 A CN1532689 A CN 1532689A CN A031072771 A CNA031072771 A CN A031072771A CN 03107277 A CN03107277 A CN 03107277A CN 1532689 A CN1532689 A CN 1532689A
- Authority
- CN
- China
- Prior art keywords
- bit
- instruction
- mode
- words group
- coordination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Detection And Correction Of Errors (AREA)
Abstract
The instruction mode switching method is for switching between N bit mode and 2N bit mode. Each N bit word block includes P parity bits and (N-P) bits of instruction code, parity bits of each instruction in N bit mode set the N bit word block in the first parity state while parity bits of each instruction in 2N bit mode set the N bit word block in the second parity state. The processor includes one instruction input device with 2N bit memory space for saving several 2N bit instruction word blocks, one instruction pick-up device for picking up one 2N word block from the instruction input device, and one execution mode switching logic for judging whether the picked 2N word block is either two (N-P) bit instructions or one 2(N-P) bit instruction.
Description
Technical field
The invention relates to the technical field of processor, refer to that especially a kind of parity check that utilizes is to carry out instruction mode switching processing device and method in computer apparatus.
Background technology
General processor has the instruction mode of one 32 bits/16 bits, and in these two kinds of mode switch execution, store required space to save procedure code, in U.S. USP 5,758, in No. 115 patent case bulletins, be with programmable counter (Program Counter, PC) the T bit in is positioned at 32 bits or 16 bit instruction modes to determine this preparation implement, and the value of utilizing branch (Branch) instruction to come T bit in the changeover program counter, its instruction mode switches as shown in Figure 1, when carrying out branch (Branch) instruction 220, the start address Badd (1) that to be branch store to the instruction of (Branch to) 16 bits also carries out the instruction of 16 bits, be somebody's turn to do the+1st, be positioned at 16 bit instruction modes to indicate this processor in order to switch this T bit, when carrying out branch (Branch) instruction 240, the address Badd (2) that to be branch store to the instruction of (Branch to) 32 bits also carries out the instruction of 32 bits, be somebody's turn to do the+0th, in order to this T bit is changed into ' 0 ', to indicate this processor to be positioned at 32 bit instruction modes, taking this kind changing method that ARM and MIPS are arranged is the processor of row, yet take the 32 bits instruction of this kind changing method and the instruction of 16 bits need be stored in different blocks respectively, instruction of 32 bits and the instruction of 16 bits can't be mingled with leaves same block in, so the procedure code storage area can't obtain optimization.
Can't be mingled with the problem that is stored in same block at instruction of 32 bits and the instruction of 16 bits, U.S. USP 6,209, in the 079B1 patent case bulletin, be with higher bit (the Most Significant Bit in the order code, MSB) bit solves the instruction of 32 bits and the instruction of 16 bits can't be mingled with the problem that is stored in same block to determine this preparation implement to be positioned at 32 bits or 16 bit instruction modes, as shown in Figure 2, if if in the MSB ' 1 ' of 32 bit boundaries, then this 32 bit is represented the instruction of one 32 bits, if if in the MSB ' 0 ' of 32 bit boundaries, then this 32 bit is represented two 16 bit instructions, if if the MSB ' 0 ' of 16 bits instruction B, then be expressed as two 16 bits instructions of carrying out in proper order, if if the MSB ' 1 ' of 16 bits instruction B, then be expressed as the 16 bits instruction of two parallel execution, take this kind changing method that the processor of M32R series is arranged, in this kind changing method, instruction of 32 bits and the instruction of 16 bits need not to be stored in respectively different blocks, and reach the purpose that improves procedure code density (Code Density), yet, when carrying out branch (branch) or jump (jump) instruction, need handled, in order to avoid jump to the latter part of one 32 bits instruction, because the latter part of this 32 bit instruction is not an executable instruction, can produce the mistake that to expect, therefore jumping address need be limited in block boundary (word boundary) or 32 bit boundaries (32-bit boundary), return address (return address) for branch one link (branch-and-link) and link (jump-and-link) instruction of jumping also need be limited in block boundary (word boundary) or 32 bit boundaries (32-bit boundary), this kind restriction can increase the inconvenience on using, simultaneously, use the processor of above-mentioned technology when carrying out branch or skip instruction, to there is no any fault-tolerant design, that is when this processor produces wrong jumping address because of hardware or external interference, this processor promptly can be handled and make total system stagnate (halt), therefore, the design of the instruction mode transform method of existing 32 bits/16 bits still has many disappearances and gives improved necessity.
The inventor whence originally in the spirit of positive invention, is urgently thought a kind of " a kind of parity check that utilizes is to carry out instruction mode switching processing device and method " that can address the above problem because of in this, and several times research experiment is eventually to finishing the present invention.
Summary of the invention
The objective of the invention is is providing a kind of parity check that utilizes to carry out instruction mode switching processing device and method, to avoid prior art jumping address to be limited in block boundary or the caused challenge of 32 bit boundaries because of need, simultaneously, improve the degree of stability of procedure code density and increase system and reach fault-tolerant purpose.
According to a characteristic of the present invention, be that proposition is a kind of to carry out instruction mode switching processing device with the bit inspection, it can carry out N bit and the instruction of 2N bit mode respectively at N bit and 2N bit mode, this N bit mode instruction is made up of a N bit words group, this 2N bit mode instruction is made up of two N bit words groups, each N bit words group comprises P coordination bit and reaches (N-p) order code of bit, P is the integer more than or equal to 1, wherein, the coordination bit of each N bit mode instruction is that its N bit words group is set at the first coordination state, the coordination bit of each N bit words group of each 2N bit mode instruction is that its N bit words group is set at the second coordination state, this processor comprises an instruction inputting device, an one instruction capture device and an execution pattern switch logic, it is the 2N bit words group of the storage space of 2N bit for a plurality of representatives instructions of storage that this instruction inputting device comprises a width, this instruction capture device is in order to capture a 2N bit words group of this order code input media, and this execution pattern switch logic is instruction of two (N-P) bits or the instruction of one 2 (N-P) bit in order to the 2N bit words group of judging acquisition, be executed in N bit or 2N bit mode with handoff processor, wherein, when the 2N bit words group of acquisition is even parity, be the first coordination state as two N bit words groups that comprised, judge the instruction that this 2N bit words group is two (N-P) bits, be the second coordination state as two N bit words groups that comprised, judge the instruction that this 2N bit words group is one 2 (N-P) bit.
According to another characteristic of the present invention, be propose a kind of in processor to carry out the method that instruction mode switches with the bit inspection, this processor can be executed in N bit and 2N bit mode, this processor comprises an instruction inputting device, it provides instruction of N bit mode and the instruction of 2N bit mode, this N bit mode instruction is made up of a N bit words group, this 2N bit mode instruction is made up of two N bit words groups, each N bit words group comprises P coordination bit and reaches (N-P) order code of bit, P is the integer more than or equal to 1, wherein, the coordination bit of each N bit mode instruction is that its N bit words group is set at the first coordination state, the coordination bit of each N bit words group of each 2N bit mode instruction is that its N bit words group is set at the second coordination state, and this method comprises: (A) the 2N bit words group of acquisition one representative instruction; (B) when the 2N bit words group of acquisition when being specific coordination state, be the first coordination state, judge the instruction that this 2N bit words group is two (N-P) bits, and handoff processor be executed in the N bit mode as two N bit words groups that it comprised; And, be the second coordination state as two N bit words groups that comprised (C) when the 2N bit words group of acquisition when being specific coordination state, judge the instruction that this 2N bit words group is one 2 (N-P) bit, and handoff processor is executed in the 2N bit mode.
Because modern design of the present invention can provide on the industry and utilize, and truly have the enhancement effect, so apply for patent of invention in accordance with the law.
Description of drawings
For further specifying technology contents of the present invention, be described in detail as follows below in conjunction with embodiment and accompanying drawing, wherein:
Fig. 1 is the synoptic diagram that existing instruction mode switches.
Fig. 2 is the synoptic diagram that another existing instruction mode switches.
Fig. 3 is that a kind of parity check that utilizes of the present invention is to carry out the Organization Chart of instruction mode switching processing device.
Fig. 4 is the package of the present invention synoptic diagram that the coordination bit produces when translating.
Fig. 5 is the program of the present invention synoptic diagram that the coordination bit is checked when carrying out.
Fig. 6 is a coordination bit look-up table of the present invention.
Fig. 7 is the arrangement mode of a program in memory location and the synoptic diagram of six kinds of different jumping address states.
Fig. 8 is the package of the present invention synoptic diagram that another parity check bit produces when translating.
Fig. 9 is another coordination bit look-up table of the present invention.
Figure 10 is a coordination bit look-up table more of the present invention.
Embodiment
Utilization of the present invention carries out instruction mode switching processing device with the bit inspection and method is to carry out N bit and the instruction of 2N bit mode respectively at N bit and 2N bit mode, this N bit mode instruction is made up of a N bit words group, this 2N bit mode instruction is made up of two N bit words groups, each N bit words group comprises P coordination bit and reaches (N-P) order code of bit, P is the integer more than or equal to 1, in present embodiment, the N value is preferably 16, the P value is preferably 1, but the convenience when it only is explanation is restriction usable range of the present invention and power.
Fig. 3 shows that the parity check that utilizes of the present invention is to carry out the system architecture of instruction mode switching processing device, it comprises an instruction inputting device 310, an one instruction capture device 320 and an execution pattern switch logic 330, it is the 32 bit words groups of the storage space of 2N=32 bit for a plurality of representatives instructions of storage that this instruction inputting device 310 comprises a width, this instruction capture device 320 is in order to capture one 32 bit words groups of this order code input media 310, this execution pattern switch logic 330 is the instruction of two N-P=15 bits or the instruction of one 2 (N-P)=30 bit in order to the 32 bit words groups of judging acquisition, is executed in 16 bits or 32 bit modes with handoff processor.
In present embodiment, this processor can be carried out N=16 bit and two kinds of patterns of 2N=32 bit, when the instruction set performed to this this processor (instruction set) encoded, this 16 bit mode instruction is made up of one 16 bit words group, each 16 bit modes instruction comprises the coordination bit of a bit, this coordination bit is higher bit (the MostSignificant Bit that is positioned at this 16 bit, MSB), but also can be arranged in any bit of this 16 bit, this 32 bit mode instruction is made up of two 16 bit words groups, each 16 bit words group comprises the order code of 1 coordination bit and 15 bits, and each coordination bit is the higher bit that is positioned at each 16 bit words group.
As shown in Fig. 4, if the specific coordination state of 32 bit words groups of representative instruction is an even parity, in 32 bit words groups if when comprising the instruction of two 16 bits, the 31st bit is the coordination bit of one 16 bit modes instruction, its be with the 30th bit to the 16 bits totally 15 bits carry out the result of XOR computing so that the 31st bit to the 16 bits become the even parity state; The 15th bit is the coordination bit of another 16 bit mode instruction, its be with the 14th bit to the 0 bit totally 15 bits carry out the result of XOR computing so that the 15th bit to the 0 bit becomes the even parity state; That is 16 the bit words group be set at the first coordination state (even parity state).
Comprise two coordination bits in each 32 bit modes instruction, that is in 32 bit words groups, if when comprising one 30 bit instruction, the 31st bit is the 30th bit to the 16 bits result of totally 15 bits execution XNOR computing, so that the 31st bit to the 16 bits become the odd-parity state; The 15th bit is the 14th bit to the 0 bit result of totally 15 bits execution XNOR computing, so that the 15th bit to the 0 bit becomes the odd-parity state; The coordination bit of each 16 bit words group of each 32 bit modes instruction is that its 16 bit words group is set at the second coordination state (odd-parity state).
After a program is translated via an assembler (assembler) group, representative is that a width that is stored in this instruction inputting device 310 is the storage space of 32 bits according to a plurality of machinery sign indicating numbers of program, carry out for this processor, this instruction capture device 320 is in order to capture-32 bit words groups of this order code input media 310, this execution pattern switch logic 330 is the instruction of two 15 bits or the instruction of one 30 bit in order to the 32 bit words groups of judging acquisition, is executed in 16 bits or 32 bit modes to switch this processor.
This execution pattern switch logic 330 at first as shown in Figure 5, to the 31st bit to the 16 bits of 32 bit words groups of this acquisition carry out a mutual exclusion or (XOR) computing to obtain a UHP signal (Upper Half Parity) 510, the 15th bit to the 0 bit is carried out a mutual exclusion exclusive disjunction to obtain a LHP signal (Lower Half Parity) 520, again this UHP signal 510 and LHP signal 520 are carried out a mutual exclusion exclusive disjunction to obtain a WP signal (WordParity) 530, this execution pattern switch logic 330 is again according to this UHP signal 510, LHP signal 520 and WP signal 530 are executed in 16 bits or 32 bit modes to judge this processor.
As shown in Figure 6, when this WP signal 530 is even parity (E), the 32 bit words groups of representing this acquisition include a correct instruction at least, when UHP signal 510 and LHP signal 520 are even parity (E), the 32 bit words groups of representing this acquisition comprise two 15 bit instructions, and UHP signal 510 and LHP signal 520 represent that 32 bit words groups of this acquisition comprise one 30 bit instruction when being odd-parity (O).
When WP signal 530 is odd-parity (O), representing that 32 bit words groups of this acquisition do not comprise normal instruction, is a special state.And this special state has following several possibility: the non-procedure code section in 32 bit words groups zone of (1) this acquisition; (2) 32 bit words groups of this acquisition are the procedure code sections, but bit is wrong, just can cause effective even parity (E) to become odd-parity (O); (3) represent other special state exchanges.In embodiments of the present invention, can WP signal 530 is wrong for odd-parity (O) is defined as bit, with as the whether wrong inspection of data bit.
Fig. 7 is that the program that shows is translated its arrangement mode in memory location of machinery sign indicating number that the back is produced through technology groups of the present invention, wherein some order format only needs to carry out 15 bits instructions and gets final product, some order format then needs to carry out the instruction of 30 bits, therefore produce 30 bits of a sequence and the procedure code that the instruction of 15 bits mixes, as shown in Fig. 7, according to technology of the present invention, instruction of 32 bit modes and 16 mode bits instruct to be mingled with and are stored in same block, and reach the purpose that improves procedure code density (Code Density).
According to technology of the present invention, this processor need not to specify the command status of jumping address destination can judge correct instruction mode, that is this processor is because of there being this execution pattern switch logic 330, it can judge correct instruction mode automatically according to the data content of jumping address, Fig. 7 also shows the correct instruction mode that six kinds of different jumping address states of this processor and this execution pattern switch logic 330 are judged, each state description is as follows:
State (1): this processor jumps to one 32 bit boundaries (32-bit boundary), and this WP=this moment (E) table is effective instruction, (UHP, IHP)=(O, O) table is one 30 bit instruction, so this processor is carried out this one 30 bit instruction.
State (2): this processor jumps to one 32 bit boundaries, and this WP=this moment (E) table is effective instruction, (UHP, LHP)=(E, E) table is two 15 bit instructions, so this processor is carried out first 15 bit instruction.
State (3): this processor does not jump to one 32 bit boundaries, and this WP=this moment (E) table is effective instruction, (UHP, LHP)=(E, E) table is two 15 bit instructions, so this processor is carried out second 15 bit instruction.
State (4): this processor does not jump to one 32 bit boundaries, and this WP=this moment (E) table is effective instruction, (UHP, LHP)=(O, O) table is one 30 bit instruction, is error condition therefore, so this processor sends exception (Exception) signal.
State (5): this processor jumps to one 32 bit boundaries, and this WP=this moment (O) table is special state, so this processor sends exception (Exception) signal for illegal command.
State (6): this processor does not jump to one 32 bit boundaries, and this WP=this moment (O) table is special state, so this processor sends exception (Exception) signal for illegal command.
As shown in Fig. 8, the first coordination state also can adopt the odd-parity state and second coordination state employing even parity state, that is in 32 bit words groups if when comprising the instruction of two 16 bits, the 31st bit is the parity check bit of one 16 bit modes instruction, its be with the 30th bit to the 16 bits totally 15 bits carry out the result of XNOR computing so that the 31st bit to the 16 bits become the odd-parity state; The 15th bit is the coordination bit of another 16 bit mode instruction, its be with the 14th bit to the 0 bit totally 15 bits carry out the result of XNOR computing so that the 15th bit to the 0 bit becomes the odd-parity state; That is 16 the bit words group be set at the first coordination state (odd-parity state).
Comprise two coordination bits in each 32 bit modes instruction, that is in 32 bit words groups if when comprising the instruction of one 30 bit, the 31st bit is the 30th bit to the 16 bits result of totally 15 bits execution XOR computing, so that the mat woven of fine bamboo strips 31 bits to the 16 bits become the even parity state; The 15th bit is the 14th bit to the 0 bit result of totally 15 bits execution XOR computing, so that the 15th bit to the 0 bit becomes the even parity state; The coordination bit of each 16 bit words group of each 32 bit modes instruction is that its 16 bit words group is set at the second coordination state (even parity state).
Implement in the framework at another kind, if the specific coordination state of 32 bit words groups of representative instruction is an odd-parity, that is WP=O (odd-parity), at this moment, because normal instruction is odd-parity, then the parity check signal UHP of the 31st bit to the 16 bits is certain opposite with the parity check signal LHP of the 15th bit to the 0 bit.This moment, if UHP is the first coordination state, then LHP was the second coordination state in normal instruction, that is, in normal instruction (WP=O), if when establishing the first coordination state and being even parity (E), when being UHP=E, represent in this 32 bit words group, comprise two 15 bit instructions; In normal instruction (WP=O), if when establishing the first coordination state and being odd-parity (O), promptly during UHP=O, represent in this 32 bit words group, comprise one 30 bit instruction, the coordination bit look-up table of this moment, as shown in Figure 9.
Figure 10 shows another kind of coordination bit look-up table, in normal instruction (WP=O), if when establishing the first coordination state and being odd-parity (O), when being UHP=O, represent in this 32 bit words group, comprise two 15 bit instructions, in normal instruction (WP=O), and during UHP=E, represent in this 32 bit words group, comprise one 30 bit instruction.
From the above, owing to use technology of the present invention, this processor need not to worry to jump to the latter part of one 32 bits instruction when carrying out branch (branch) or jumping (jump) instruction, this moment is as state (4), this processor sends exception (Exception) signal, therefore jumping address need not to be limited in block boundary or 32 bit boundaries, in like manner, return address for branch-link and the instruction of jump-link also need not to be limited in block boundary or 32 bit boundaries, not only improve procedure code density (Code Density), also increase the convenience of using, simultaneously, when processor jumps to wrong position or this processor and produces wrong jumping address because of hardware or external interference carrying out branch or skip instruction, this processor can send the exception signal, can not make the mistake that total system is paused (halt) or generation can not be expected to allow operating system handle,, and reach fault-tolerant purpose with the degree of stability of increase system.
To sum up institute is old, and no matter the present invention all is different from the feature of prior art with regard to purpose, means and effect, in fact is one to have the invention of practical value.Only it should be noted that above-mentioned many embodiment give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (18)
1. one kind to carry out instruction mode switching processing device with the bit inspection, it can carry out N bit and the instruction of 2N bit mode respectively at N bit and 2N bit mode, this N bit mode instruction is made up of a N bit words group, this 2N bit mode instruction is made up of two N bit words groups, each N bit words group comprises P coordination bit and reaches (N-P) order code of bit, P is the integer more than or equal to 1, wherein, the coordination bit of each N bit mode instruction is that its N bit words group is set at the first coordination state, the coordination bit of each N bit words group of each 2N bit mode instruction is that its N bit words group is set at the second coordination state, it is characterized in that this processor comprises:
One instruction inputting device, it comprises a width is the 2N bit words group of the storage space of 2N bit for a plurality of representatives instructions of storage;
One instruction capture device is in order to capture a 2N bit words group of this order code input media; And
One execution pattern switch logic is instruction of two (N-P) bits or the instruction of one 2 (N-P) bit in order to the 2N bit words group of judging acquisition, is executed in N bit or 2N bit mode with handoff processor;
Wherein, when the 2N bit words group of acquisition is even parity, be the first coordination state as two N bit words groups that comprised, judge the instruction that this 2N bit words group is two (N-P) bits, be the second coordination state as two N bit words groups that comprised, judge the instruction that this 2N bit words group is one 2 (N-P) bit.
2. as claimed in claim 1ly it is characterized in that to carry out instruction mode switching processing device with the bit inspection wherein, this first coordination state is an even parity, this second coordination state is an odd-parity.
3. as claimed in claim 1ly it is characterized in that to carry out instruction mode switching processing device with the bit inspection wherein, this N value is 16, the P value is 1.
One kind in processor to carry out the method that instruction mode switches with the bit inspection, this processor can be executed in N bit and 2N bit mode, this processor has an instruction set, it provides instruction of N bit mode and the instruction of 2N bit mode, this N bit mode instruction is made up of a N bit words group, this 2N bit mode instruction is made up of two N bit words groups, each N bit words group comprises P coordination bit and reaches (N-P) order code of bit, P is the integer more than or equal to 1, wherein, the coordination bit of each N bit mode instruction is that its N bit words group is set at the first coordination state, the coordination bit of each N bit words group of each 2N bit mode instruction is that its N bit words group is set at the second coordination state, it is characterized in that this method comprises:
The 2N bit words group of acquisition one representative instruction; And
When the 2N bit words group of acquisition is even parity, be the first coordination state as two N bit words groups that it comprised, judge the instruction that this 2N bit words group is two (N-P) bits, and handoff processor is executed in the N bit mode; And
When the 2N bit words group of acquisition is even parity, be the second coordination state as two N bit words groups that comprised, judge the instruction that this 2N bit words group is one 2 (N-P) bit, and handoff processor is executed in the 2N bit mode.
5. as claimed in claim 4 in processor to carry out the method that instruction mode switches with the bit inspection, it is characterized in that wherein, this first coordination state is an even parity, this second coordination state is an odd-parity.
6. as claimed in claim 4 in processor to carry out the method that instruction mode switches with the bit inspection, wherein, this N value is 16, the P value is 1.
7. one kind to carry out instruction mode switching processing device with the bit inspection, it can carry out N bit and the instruction of 2N bit mode respectively at N bit and 2N bit mode, this N bit mode instruction is made up of a N bit words group, this 2N bit mode instruction is made up of first N bit words group and second N bit words group, each N bit words group comprises the order code of P coordination bit and bit, P is the integer more than or equal to 1, wherein, the coordination bit of each first N bit mode instruction is that its N bit words group is set at the first coordination state, the coordination bit of each second N bit mode instruction is that its N bit words group is set at the second coordination state, each 2N bit mode instruction is set at the second coordination state, it is characterized in that this processor comprises:
One instruction inputting device, it comprises a width is the 2N bit words group of the storage space of 2N bit for a plurality of representatives instructions of storage;
One instruction capture device is in order to capture a 2N bit words group of this order code input media; And
One execution pattern switch logic is instruction of two (N-P) bits or the instruction of one 2 (N-P) bit in order to the 2N bit words group of judging acquisition, is executed in N bit or 2N bit mode with handoff processor;
Wherein, when the 2N bit words group of acquisition is odd-parity, as first N bit words group of being comprised is the first coordination state, judge the instruction that this 2N bit words group is two (N-P) bits, as first N bit words group of being comprised is the second coordination state, judges the instruction that this 2N bit words group is one 2 (N-P) bit.
8. as claimed in claim 7ly it is characterized in that to carry out instruction mode switching processing device with the bit inspection wherein, this first coordination state is an even parity, this second coordination state is an odd-parity.
9. as claimed in claim 7ly it is characterized in that to carry out instruction mode switching processing device with the bit inspection wherein, this N value is 16, the P value is 1.
One kind in processor to carry out the method that instruction mode switches with the bit inspection, this processor can be executed in the N bit and the 2N bit mode is carried out N bit and the instruction of 2N bit mode, this N bit mode instruction is made up of a N bit words group, this 2N bit mode instruction is made up of first N bit words group and second N bit words group, each N bit words group comprises P coordination bit and reaches (N-P) order code of bit, P is the integer more than or equal to 1, wherein, the coordination bit of each first N bit mode instruction is that its N bit words group is set at the first coordination state, the coordination bit of each second N bit mode instruction is that its N bit words group is set at the second coordination state, each 2N bit mode instruction is set at the second coordination state, it is characterized in that this method comprises:
The 2N bit words group of acquisition one representative instruction; And
When the 2N bit words group of acquisition is odd-parity, be the first coordination state as first N bit words group that it comprised, judge the instruction that this 2N bit words group is two (N-P) bits, and handoff processor is executed in the N bit mode; And
When the 2N bit words group of acquisition is odd-parity, be the second coordination state as first N bit words group that it comprised, judge the instruction that this 2N bit words group is one 2 (N-P) bit, and handoff processor is executed in the 2N bit mode.
11. as claimed in claim 10 in processor to carry out the method that instruction mode switches with the bit inspection, it is characterized in that wherein, this first coordination state is an even parity, this second coordination state is an odd-parity.
12. as claimed in claim 10 in processor to carry out the method that instruction mode switches with the bit inspection, it is characterized in that wherein, this N value is 16, the P value is 1.
13. one kind to carry out instruction mode switching processing device with the bit inspection, it can carry out N bit and the instruction of 2N bit mode respectively at N bit and 2N bit mode, this N bit mode instruction is made up of a N bit words group, this 2N bit mode instruction is made up of first N bit words group and second N bit words group, each N bit words group comprises P coordination bit and reaches (N-P) order code of bit, P is the integer more than or equal to 1, wherein, the coordination bit of each first N bit mode instruction is that its N bit words group is set at the second coordination state, the coordination bit of each second N bit mode instruction is that its N bit words group is set at the first coordination state, each 2N bit mode instruction is set at the second coordination state, it is characterized in that this processor comprises:
One instruction inputting device, it comprises a width is the 2N bit words group of the storage space of 2N bit for a plurality of representatives instructions of storage;
One instruction capture device is in order to capture a 2N bit words group of this order code input media; And
One execution pattern switch logic is instruction of two (N-P) bits or the instruction of one 2 (N-P) bit in order to the 2N bit words group of judging acquisition, is executed in N bit or 2N bit mode with handoff processor;
Wherein, when the 2N bit words group of acquisition is odd-parity, as first N bit words group of being wrapped is the second coordination state, judge the instruction that this 2N bit words group is two (N-P) bits, as first N bit words group of being comprised is the first coordination state, judges the instruction that this 2N bit words group is one 2 (N-P) bit.
14. as claimed in claim 13ly it is characterized in that to carry out instruction mode switching processing device with the bit inspection wherein, this first coordination state is an even parity, this second coordination state is an odd-parity.
15. as claimed in claim 13ly it is characterized in that to carry out instruction mode switching processing device with the bit inspection wherein, this N value is 16, the P value is 1.
16. one kind in processor to carry out the method that instruction mode switches with the bit inspection, this processor can be executed in the N bit and the 2N bit mode is carried out N bit and the instruction of 2N bit mode, this N bit mode instruction is made up of a N bit words group, this 2N bit mode instruction is made up of first N bit words group and second N bit words group, each N bit words group comprises P coordination bit and reaches (N-P) order code of bit, P is the integer more than or equal to 1, wherein, the coordination bit of each first N bit mode instruction is that its N bit words group is set at the second coordination state, the coordination bit of each second N bit mode instruction is that its N bit words group is set at the first coordination state, each 2N bit mode instruction is set at the second coordination state, it is characterized in that this method comprises:
The 2N bit words group of acquisition one representative instruction; And
When the 2N bit words group of acquisition is odd-parity, be the second coordination state as first N bit words group that it comprised, judge the instruction that this 2N bit words group is two (N-P) bits, and handoff processor is executed in the N bit mode; And
When the 2N bit words group of acquisition is odd-parity, be the first coordination state as first N bit words group that it comprised, judge the instruction that this 2N bit words group is one 2 (N-P) bit, and handoff processor is executed in the 2N bit mode.
17. as claimed in claim 16 in processor to carry out the method that instruction mode switches with the bit inspection, it is characterized in that wherein, this first coordination state is an even parity, this second coordination state is an odd-parity.
18. as claimed in claim 16 in processor to carry out the method that instruction mode switches with the bit inspection, it is characterized in that wherein, this N value is 16, the P value is 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03107277A CN100595731C (en) | 2003-03-21 | 2003-03-21 | Processor and method by using batten check to switch instruction mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03107277A CN100595731C (en) | 2003-03-21 | 2003-03-21 | Processor and method by using batten check to switch instruction mode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1532689A true CN1532689A (en) | 2004-09-29 |
| CN100595731C CN100595731C (en) | 2010-03-24 |
Family
ID=34282929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN03107277A Expired - Fee Related CN100595731C (en) | 2003-03-21 | 2003-03-21 | Processor and method by using batten check to switch instruction mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100595731C (en) |
-
2003
- 2003-03-21 CN CN03107277A patent/CN100595731C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN100595731C (en) | 2010-03-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1264083C (en) | Method and apparatus for maintaining context while executing translated instructions | |
| CN1379874A (en) | Method of changing modes of code generation | |
| CN1293776A (en) | Zero overhead computer interrupts with task switching | |
| CN1100294C (en) | Central processing unit for preventing program malfunction | |
| CN1367895A (en) | Migration of different source languages to executing medium | |
| CN1295600C (en) | Windows program abnormality capturing and positioning method | |
| CN1764888A (en) | Branch based activity monitoring | |
| CN1477512A (en) | Embedded sorftware task endless loop monitoring method | |
| CN101046775A (en) | Fast-taking of lockable code and its processor, controller and control method | |
| CN1873610A (en) | Buffer storage collecting mechanism and collecting method for supporting multithread processor | |
| CN1532689A (en) | Processor and method by using batten check to switch instruction mode | |
| CN1295778C (en) | Method for verifying consistency of chip hardware behavior and software simulation behavior | |
| CN110187884B (en) | Memory access instruction instrumentation optimization method in multi-thread application scene | |
| CN101055542A (en) | Symbol debug method and system in cross integration development environment | |
| CN1519703A (en) | Computer multithreading test system capable of being combined and linked as well as its method | |
| CN1650258A (en) | Automatic task distribution in scalable processors | |
| CN1584844A (en) | On-line updating method and apparatus of single-chip apparatus | |
| CN1486459A (en) | Branch handling for single instruction multiple datapath processor architectures | |
| CN1592890A (en) | Event handling | |
| CN1096026C (en) | Programmable controller with skip processing part not tranfering control to CPU | |
| CN1293462C (en) | Processor and method for executing instruction set with different length | |
| CN1190738C (en) | Data processing device and its data read method | |
| CN1371053A (en) | Application program downloading method in compilation system platform of electronic communication equipment | |
| CN1632773A (en) | Interrupt processing apparatus and method in chip | |
| CN1841333A (en) | Dynamic random memory testing method and system thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100324 Termination date: 20150321 |
|
| EXPY | Termination of patent right or utility model |