CN101046775A - Fast-taking of lockable code and its processor, controller and control method - Google Patents
Fast-taking of lockable code and its processor, controller and control method Download PDFInfo
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- CN101046775A CN101046775A CNA2007101045052A CN200710104505A CN101046775A CN 101046775 A CN101046775 A CN 101046775A CN A2007101045052 A CNA2007101045052 A CN A2007101045052A CN 200710104505 A CN200710104505 A CN 200710104505A CN 101046775 A CN101046775 A CN 101046775A
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Abstract
An embodiment of the invention discloses a system and a method for cache locked encoding. In the embodiment, a processor comprises a cache and a cache controller. The cache is used for temporarily stores an encoding duplicate in a main memory. At the same time, the cache is divided into a plurality of cache ways, each cache way is divided into a plurality of cache way portions. The cache controller uses a first signal to appoint one of the cache way in the plurality of the cache ways as part cache channels, and uses a second signals to define which cache way poritions in the cache ways need to be locked.
Description
Technical field
The invention relates to processor, the System and method for that refers to a kind of high-speed cache especially and get the part locking soon.
Background technology
Circuit designers is devoted to reduce the data and the speed of instructing the required time to operate with the increase processor that capture storage from memory location.The method of a kind of OverDrive Processor ODP access code (code) is the coding duplicate that utilizes the last autonomous memory of the temporary processor of high-speed cache to read, because software program is got used to doing circulation thereby is captured position identical in the storer again and again, therefore in the process of linking up with processor, the portion-form that merges fast taking system can quicken to capture required sign indicating number, when being present in, the sign indicating number of processor requirement gets soon, be called " get soon and seek (cache hit) ", be not present in respect to the sign indicating number that requires and be called " getting error (cache miss) soon " in getting soon.The sign indicating number of " getting soon and seeking " can be captured more quickly, if error takes place to get soon, and the then necessary autonomous memory readout code of processor, and the time of required cost is the hundreds of times from the high-speed cache acquisition code.
Get soon is by getting controller (cache controller) control soon, including algorithm and store which sign indicating number with decision.Got soon when middle when a new sign indicating number autonomous memory captures and is allocated in, placement algorithm determines the sign indicating number which has been present in getting soon to be dropped.Above-mentioned placement algorithm is based under the notion of statistics probability, judges which sign indicating number most possibly will be used again.For example, " (round-robin) rotates " method be based on determined order simply with next position the sign indicating number abandon; And " minimum use (least recently used) " method is to continue to follow the trail of each to login the fast line taking (cache line) of getting soon and abandon the oldest sign indicating number, is complicated method.
When processor sends when requiring readout code, get soon controller can compare above-mentioned requirements sign indicating number the address with get soon in the address, get soon to confirm whether above-mentioned sign indicating number has been present in.For example, the address that the 4K byte is got soon has 32, and wherein, 20 (address [31:12]) is that label position (tag bits) and 12 (address [11:0]) are bits of offset (offset bits).The label position is stored in label respectively and gets soon, and discerns 2 of primary memory
20Which will be stored in the given address of getting soon in the fast line taking; 12 bits of offset point out that sign indicating number will be stored in 2
12Which position during byte is got soon.
Get controller soon and use bits of offset according to the framework of getting soon, for example, " directly reflection (directmap) " is a kind of form of getting soon.There is the coding of particular offset position to be stored in unique position in getting soon, for example, suppose the fast line taking of 32 bytes have address realm from 0000_0700 (sexadecimal) be stored in to 0000_071F (sexadecimal) get soon in offset address 700 to 71F, and suppose that the second fast line taking has address realm from 1234_5700 to 1234_571F.The above-mentioned second fast line taking can't be stored with the first fast line taking simultaneously, because these two fast line takings have identical offset address 700 to 71F.Yet because the random nature of coding compiling, the conflict of this class is easy to take place.
Because directly reflection can be accompanied by the problem of this class, develop the cache architecture that a kind of " set relations type ".For example, " two-way " set relations type get soon be with whole get soon be divided into two identical sizes get passage (cache ways) soon.Extra position is used for indicating and will be stored in two and gets which specific fast line taking of passage soon, and wherein above-mentioned extra bits is to be taken from position specific in the offset address.Algorithm can be used for compiling this extra bits and which fast line taking decision will be stored in, and perhaps, the label address can be used for relatively and detect above-mentioned fast line taking is to be stored in first or second to get passage soon.
Get soon and can be divided into several parts, for example, " four-way " set relations type has been got four soon and has been won the confidence soon, and eight have got eight soon to the set relations type and get passage soon.Can be stored in different getting soon in the passage simultaneously by the fast line taking that allows the same offset position, can increase and get the ratio of seeking soon.Directly reflection to get the probability of seeking soon be 65%, be rational numerical; And use four-way set relations type to get soon, and get the probability of seeking soon and can be increased to 90%, increase the acquisition speed of processor thereupon.Because the coded address is tended to identical bits of offset usually, it is reasonable using multichannel cache architecture.
The another kind of practice, get soon be designed to each fast line taking can be stored in get soon in Anywhere, the getting soon of this form is called gathers relationship type (fully set-associative) fully and gets soon, also or fully fechtable storer (content accessible memory) or CAM.CAM needs a large amount of comparator circuits (comparators) with correlation logic and finally can cause capturing slowly the time, and four-way is got only needs four or eight comparator circuits with eight soon to the set relations type, can provide preferable acquisition speed usually.
Get the placement algorithm of controller soon and extensively noted, unfortunately, there is restriction in the placement algorithm of industry standard, promptly is can provide preferable performance on average, but may be at every turn all provides optimum performance to the key work of system.Other work of processor processing in time may be not urgent, but part work may need to handle fast, similarly be " in real time " work, therefore, software program writes in the mode that urgent real-time working is interrupted other work usually, then, in case interrupt finishing, above-mentioned software program can be returned to operate as normal and continue to process.
Interrupt or real-time working may not can usually takes place, when in case when taking place, wish that but they can be performed apace.For instance, suppose that the interruption customary procedure produces ringing signal because of cell phone incoming call, though the several talent's generations of above-mentioned interruption possibility once, when taking place, because it is a real-time event, so necessary execution is soon enough.When phone comes, mobile phone may be carried out background frame, but the tinkle of bells interrupts acquiring a priority, want to carry out fast interrupt or the sign indicating number of other high priority must be loaded on get soon in and in addition " locking (lock) ", above-mentioned thus sign indicating number will can not be dropped.This method has been improved the customary procedure that interrupts, because this method can guarantee that the interruption customary procedure of wanting to capture will be sought and carry out apace in getting soon.General placement algorithm is not mature enough usually for the cognition of high priority sign indicating number, therefore, the software program expert must cognitive sign indicating number which part have higher right of priority compared to other parts, and then constantly above-mentioned part sign indicating number is locked in get soon in so that can be for use at any time.
Another kind is got locking soon and is used in the frequent work of using.Suppose that number of times that the software program deviser recognizes that certain specific sign indicating number section is performed is higher than other work far away, for optimization is got the ratio of seeking soon, during the software program deviser can select the sign indicating number that above-mentioned use is frequent to be locked in to get soon.Simultaneously, according to the analysis of coding and processor,, therefore may be placed in the nearest use classification in order to avoid be dropped owing to use frequent sign indicating number to be used again and again at short notice.Abandoning above-mentioned sign indicating number and the above-mentioned sign indicating number of autonomous memory acquisition at once will waste the time of processor, and therefore, it is useful locking above-mentioned sign indicating number.
Traditional processor is by locking the whole lock function computing of winning the confidence soon, though locking has improved the execution performance that interrupts with the frequent sign indicating number that uses, the performance of acquisition remainder code will descend.Each that suppose that the 4K four-way gets is soon got passage soon and is stored 1K, and the interruption customary procedure of 600 bytes is locked to and gets soon, there are 424 bytes that do not have to use to be wasted in the passage getting soon of above-mentioned locking, the software program deviser can lock other coding, will put into which coding but will be difficult to decision in above-mentioned remaining space.On the other hand, suppose to have the four-way of 64K byte to get soon, each gets passage soon is 16K, gets passage if equally lock 600 bytes soon in one of them, and the 15K byte of will having an appointment is wasted.Because recent trend tends to design bigger getting soon, it is inevitable also bigger that each gets passage soon, and the space of getting passage has soon been wasted in unnecessary locking.Therefore, in order to satisfy above-mentioned deficiency and inappropriate, it is necessary that being wasted in this industry of channel space got in the minimizing of trying one's best soon.
Summary of the invention
In view of this, the invention provides a kind of locking coding (for example data or instruction) System and method in getting soon, simultaneously, the feature that processor proposed by the invention can provide circuit designers to describe the locking coding, and can save and get the space soon.In an embodiment, processor proposed by the invention includes gets and gets soon controller soon, but the above-mentioned coding duplicate of getting soon in the temporary storage, and above-mentioned getting soon can be divided into a plurality of passages (cache way) of getting soon, and each gets passage soon can be divided into a plurality of channel parts (cache way portion) of getting soon again; The above-mentioned controller of getting soon utilizes first and second signals to control above-mentionedly to get soon, wherein, first signal is to point out which is won the confidence soon to win the confidence soon (partial cache way) for part, and secondary signal to be definitional part get soon in the passage which to get channel part soon be locked.
In addition, in another embodiment, the above-mentioned controller of getting is soon controlled the configuration of getting middle coding soon, include working storage with the storage compartment signal of winning the confidence soon, above-mentioned part win the confidence soon signal point out which win the confidence soon for the part win the confidence soon, wherein, partly getting passage soon is divided into a plurality of channel parts of getting soon again; The above-mentioned controller of getting soon also can comprise another working storage to store lock part signal (locked portionsignal), and wherein, each during signal instruction part in above-mentioned lock part is won the confidence is soon got channel part soon and is locking or not locking.
In another embodiment, the present invention discloses and a kind ofly gets soon, include several and get passage soon, each gets passage soon can be divided into a plurality of channel parts of getting soon, all are got in the passage at least one soon and get passage soon and can be designated as part and get passage soon, each gets channel part soon separately address, and part is got in the passage each soon and got channel part branch soon and indicated it is locking or not locking.
Moreover, in another embodiment, the present invention discloses a kind of locking and is encoded in method in getting soon, said method comprises to get soon in the passage from several specifies one to win the confidence soon, there is the passage of getting soon to be defined as locking than low address (lower address), have the passage of getting soon of higher address (higher address) then to be defined as not having locked, and appointed each part of getting passage soon can be indicated and is locked or do not have locked.
Description of drawings
Fig. 1 is the calcspar of the computer system of the embodiment of the invention.
Fig. 2 is the calcspar of the embodiment of the invention above-mentioned fast taking system in Fig. 2.
Fig. 3 is the embodiment of the invention above-mentioned calcspar of getting controller soon in Fig. 2.
Fig. 4 A and 4B illustrate the diagram that direct reflection is got soon.
Fig. 4 C is loaded on the icon of locked part working storage for locked part signal among Fig. 3.
Fig. 5 A and 5B illustrate the icon that four-way set relations type is got soon.
Fig. 5 C illustrates among Fig. 3 the part signal of winning the confidence soon to be loaded on win the confidence the soon icon of working storage of above-mentioned part.
Fig. 5 D illustrates the icon that locked part signal among Fig. 3 is loaded on locked part working storage.
Fig. 6 A and 6B illustrate eight icons of getting soon to the set relations type.
Fig. 6 C illustrates among Fig. 3 the part signal of winning the confidence soon to be loaded on win the confidence the soon icon of working storage of above-mentioned part.
Fig. 6 D is the icon that locked part signal is loaded on locked part working storage in the example key diagram 3.
Fig. 7 is the manner of execution process flow diagram of the present announcement of the embodiment of the invention.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
Embodiment:
As a rule, fast taking system can be analyzed according to its performance, captures the time by analyzing the total get the number percent sought and processor soon, and circuit designers can come optimization to get performance soon according to these information.The present invention discloses framework a kind of and that processor merges, and the optimization that above-mentioned framework can make circuit designers allow and get use soon is better, and the sign indicating number section that the locking of permission circuit designers may be used is to accelerate acquisition speed.The present invention proposes a kind of System and method for and the deviser can be locked get soon single part in the passage, and the direct whole way of getting passage soon of locking of case is got the space soon to optimization preferable elasticity is provided before replacing.The so-called space of getting soon of the present invention can comprise for instance, and program coding, data or both all are that so-called " sign indicating number " is to be used for showing getting any possible content soon.Among the present invention, partially or completely lock one get soon the part can be interpreted into the section data that is not dropped simply, above-mentioned locking there is no need to prevent to get soon the independent renewal of lock part.
Continue to increase owing to greatly get the demand of passage soon, the system and method that provides the low set relations type that uses smaller portions efficiently to get soon needs, and similarly is that four-way or eight is got soon to the set relations type.The system that the present invention proposes allows smaller portions that the low set relations type of circuit designers locking gets soon with the unnecessary space of getting soon that avoids waste.The present invention proposes to cut apart and gets the processor of passage to smaller portions soon, circuit designers can be locked lessly get the space soon and can not waste the remaining spaces of getting soon in a large number more accurately.Circuit designers can be decided in its sole discretion to be needed blocked high priority sign indicating number and uses frequent sign indicating number, and the more unessential space of getting soon can keep to these sign indicating numbers, load then and lock that these are encoding to reservation gets the space soon, thus, the remaining part of getting sooner can be used as normal fast fetch bit and puts.Therefore, can capture high priority coding and high frequency of utilization coding apace, can also getting soon of the general coding of optimization seek probability, thereby increase the processor bulk velocity.
Fig. 1 is the calcspar of embodiment of the invention computer system 10, wherein includes processor 12, primary memory 14 and I/O (I/O) device 16, is connected by internal bus 18 between each element, as shown in Figure 2.Processor 12 comprises fast taking system 20, and fast taking system 20 includes to be got controller 22 soon and get 24 soon.
Getting 24 soon is that first stratum 1 (L1) gets soon, or is called mainly and gets soon.For instance, it can include the acquisition system (SRAM) at random synchronously of 32K byte, gets the 24 regional duplicates that are used for temporarily storing the sign indicating number that processor 12 may re-use soon.Primary memory 14 comprises dynamic random acquisition storer (DRAM), and is cheap than SRAM usually, but needs the more acquisition time.Because autonomous memory 14 acquisition datas must pass through bus 18, and therefore limited speed, preferably uses the sign indicating number of getting soon in 24 in the clock of bus 18 as far as possible.
Get 24 soon and can include set relations type framework, perhaps in other words, it includes several and gets passage soon.Getting 24 soon can be direct reflection and gets soon, reflection do not get soon not as set relations type framework cut apart win the confidence soon, each of set relations type framework is got passage soon and is stored several fast line takings, and several coding projects are represented in the fast line taking of each bar, wherein each coding project 1 byte normally.In some embodiment, the fast line taking of each bar can be 32 bytes.According to announcement of the present invention, get soon 24 each to get passage soon be to be divided into several to get channel part soon, each gets channel part soon will have several fast line takings, each is got channel part soon and is designed to separately address, it can be alone be addressed respectively at other part, simultaneously, each is got channel part soon and can be designated as locking or non-locking respectively.
Get controller 22 soon and get 24 relevant operations soon in order to control.When processor 12 requires autonomous memory 14 acquisition datas or instruction, whether get address that controller 22 requires with the Address Confirmation of getting 24 fast line taking soon soon is present in and gets in 24 soon, if exist, then this acquisition is called " get soon and seek ", and data can be immediately from getting acquisition in 24 soon.If data are not being got in 24 soon, then this result is called " getting error soon ", and processor 12 necessarily requires the duplicate of autonomous memory 14 acquisition datas and storage data in getting soon in 24, for the possibility that uses above-mentioned data next time.When sign indicating number autonomous memory 14 is read, processor 12 needs to wait for the cycle of about 10 to 100 clocks.
For instance, it is primary memory 14 runnings that processor 12 can be designed to 32 bit address space, for getting soon of 4K byte arranged, preceding 20 (positions 31 to 12) are the label addresses, and be stored in label and get soon, can confirm that the coding of above-mentioned requirements is whether in getting soon by the label address that relatively requires.Back 12 (positions 11 to 0) be " bits of offset ", the position that above-mentioned coding was stored during " bits of offset " pointed out to get soon, and the bit address [4:0] in 12 of bits of offset is as line taking bits of offset soon, is associated with the fast line taking of same 32 bytes.The size of the fast line taking of each bar is the length decision by fast line taking bits of offset, for example, use bit address [4:0] in 12 the bits of offset as fast line taking bits of offset, the size of fast line taking is 25 (32) bytes, bit address [11:5] in the 12 biased displacements is to be defined as the label bits of offset, and is relevant with the fast line taking that identical label address is arranged.In directly reflection is got soon, unique position during the project of getting will be stored in based on 12 positions of second half section and get soon soon, therefore, during two fast line takings that identical skew arranged can't be stored in simultaneously and get soon.
Getting controller 22 soon uses and gets the sign indicating number that placement algorithm decides which position of getting soon in 24 newly to be received soon and replace.Simultaneously, get placement algorithm soon and determine which sign indicating number to be dropped from getting 24 soon, drop policy can comprise (round robin) technology of rotating, the most seldom use (least recently used) technology or other suitable technique.
Get soon the placement algorithm except carrying out, to get controller 22 soon and also stores " partly winning the confidence soon " signal, this signal is which to be pointed out all to get soon in the passage get passage soon and partly locked.Which blocked signal of winning the confidence soon was case be used for judging before this class signal was similar to, different parts are, disclosed part win the confidence soon signal can by the further information table of processor 12 lucid and lively win the confidence be locked fully, do not have locked fully or part locking, then be not fully locked or do not have lockedly fully do not have blocked the winning the confidence soon can be for the standard configuration utilization by part winning the confidence soon of winning the confidence soon that signal is indicated as being that part wins the confidence soon.
A four-way set relations type has been got soon and has been got passage 0 to 3 soon, and using a length is that 2 the part signal of winning the confidence soon defines the locking pattern and indicates the specific passage of getting soon.Numerical value is that a part of 00 signal representative (if the lock part is arranged) lock part of winning the confidence soon only can appear at the 0th and gets passage soon; Numerical value 01 represents the 0th to get passage soon and locked fully, and the 1st got passage soon to have the part part locked, and the 2nd and the 3rd gets passage soon and do not have locked and can use for standard configuration; Numerical value 10 represents the 0th and the 1st to get soon that passage is locked fully and the 2nd get passage soon and might have the part part locked, and the 3rd gets passage does not soon then have locked; Numerical value 11 represents the 0th to 2 to get passage soon and all locked fully, and the 3rd gets passage soon and may partly be locked.The part signal of winning the confidence soon is 3 to getting soon for one eight, and 16 then are 4 to the part of getting the soon signal of winning the confidence soon, by that analogy.
Get controller 22 soon and also store " lock part signal " simultaneously, the lock part signal indicates that the part of winning the confidence soon that the part locking is won the confidence soon is locking or can uses for standard configuration, and it is to lock fully, do not lock fully or the part locking that signal definition above-mentioned part in lock part is got passage soon.Circuit designers can set up any suitable symbol represent locked and do not have the locking part, the corresponding lock-out state of getting channel part soon of each representative of lock part signal, the above-mentioned part of " 0 " expression is locked, and " 1 " represents that then above-mentioned part does not have locked (or opening can be used for standard configuration).For instance, get soon for one and may each get passage soon and be divided into four and get channel part soon, the lock-out state of getting channel part soon is by the lock part signal definition that comprises four, for example, if want to lock specific the 1st, the 3rd and the 4th part of getting passage soon, then the lock part signal is 0100; There are eight lock part signals of winning the confidence soon of getting channel part soon then to have 8.Win the confidence soon signal and combining of lock part signal of the previous part of being carried can provide circuit designers more preceding case has better settling mode in the space utilization getting soon of locking, therefore, less part similarly is that the part of 1K or 2K byte is locked can be according to needs the time.
Via the design platform of processor 12, allow circuit designers to set up high priority required the getting soon of encoding by win the confidence soon signal and lock part signal of setting section.These signals can utilize various suitable methods to add and get controller 22 soon, in case load the high priority sign indicating number, win the confidence soon signal and lock part signal of part will for good and all be set, thus processor 12 do standard operation during, these signals can be maintained fixed.
Fig. 3 is for getting the calcspar of controller 22 among embodiment of the invention Fig. 2 soon, gets controller soon and includes control module 26, part win the confidence soon working storage 28 and lock part working storage 30.Get controller 22 soon and control the coding configuration of getting soon in 24, control module 26 receives the signal from circuit designers in processor 12 during the designs, and signal is pointed win the confidence soon and win the confidence part soon will be locked.Control module 26 is sent the part signal of winning the confidence soon will be written into the working storage 28 of winning the confidence soon, and the above-mentioned part signal of winning the confidence is soon specified and got in 24 one soon and win the confidence soon and win the confidence soon for part.Above-mentioned part is got passage soon and is divided into several parts of winning the confidence soon, the signal that the response circuit deviser is given again.Control module 26 is sent the lock part signal and is written into lock part working storage 30, and above-mentioned lock part signal indicates whether each gets channel part soon locked.
No matter above-mentioned whether the part of winning the confidence soon or win the confidence soon at sign indicating number place locked, and control module 26 is the also control acquisition of getting sign indicating number in the passage soon simultaneously.Control module 26 guarantees that also the sign indicating number that autonomous memory 14 receives can not replace locked sign indicating number and locked sign indicating number is dropped, and the sign indicating number that autonomous memory 14 receives only can be placed and get soon in 24 to there not being blocked part.Control module 26 comprises configuration codes and abandons old or do not need the placement algorithm of sign indicating number, and further the program of being designed so that can be loaded at least one with blocked sign indicating number and gets channel part soon.Control module 26 can be respectively according to being stored in part win the confidence the soon signal and be stored in the lock part signal of lock part working storage 30 of the part of working storage 28 of winning the confidence soon, make the sign indicating number of loading be locked at least one and get in the channel part soon.
Fig. 4 A is the synoptic diagram that direct reflection is got soon.In the present embodiment, be getting soon of a 64K byte.For example have the address offset scope from 0000 (sexadecimal) to FFFF (sexadecimal), get soon and can be divided into several parts, quantity is not limit, shown in Fig. 4 B.Above-mentioned getting soon is divided into 16 parts, and each part is the 4K byte, and four positions in the coded address are to be used for determining to be which specific part in 16 parts.Because directly reflection is got soon and do not got passage soon, there is no need the storage compartment signal of winning the confidence soon so in this example, get controller 22 soon.But the lock part signal of a sixteen bit is still and must be used for indicating which is locked in 16 parts, the part of " 0 " representative locking, and " 1 " representative does not have blocked part, illustrates as Fig. 4 C.If the lock part signal is 0011_1111_1111_1111, then first and second parts are blocked, and remaining 14 parts be do not have blocked.Before these two parts of locking, circuit designers can load the data of 8K byte or instruct to and want in the blocked part, and then this lock part signal of 16 can be loaded into lock part working storage 30 so that lock this two parts.
Fig. 5 A is a synoptic diagram that four-way set relations type is got soon.In the present embodiment, above-mentionedly get total total 64K byte soon, and these four have respectively winning the confidence soon of 16K byte that 14 address offset is all arranged, scope is from 0000 to 3FFF, and each gets passage soon can be divided into several parts.In Fig. 5 B diagram, each is got passage soon and is divided into 8 and gets channel part soon, and each part is the 2K byte.Get soon in the structure in this four-way, 0 in the coded address is used to refer to the skew of the 2K data address of the track address of winning the confidence soon separately to 10 position; 3 positions (address [13:11]) are used for distinguishing gets channel part (as getting soon shown in the channel part left of Fig. 5 B) soon; And the position of these two most significant digits (address [15:14]) indicates above-mentioned coding will be stored in four and get soon which gets passage soon in the passage.In the present embodiment, getting controller 22 soon, to store a length be that 2 part wins the confidence soon that to get some in the passage soon serve as partly to get passage soon to signal to indicate four, in addition, also storing one eight lock part signal is blocked to indicate eight which (if any) of getting soon in the channel part.
For example, with reference to figure 5C and Fig. 5 D diagram, as fruit part win the confidence soon signal be 01 and the lock part signal be 0101_1111, then get passage 0 soon and be locked fully with get soon passage 2 and 3 be do not have fully locked.In getting passage 1 soon, the 1st and the 3rd gets channel part 000 and 010 soon by 0 locking, and get soon in the passage 1 remaining six get soon channel part (001,011,100,101,110 and 111) be do not have locked.2 the part signal of winning the confidence soon is loaded on part and wins the confidence soon (Fig. 5 C) in the working storage 28, and 8 lock part signals are to be loaded lock part working storage 30 (Fig. 5 D).
Suppose that one gets the four-way set associative framework that includes the 32K byte soon, wherein, each is got passage soon and is divided into eight and gets channel part soon, and each is won the confidence soon is that to get channel part soon be the 1K byte for 8K byte and each.Only need 15 to define the address than low address, the skew that 10 (address [9:0]) definition 1K part is got passage soon; Ensuing 3 (address [12:10]) is each part of winning the confidence soon of winning the confidence soon of definition, and uppermost two positions (address [14:13]) is used for defining four to get passage soon.
Suppose that a four-way set relations type each in getting soon gets passage soon and be divided into four and get channel part soon.Get the passage all part and second the 3rd part of getting passage soon soon if want to lock first, the signal of then partly winning the confidence soon is 01, and four lock part signal is 1101.The another one example, if want to lock first the first and the 4th part of getting passage soon, then the part win the confidence soon signal be 00 and the lock part signal be 0110.
Fig. 6 A is one eight and gets synoptic diagram soon to the set relations type.Among this embodiment, the above-mentioned 64K byte altogether of getting soon, and also these eight address offsets of having won the confidence soon that the 8K byte is arranged are from 0000 to 1FFF, and each is got passage soon and is divided into several parts.As Fig. 6 B diagram, each is got passage soon and is divided into four and gets channel part soon, and each part is the 2K byte.Above-mentioned eight in cache architecture, the position of position 0 to 10 is used to refer to the skew of the 2K data address of the track address of winning the confidence soon separately; Channel part is got in 2 (address [12:11]) definition soon; And three positions in the most significant digit (address [15:13]) points out to encode and is stored in eight and gets in the passage which soon.Getting controller 22 soon, to store a length be that 3 the part signal of winning the confidence soon is that 4 lock part signal will lock four of passage of getting soon that choose with appointment and gets in the channel part which soon and get channel part soon to specify eight to get soon which serve as that part is got passage soon in the passage, also to store a length simultaneously.
With reference to figure 6C and Fig. 6 D, as fruit part win the confidence soon signal be 001 and the lock part signal be 1101, it is locked fully then getting passage 0 soon, get passage 2 to 7 soon and then be do not have fully locked.Win the confidence soon in 1, have only that to get channel part 10 soon locked, getting passage (00,01 and 11) part soon for remaining three does not then have locked.3 the part signal of winning the confidence soon is loaded on part and wins the confidence soon (Fig. 6 C) in the working storage 28, and 4 lock part signals are to be loaded lock part working storage 30 (Fig. 6 D).
The invention describes the example that four-way and eight is got soon to the set relations type, though in the present invention four-way and eight to being taken as preferred embodiment soon, be noted that get soon 24 can be divided into any suitable number according to the hope of circuit designers get passage soon.Simultaneously, to get winning the confidence soon of channel part soon be example to be divided into four or eight at this, though this also is preferred embodiment, still being noted that wins the confidence soon can be divided into any suitable number according to the hope of circuit designers get channel part soon.
The present invention has defined the method that is encoded in getting soon that locks simultaneously, including to get soon in the passage from several specifies one to get passage soon, wherein, ordering is all locked fully above-mentioned winning the confidence soon before winning the confidence soon, ordering after then do not have lockedly fully, the appointed passage of getting soon then can designated each part be locked or not have locked.The advantage of this method provides simple and efficient mode, and part less in getting soon by locking is to lower the waste of getting the space soon.
The process flow diagram of Fig. 7 method in getting soon for locking data of the present invention or sign indicating number.Shown in square 32, said method comprises to get soon in the passage from several specifies one to get passage soon, and in square 34, the address is defined as locking than low the winning the confidence soon of winning the confidence soon of appointment.In square 36, the address does not have locked than high then being defined as of passage of getting soon of appointment.Appointed get soon passage then can designated each part be locked or do not have locked, shown in square 38.
Based on the analysis of processor to the coding acquisition, circuit designers can select to lock in regular turn given sign indicating number in getting soon, to improve the usefulness of processor.According to analysis, circuit designers can utilize lock-in feature proposed by the invention to describe the sign indicating number that will lock, known and wanted blocked sign indicating number that the deviser can be loaded into above-mentioned sign indicating number available win the confidence the soon value of signal and lock part signal of channel part and importation of getting soon and get soon so that sign indicating number is locked in.Therefore, by lowering the space waste, the bigger remaining space of getting soon can make to get soon and seeks probability and improve, and simultaneously, is locked in by the coding with high priority and gets soon, and above-mentioned coding can be captured apace to grasp real-time or frequent use.
In embodiments of the invention, can also calculate the lost data length when taking place to get loss soon, then the length that is marked as non-locking part in the passage is got in more above-mentioned lost data and above-mentioned appointment soon.To get in the passage length of non-locking part soon than above-mentioned appointment less or identical when the length of lost data, loads above-mentioned lost data to above-mentioned appointment and get soon and be marked as nonlocking part in the passage.Get the length of non-locking part in the passage when the length of above-mentioned lost data soon greater than above-mentioned appointment, load above-mentioned lost data to the above-mentioned nonlocking passage of getting soon.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (10)
1. the processor of the fast taking system of a lockable code includes:
Get soon, be used for the duplicate of the sign indicating number of temporary primary memory, wherein, above-mentioned getting soon is to be divided into a plurality of passages of getting soon, above-mentioned each get passage soon and be divided into a plurality of channel parts of getting soon; And
Get controller soon, be used to control and above-mentionedly get soon, wherein, the above-mentioned controller of getting soon utilizes first signal to specify above-mentionedly a plurality ofly to get one in the passage soon and win the confidence soon and win the confidence soon for part, and to utilize secondary signal to specify soon the win the confidence part of which above-mentioned part in winning the confidence soon be blocked.
2. processor according to claim 1, wherein, the above-mentioned controller of getting soon comprises the working storage of partly winning the confidence soon to store above-mentioned first signal as the signal of partly winning the confidence soon, and the above-mentioned controller of getting soon comprises the lock part working storage to store above-mentioned secondary signal as the lock part signal.
A lockable code get controller soon, the configuration of sign indicating number in getting soon in order to control, above-mentioned getting soon is divided into a plurality of passages of getting soon, the above-mentioned controller of getting soon includes:
The part working storage of winning the confidence soon, in order to the storage compartment signal of winning the confidence soon, the above-mentioned part signal of winning the confidence soon is to specify above-mentioned getting soon a plurality ofly to get one in the passage soon and win the confidence soon and win the confidence soon as part, above-mentioned part is got passage soon and is divided into a plurality of channel parts of getting soon; And
The lock part working storage, in order to storing the lock part signal, whether above-mentioned lock part signal is that each that indicate that above-mentioned part gets passage is soon got channel part soon locked.
4. the controller of getting soon according to claim 3 comprises control module, in order to control above-mentioned get the configuration of above-mentioned sign indicating number in the passage soon and control those do not have the blocked channel part of getting soon.
5. the controller of getting soon according to claim 4, wherein, above-mentioned control module makes sign indicating number be loaded at least one channel part of getting soon, wherein, above-mentioned control module makes the sign indicating number of above-mentioned loading be locked at least one channel part of getting soon, and the above-mentioned channel part of getting soon is win the confidence soon signal and an above-mentioned lock part signal of corresponding above-mentioned part.
6. getting soon of a lockable code, it includes several wins the confidence soon, it is characterized in that:
Each gets passage soon is to be divided into a plurality of channel parts of getting soon, and above-mentioned several are got in the passage soon, and at least one passage of getting soon can be designated as part and gets passage soon;
Each gets channel part soon can be by addressing respectively; And
Above-mentioned part get passage soon each get soon channel part be marked as locked or nonlocking.
7. according to claim 6ly get soon, wherein, appointedly win the confidence soon compared to above-mentioned, have than winning the confidence soon of low address to be marked as locking, appointedly win the confidence soon compared to above-mentioned, there have winning the confidence soon of higher address then to be marked as to be nonlocking.
8. the method for lock code in the high-speed cache includes:
Specify one to get passage soon from a plurality of get soon in the passage, appointedly win the confidence soon compared to above-mentioned, have than winning the confidence soon of low address to be marked as locking, appointedly win the confidence soon compared to above-mentioned, there have winning the confidence soon of higher address then to be marked as to be nonlocking; And
Several parts of getting soon in the passage of indicating above-mentioned appointment are locking or nonlocking.
9. method according to claim 8 includes:
Be marked as when locking as the above-mentioned passage of getting soon, load sign indicating number to above-mentioned be defined as locking get passage soon;
Lock above-mentioned be marked as locking get passage soon;
When being marked as the part of locking, be written into sign indicating number as above-mentioned to the above-mentioned part that is marked as locking; And
Lock the above-mentioned part that is marked as locking.
10. method according to claim 8 includes:
Calculate the lost data length when taking place to get loss soon;
The length that is marked as non-locking part in the passage is got in more above-mentioned lost data and above-mentioned appointment soon; And
When the length of lost data gets soon than above-mentioned appointment that the length of non-locking part is less or identical in the passage, load above-mentioned lost data to above-mentioned appointment and get soon and be marked as nonlocking part in the passage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US80765306P | 2006-07-18 | 2006-07-18 | |
| US60/807,653 | 2006-07-18 | ||
| US11/470,304 | 2006-09-06 |
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| CN100495362C CN100495362C (en) | 2009-06-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105308580A (en) * | 2013-05-15 | 2016-02-03 | 亚马逊技术股份有限公司 | Allocating data based on hardware faults |
| WO2016097807A1 (en) * | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Cache replacement policy that considers memory access type |
| US9652400B2 (en) | 2014-12-14 | 2017-05-16 | Via Alliance Semiconductor Co., Ltd. | Fully associative cache memory budgeted by memory access type |
| US9811468B2 (en) | 2014-12-14 | 2017-11-07 | Via Alliance Semiconductor Co., Ltd. | Set associative cache memory with heterogeneous replacement policy |
| US9898411B2 (en) | 2014-12-14 | 2018-02-20 | Via Alliance Semiconductor Co., Ltd. | Cache memory budgeted by chunks based on memory access type |
| US9910785B2 (en) | 2014-12-14 | 2018-03-06 | Via Alliance Semiconductor Co., Ltd | Cache memory budgeted by ways based on memory access type |
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2007
- 2007-05-25 CN CNB2007101045052A patent/CN100495362C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105308580A (en) * | 2013-05-15 | 2016-02-03 | 亚马逊技术股份有限公司 | Allocating data based on hardware faults |
| CN105308580B (en) * | 2013-05-15 | 2019-08-13 | 亚马逊技术股份有限公司 | Data are distributed based on hardware fault |
| WO2016097807A1 (en) * | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Cache replacement policy that considers memory access type |
| US9652400B2 (en) | 2014-12-14 | 2017-05-16 | Via Alliance Semiconductor Co., Ltd. | Fully associative cache memory budgeted by memory access type |
| US9652398B2 (en) | 2014-12-14 | 2017-05-16 | Via Alliance Semiconductor Co., Ltd. | Cache replacement policy that considers memory access type |
| US9811468B2 (en) | 2014-12-14 | 2017-11-07 | Via Alliance Semiconductor Co., Ltd. | Set associative cache memory with heterogeneous replacement policy |
| US9898411B2 (en) | 2014-12-14 | 2018-02-20 | Via Alliance Semiconductor Co., Ltd. | Cache memory budgeted by chunks based on memory access type |
| US9910785B2 (en) | 2014-12-14 | 2018-03-06 | Via Alliance Semiconductor Co., Ltd | Cache memory budgeted by ways based on memory access type |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100495362C (en) | 2009-06-03 |
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