CN1531058A - Rear sectional method for preventing fuse semiconductor from damage of its side wall - Google Patents
Rear sectional method for preventing fuse semiconductor from damage of its side wall Download PDFInfo
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- CN1531058A CN1531058A CNA031191819A CN03119181A CN1531058A CN 1531058 A CN1531058 A CN 1531058A CN A031191819 A CNA031191819 A CN A031191819A CN 03119181 A CN03119181 A CN 03119181A CN 1531058 A CN1531058 A CN 1531058A
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- fuse
- sidewall
- damages
- semiconductor device
- dielectric layer
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Abstract
The present invention is a method for preventing the side wall of a fuse from damaging in the rear-stage process of the semiconductor device. The method comprises the steps after forming a fuse on a substrate: forming a spacing wall on a side wall of the fuse first, then forming a dielectric layer and a protecting layer on the substrate, and next patterning the protecting layer and the dielectric layer to form an opening of the fuse. The spacing wall provided on the side wall of the fuse can protect the fuse from damage of its side wall during the etching and washing processes for forming the fuse opening.
Description
Technical field
The present invention relates to a kind of semi-conductive technology, particularly the last part technology method of the semiconductor device that damages about a kind of sidewall that prevents fuse.
Background technology
In semiconductor device, particularly in large-scale storage component part, can utilize fuse (Fuse) to repair the defective (Defect) of device usually, to promote the qualification rate (Yield) of product.Typical repairing method, be when testing semiconductor memory devices, find the position (Bit) that breaks down at the row (Row) of memory or row (Column), then utilize laser that specific insurance silk thread fusing is blown, so that when choosing the position that this breaks down in the future, can see through decoding circuit and change to fix-up circuit automatically.
Known fuse technology; be that the fuse opening in fix-up circuit district and the welding pad opening of internal circuit region are opened simultaneously; its technology is to utilize the photoresist layer with fuse opening and welding pad opening pattern as the cover curtain; the protective layer by photoresist layer covered is removed not in etching; make internal circuit region form the welding pad opening that exposes soldering pad layer; afterwards, a part of etching of the dielectric layer that will insure on the silk thread again to be covered is removed, to form the fuse opening.
Above-mentioned known method is in the process of opening safety silk opening, the sidewall of fuse subjects to etching and destroys, and in the cleaning process after forming the fuse opening, because the degree of depth of welding pad opening is more shallow, and the degree of depth of fuse opening is darker, therefore, when after cleaning, being spin-dried for, staying cleaning fluid or the moisture among the fuse opening and be difficult for being spin-dried for.In case cleaning fluid or moisture rest on the surface and the sidewall of fuse, the phenomenon that then has corrosion takes place, even causes fuse to peel off and can't bring into play the problem of the effect of its repairing.
Summary of the invention
The last part technology method that the purpose of this invention is to provide a kind of semiconductor device, the destruction that suffers etching or cleaning in order to the sidewall that in the process of opening safety silk opening, prevents fuse.
The present invention proposes the last part technology method of the semiconductor device that a kind of sidewall that prevents fuse damages; the method is to form in substrate after the fuse; sidewall at fuse forms a clearance wall earlier; in substrate, form dielectric layer and protective layer again; then; again with protective layer and dielectric layer patternization, to form the fuse opening.
Owing to have clearance wall on its sidewall of fuse, therefore, in the technology of etching that forms the fuse opening and cleaning, clearance wall can be protected fuse, avoids its sidewall to be damaged.
The present invention proposes the last part technology method of the semiconductor device that sidewall that another kind prevents fuse damages again, the method is to form in substrate after fuse and the metal level, in substrate, form the ground floor dielectric layer earlier, and, expose the opening of fuse with formation first dielectric layer patternization.Then, form a clearance wall, and in substrate, form second layer dielectric layer and protective layer at the sidewall of fuse, afterwards, again with protective layer and second layer dielectric layer patternization, with formation welding pad opening and fuse opening.
According to the above, the present invention is before forming the fuse opening, and the sidewall at fuse forms clearance wall earlier.Because the material of clearance wall and the material of dielectric layer are inequality, therefore, in the process of opening safety silk opening, clearance wall can be protected fuse, makes the sidewall of fuse can't suffer etched destruction.And after cleaning be spin-dried for step the time, even cleaning fluid or moisture have residual phenomenon, because before forming the fuse opening, the sidewall of fuse has formed clearance wall, can't residual cleaning fluid or moisture on the sidewall of fuse, therefore, can avoid the phenomenon of the sidewall generation corrosion of fuse.
Description of drawings
The generalized section of the last part technology method of Figure 1A to Fig. 1 G has described the embodiment of the invention the semiconductor device that a kind of sidewall that prevents fuse damages.
Description of reference numerals
100: substrate
102: metal level
104: fuse
106,116: dielectric layer
108: photoresist layer
110,112: opening
114: the spacer material layer
114a: clearance wall
118: weld pad
120: protective layer
122: welding pad opening
124: the fuse opening
Embodiment
Please refer to Figure 1A, in substrate 100, form metal level 102 and fuse 104.Metal level 102 can be to form layer of aluminum metal level and one deck titanium nitride layer in substrate 100 in regular turn with the formation method of fuse 104, afterwards, defines it again, so that aluminum metal layer and titanium nitride layer patterning.Then, in substrate 100, form one dielectric layer 106, to cover the surface of metal level 102 and fuse 104.The material of dielectric layer 106 can be a silica, and the method for its formation can be high density plasma chemical vapor deposition method (HDP-CVD).
, please refer to Figure 1B, with dielectric layer 106 planarizations thereafter.The method of planarization can be chemical mechanical milling method (CMP).Then, on dielectric layer 106, form one deck photoresist layer 108.Photoresist layer 108 has an opening 110, and it is positioned at the top of fuse 104.
Then, please refer to Fig. 1 C, serves as the cover curtain with photoresist layer 108, and the dielectric layer 106 that opening 110 is exposed is removed in etching, to form an opening 112, makes the upper surface of fuse 104 and sidewall expose out.
Afterwards, please refer to Fig. 1 D, remove photoresist layer 108.Then, in substrate 100, form one deck spacer material layer 114 again.The material of spacer material layer 114 has different rate of etch with the dielectric layer of follow-up formation 116 materials, can be silicon nitride or silicon oxynitride, and the method for its formation can be plasma enhanced chemical vapor deposition method (PECVD).
, please refer to Fig. 1 E, spacer material layer 114 is carried out etch-back, form clearance wall 114a with sidewall at fuse 104 thereafter.Then, in substrate 100, form another layer dielectric layer 116.The material of this dielectric layer 116 can be a silica, and the method for its formation can be the plasma enhanced chemical vapor deposition method.
Afterwards, please refer to Fig. 1 F, with dielectric layer 116 planarizations.The method of its planarization can be a chemical mechanical milling method.Then, on dielectric layer 116, form weld pad 118 and protective layer 120.The material of weld pad 118 can be a copper.The formation method of protective layer 120 can be to form one deck silicon oxide layer earlier with chemical vapour deposition technique, forms one deck silicon nitride (SiN) layer again on silicon oxide layer.
Thereafter; please refer to Fig. 1 G; in substrate 100, form one deck photoresist layer (not shown); and serve as cover curtain with this photoresist layer; elder generation's etch protection layer 120 is to form a welding pad opening 122 and a fuse opening 124, then; the dielectric layer 116 that exposed of etching fuse opening 124 again is so that the surface exposure of fuse 104 comes out.Afterwards, again photoresist layer is removed.In the etching process of opening safety silk opening; selection is carried out etching for the etching solution that dielectric layer 116/ clearance wall 114a has high etching selectivity; clearance wall 114a is remained,, make its sidewall can not suffer etched destruction with protection fuse 104.
Described according to above embodiment, the present invention is before forming fuse opening 124, forms opening 112 earlier and make the upper surface of fuse 104 and sidewall expose out in dielectric layer 106.Because the thickness of dielectric layer 106 is not thick, the degree of depth of formed opening 112 is not dark, therefore, and in the cleaning process after forming opening 106, cleaning fluid among the opening 106 or moisture are very easy to be spin-dried for, and do not have the surface that rests on fuse 104 or the phenomenon of sidewall.After forming opening 112, the sidewall of fuse 104 forms clearance wall 114a immediately.In other words, the sidewall of fuse 104 is promptly covered by clearance wall 114a.Therefore; in the process of opening safety silk opening, utilize and carry out etching for the etching solution that has high etching selectivity between the dielectric layer 116/ clearance wall 114a, clearance wall 114a is remained; with protection fuse 104, make its sidewall can not suffer etched destruction.And after opening safety silk opening 124, after cleaning be spin-dried for step the time, even cleaning fluid or moisture have residual phenomenon, because the sidewall of fuse 104 has formed clearance wall 114a, and do not expose out, therefore, cleaning fluid or moisture can't remain in the sidewall of fuse 104 and the phenomenon of corroding.So the present invention can reach the purpose of avoiding the sidewall corrosion really at the sidewall formation clearance wall of fuse.
Though the present invention with preferred embodiment explanation as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with claim.
Claims (19)
1. the last part technology method of the semiconductor device that damages of a sidewall that prevents fuse is characterized in that this method comprises:
One substrate is provided, has formed a fuse in this substrate;
Sidewall in this fuse forms a clearance wall;
In this substrate, form a dielectric layer;
In this substrate, form a protective layer; And
This protective layer of patterning and this dielectric layer are to form a fuse opening.
2. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 1 damages is characterized in that the formation method of this clearance wall comprises:
In this substrate, form a spacer material layer; And
This spacer material layer of etch-back forms this clearance wall with the sidewall in this fuse.
3. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 1 damages is characterized in that the material of this clearance wall has different rate of etch with this dielectric layer material.
4. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 3 damages is characterized in that this clearance wall is formed with the plasma enhanced chemical vapor deposition method.
5. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 3 damages is characterized in that the material of this clearance wall comprises silicon nitride.
6. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 3 damages is characterized in that the material of this clearance wall comprises silicon oxynitride.
7. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 3 damages is characterized in that the material of this dielectric layer comprises the formed silica of plasma enhanced chemical vapor deposition method.
8. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 1 damages is characterized in that the formation method of this fuse comprises:
Formation one contains the metal level of aluminium in this substrate;
On this metal level, form the titanium nitride layer; And
Define this titanium nitride layer and this contains the metal level of aluminium.
9. the last part technology method of the semiconductor device that damages of a sidewall that prevents fuse is characterized in that this method comprises:
One substrate is provided, has formed a metal level and a fuse in this substrate;
In this substrate, form one first dielectric layer;
With this first dielectric layer flatening;
With this first dielectric layer patternization, to form an opening, this opening exposes the upper surface and the sidewall of this fuse;
Sidewall in this fuse forms a clearance wall;
In this substrate, form one second dielectric layer;
With this second dielectric layer flatening;
On this second dielectric layer, form a weld pad;
In this substrate, form a protective layer; And
This protective layer of etching, to form a welding pad opening and a fuse opening, this second dielectric layer of this fuse opening of etching below again is so that the upper surface of this fuse exposes out.
10. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 9 damages is characterized in that the formation method of this clearance wall comprises:
In this substrate, form a spacer material layer; And
This spacer material layer of etch-back forms this clearance wall with the sidewall in this fuse.
11. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 9 damages is characterized in that the material of this clearance wall has different rate of etch with this second dielectric layer material.
12. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 11 damages is characterized in that this clearance wall is formed with the plasma enhanced chemical vapor deposition method.
13. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 11 damages is characterized in that the material of this clearance wall comprises silicon nitride.
14. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 11 damages is characterized in that the material of this clearance wall comprises silicon oxynitride.
15. comprising with the plasma enhanced chemical vapor deposition method, the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 11 damages, the formation method that it is characterized in that this second dielectric layer form one silica layer.
16. comprising with the high density plasma chemical vapor deposition method, the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 9 damages, the formation method that it is characterized in that this first dielectric layer form one silica layer.
17. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 9 damages is characterized in that the method for the planarization of this first dielectric layer comprises chemical mechanical milling method.
18. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 9 damages is characterized in that the method for the planarization of this second dielectric layer comprises chemical mechanical milling method.
19. the last part technology method of the semiconductor device that the sidewall that prevents fuse as claimed in claim 9 damages is characterized in that the formation method of this fuse comprises:
Formation one contains the metal level of aluminium in this substrate;
On this metal level, form the titanium nitride layer; And
Define this titanium nitride layer and this contains the metal level of aluminium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031191819A CN1531058A (en) | 2003-03-13 | 2003-03-13 | Rear sectional method for preventing fuse semiconductor from damage of its side wall |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031191819A CN1531058A (en) | 2003-03-13 | 2003-03-13 | Rear sectional method for preventing fuse semiconductor from damage of its side wall |
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| Publication Number | Publication Date |
|---|---|
| CN1531058A true CN1531058A (en) | 2004-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA031191819A Pending CN1531058A (en) | 2003-03-13 | 2003-03-13 | Rear sectional method for preventing fuse semiconductor from damage of its side wall |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105376934A (en) * | 2014-09-02 | 2016-03-02 | 富葵精密组件(深圳)有限公司 | Circuit board and manufacturing method of the circuit board |
-
2003
- 2003-03-13 CN CNA031191819A patent/CN1531058A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105376934A (en) * | 2014-09-02 | 2016-03-02 | 富葵精密组件(深圳)有限公司 | Circuit board and manufacturing method of the circuit board |
| CN105376934B (en) * | 2014-09-02 | 2018-03-09 | 鹏鼎控股(深圳)股份有限公司 | The manufacture method of circuit board and circuit board |
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