CN1527381A - Manufacture method of CMOS film transistor module - Google Patents
Manufacture method of CMOS film transistor module Download PDFInfo
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- CN1527381A CN1527381A CNA031198228A CN03119822A CN1527381A CN 1527381 A CN1527381 A CN 1527381A CN A031198228 A CNA031198228 A CN A031198228A CN 03119822 A CN03119822 A CN 03119822A CN 1527381 A CN1527381 A CN 1527381A
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Abstract
The manufacture of CMOS film transistor module features that after manufacturing the pattern of the contact window, re-doping implantation of N type ion is performed to form the source/drain area of NMOS module. The manufacture process of the present invention reduces one photoetching step and mask use amount compared with available process.
Description
Technical field
The present invention relates to a kind of LCD (liquid crystal display, LCD) manufacturing process, and particularly relate to the manufacture method of a kind of CMOS thin film transistor (CMOS TFT) assembly.
Background technology
In present active LCD device, include one drive circuit (driver circuit), and more include a CMOS thin film transistor (CMOSTFT) assembly in this drive circuit.Yet; because N type metal oxide semiconductor thin-film transistor component can be because the effect of hot carrier in the CMOS TFT assembly; and the problem of grid leakage current is arranged when off status (Off state); so N type metal oxide semiconductor thin-film transistor component can design lightly mixed drain area (lightly doped region usually; LDD), be used for lowering grid leakage current.
Below utilize Figure 1A～1E, be used for illustrating the manufacture method of existing CMOS thin film transistor (CMOS TFT) assembly.
At first, see also Figure 1A, a substrate of glass 100 is provided, this substrate 100 has 110, one p type metal oxide semiconductor (PMOS) district 120, a n type metal oxide semiconductor (NMOS) district.Then, use one of one first photomask first patterning manufacturing process (patterning process I), form one first polysilicon layer 130 and one second polysilicon layer 135 in this substrate 100 of part, wherein this first polysilicon layer 130 is arranged in this nmos area 110, and this second polysilicon layer 135 is arranged in this PMOS district 120.
See also Figure 1B, use one of one second photomask second patterning manufacturing process (patterning ptocess II), form a photoresist layer 140 on this first polysilicon layer 130 of part or this second polysilicon layer 135, covering this second polysilicon layer 135 at this with this photoresist layer 140 is example.Then, carry out an ion and inject manufacturing process 150 (for example being the light dope manufacturing process of p type ion) in order to adjust starting voltage value (threshold voltage adjustment, Vt adjustment), symbol 131 is first polysilicon layer of expression through adjusting.
See also Fig. 1 C, remove after this photoresist layer 140, use one of one the 3rd photomask the 3rd patterning manufacturing process (patterning process III), form a photoresist layer 155 on this first polysilicon layer 131 of part, and cover this second polysilicon layer 135.Afterwards, the heavy doping ion of carrying out a n type ion is injected manufacturing process (n
+-ions doping) 160 and form n
+-polysilicon film 170 in this first polysilicon layer 131, this n
+-polysilicon film 170 is the source/drain region of NMOS assembly in order to be used as.
See also Fig. 1 D, remove after this photoresist layer 155, form a gate insulator 180 in this first polysilicon layer 131, this second polysilicon layer 135 and this substrate 100.Afterwards, form a metal level (not shown) on this gate insulator 180.Then, use one of one the 4th photomask the 4th patterning manufacturing process (patterning process IV), this metal level of patterning (not shown) and form a first grid 190 and a second grid 195, this first grid 190 is arranged in nmos area 110, and this second grid 195 is arranged in PMOS district 120.
Still seeing also Fig. 1 D, is mask with this first grid 190 with this second grid 195, and the light dope ion that carries out a n type ion injects manufacturing process (n
--ions doping) 200, form a n
--polysilicon film 210 is arranged in this n of nmos area 110 in this first polysilicon layer 131 of part and this second polysilicon layer 135 of part
--polysilicon film 210 in order to be used as be lightly mixed drain area (lightly doped drain, LDD).
Then, see also Fig. 1 E, use one of one the 5th photomask the 5th patterning manufacturing process (patterning process V), form a photoresist layer 220 and cover this nmos area 110.Then, the heavy doping ion of carrying out a p type ion is injected manufacturing process (p
+-ions doping) 230, form a p
+-polysilicon film 240 in the part this second polysilicon layer 135 in, this p
+-polysilicon film 240 is the source/drain region of PMOS assembly in order to be used as.
See also Fig. 1 E, remove this photoresist layer 220.So promptly form a NMOS assembly 250 in nmos area 110, and a PMOS assembly 255 is in PMOS district 120.
Then, see also Fig. 1 F, form after the passivation layer (passivation layer) 260, use one of one the 6th photomask the 6th patterning manufacturing process (patterning process VI), form a plurality of contact holes 270 and pass through this passivation layer 260 and expose the source/drain region 170 of NMOS assembly 250 and the source/drain region 240 of PMOS assembly 255 with gate insulator 180.At last, insert electric conducting material in these contact holes 270 and form a plurality of connectors (plugs) 280.
Therefore, above-mentioned existing manufacturing process must use six photomasks (i.e. six road photoetching corrosion manufacturing process) just can produce CMOS TFT assembly, thereby makes manufacturing cost quite high.
Summary of the invention
In view of this, task of the present invention is to provide the manufacture method of a kind of CMOS thin film transistor (CMOS TFT) assembly.
Task of the present invention is to provide a kind of needs to use the manufacture method of the CMOS TFT assembly of five photomasks (i.e. five road photoetching corrosion manufacturing process).
For finishing above-mentioned task, the invention provides a kind of manufacture method of CMOS thin film transistor assembly, comprise the following steps:
(a) provide a substrate of glass, this substrate has a n type metal oxide semiconductor (NMOS) district and a p type metal oxide semiconductor (PMOS) district, wherein this nmos area more comprises one first doped region, a light doping section and a first grid polar region, and this PMOS district more comprises one second doped region and a second grid district;
(b) use one of one first photomask first patterning manufacturing process (patterning process), form one first semiconductor island and one second semiconductor island in this substrate of part, wherein this first semiconductor island is arranged in this nmos area, and this second semiconductor island is arranged in this PMOS district;
(c) use one of one second photomask second patterning manufacturing process, and this first semiconductor island of part and this second semiconductor island are exposed;
(d) inject admixture in this first semiconductor island that exposes and this second semiconductor island, in order to adjust the starting voltage value;
(e) form a gate insulator in this first semiconductor island, this second semiconductor island and this substrate;
(f) form a conductive layer on this gate insulator;
(g) use one of one the 3rd photomask the 3rd patterning manufacturing process, remove this conductive layer of part and define a first grid and a second grid, wherein this first grid is positioned at this first grid polar region, and this second grid is positioned at this second grid district;
(h) be mask with these first, second grids, the light dope ion that carries out a n type ion injects manufacturing process, forms a lightly mixed drain area in this first semiconductor island at this light doping section of position;
(i) use one of one the 4th photomask the 4th patterning manufacturing process, expose this PMOS district;
(j) be mask with this second grid, carry out the heavy doping ion of a p type ion and inject manufacturing process, form second source/drain region in this second semiconductor island of position at this second doped region;
(k) form a passivation layer on this gate insulator and these first, second grids;
(l) use one of one the 5th photomask the 5th patterning manufacturing process, form one first contact hole, one second contact hole, one the 3rd contact hole and one the 4th contact hole and pass through this passivation layer and this gate insulator, wherein these first contact holes and second contact hole system is to should first doped region, and these grade in an imperial examination three contact holes and the 4th contact hole system are on second source/drain region;
(m) via these first, second and third and four contact holes, carry out the heavy doping ion of a n type ion and inject manufacturing process, form first source/drain region in this first semiconductor island at this first doped region of position, the heavy doping ion dosage of wherein aforementioned p type ion is greater than the heavy doping ion dosage of this n type ion; And
(n) insert electric conducting material in these contact holes, and form one first connector, one second connector, one the 3rd connector and one the 4th connector, wherein these first, second connector systems electrically connect this first source/drain region, and these second, third connector systems electrically connect this second source/drain region.
Description of drawings
For above-mentioned task of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Figure 1A～1F shows the manufacturing process profile of existing CMOS TFT; And
Fig. 2～10 show the manufacturing process profile of the present invention's CMOS TFT.
The reference numeral explanation
Existing part (Figure 1A～1F)
100～substrate; 110～nmos area; 120～PMOS district; 130～the first polysilicon layers; 131～through first polysilicon layer of adjustment; 135～the second polysilicon layers; 140,155,220～energy-sensitive dye layer (for example being the photoresist layer); 150～ion injects manufacturing process; The heavy doping ion of 160～n type ion is injected manufacturing process; 170～n
+-polysilicon film (source/drain region); 180～gate insulator; 190～first grid; 195～second grid; The light dope ion of 200～n type ion injects manufacturing process; 210～n
--polysilicon film (LDD district); The heavy doping ion of 230～p type ion is injected manufacturing process; 240～p
+-polysilicon film (source/drain region); 250～NMOS assembly; 255～PMOS assembly; 260～passivation layer; 270～contact hole; 280～connector.
This case part (Fig. 2～10)
200～substrate; 210～nmos area; 211～the first doped regions; 212～light doping section; 213～first grid polar region; 220～PMOS district; 221～the second doped regions; 222～second grid district; 240～the first semiconductor islands (for example being first polysilicon layer); 241～through first polysilicon layer of adjustment; 245～the second semiconductor islands (for example being second polysilicon layer); 310,610～energy-sensitive dye layer (for example being the photoresist layer); 320～ion injects manufacturing process; 410～gate insulator; 412～silica (SiO
x) layer; 414～silicon nitride (SiN
x) layer; 420～conductive layer; 510～first grid; 520～second grid; The light dope ion of 530～n type ion injects manufacturing process; 540～n
--polysilicon film (LDD district); The heavy doping ion of 710～p type ion is injected manufacturing process; 720～p
+-polysilicon film (source/drain region); 722～lighter p type ion doped region; 810～passivation layer; 822,824,826,828～contact hole; The heavy doping ion of 910～n type ion is injected manufacturing process; 920～n
+-polysilicon film (source/drain region); 1010,1020,1030,1040～connector.
Embodiment
See also Fig. 2～10, in order to explanation the present invention's the manufacturing process of CMOS thin film transistor (CMOS TFT) assembly.
At first, see also Fig. 2, providing for example is a dielectric base 200 of substrate of glass, this substrate 200 has 210 and one p type metal oxide semiconductor (PMOS) district 220, a n type metal oxide semiconductor (NMOS) district, wherein this nmos area 210 more comprises one first doped region 211, a light doping section 212 and a first grid polar region 213, and this PMOS district 220 more comprises one second doped region 221 and a second grid district 222.
See also Fig. 2, can form a resilient coating (buffer layer) 230 in this substrate 200, this resilient coating 230 for example is by a silicon nitride layer (SiN
x) 232 with one silica layer (SiO
x) 234 formations.Be simplicity of illustration, the 3rd～10 following figure will not draw this resilient coating 230.
See also Fig. 2, use one of one first photomask (reticle or photomask) first patterning manufacturing process (patterning process I) then, form for example is that one first semiconductor island 240 (following with 240 expressions of first polysilicon layer) and one second semiconductor island 245 (following with 245 expressions of second polysilicon layer) of silicon island (silicon island) or polysilicon layer (polysilicon layer) is in this substrate 200 of part, wherein this first polysilicon layer 240 is arranged in this nmos area 210, and this second polysilicon layer 245 is arranged in this PMOS district 220.
See also Fig. 3, use one of one second photomask second patterning manufacturing process (patterningprocess II), form an energy-sensitive dye layer 310 (energy sensitive layer, for example be the photoresist layer) on this first polysilicon layer 240 of part or this second polysilicon layer 245, covering this second polysilicon layer 245 at this with this photoresist layer 310 is example.Then, carry out an ion and inject manufacturing process 320 (for example being the light dope manufacturing process of p type ion) in order to adjust starting voltage value (thresholdvoltage adjustment, Vt adjustment), symbol 241 is first polysilicon layer of expression through adjusting.
See also Fig. 4, remove after this energy-sensitive dye layer 310, forming for example is silica (SiO
x) layer 412 and silicon nitride (SiN
x) gate insulators 410 that constitute of layer 414 are in this first polysilicon layer 241, this second polysilicon layer 245 and this substrate 200.Then, form a conductive layer 420 on this gate insulator 410, wherein this conductive layer 420 can be a metal level, for example is molybdenum, aluminium or copper alloy layer.
See also Fig. 5, use one of one the 3rd photomask the 3rd patterning manufacturing process (patterningprocess III), remove this conductive layer 420 of part and define a first grid 510 and a second grid 520, wherein this first grid 510 is arranged in this first grid polar region 213, and this second grid 520 is arranged in this second grid district 222.
Seeing also Fig. 5, is mask with these first, second grids 510,520, and the light dope ion that carries out a n type ion injects manufacturing process (n
--ions doping, implantation dosage are 1E11～1E14atom/cm approximately
2) 530, form a n
--polysilicon film 540 wherein is arranged in this n of light doping section 212 in this first polysilicon layer 241 of part and this second polysilicon layer 245 of part
--polysilicon film 540 be in order to be used as be the NMOS assembly lightly mixed drain area (lightly doped drain, LDD).
See also Fig. 6, use one of one the 4th photomask the 4th patterning manufacturing process (patterningprocess IV), form an energy-sensitive dye layer 610 (for example being the photoresist layer) and cover this nmos area 210.
Seeing also Fig. 7, is mask with this second grid 520 with this energy-sensitive dye layer 610, carries out the heavy doping ion of a p type ion and injects manufacturing process (p
+-ions doping, implantation dosage are 1E16～1E20atom/cm approximately
2) 710 and form a p
+-polysilicon film 720 is in this second polysilicon layer 245 of part, and the position is at this p of this second doped region 221
+-polysilicon film 720 is to be the source/drain region 720 of PMOS assembly in order to be used as.
See also Fig. 8, remove this energy-sensitive dye layer 610, form a passivation layer (passivationlayer) 810 then on this gate insulator 410 and these first, second grids 510,520.This passivation layer 810 for example is a silicon nitride (SiN
x) layer or silica (SiO
x) layer.
See also Fig. 8, use one of one the 5th photomask the 5th patterning manufacturing process (patterningprocess V), form one first contact hole 822, one second contact hole 824, one the 3rd contact hole 826 and one the 4th contact hole 828 and pass through this passivation layer 810 and this gate insulator 410, wherein first contact hole 822 and second contact hole 824 are to should first doped region 211, and the 3rd contact hole 826 and the 4th contact hole 828 are that the position is above source/drain region 720.What will pay special attention to here is that the 3rd contact hole 826 and the 4th contact hole 828 can not touch second grid 520.
See also Fig. 9,, carry out the heavy doping ion of a n type ion and inject manufacturing process (n via these first, second and third and four contact holes 822,824,826,828
+-ions doping, implantation dosage are 1E15～1E19atom/cm approximately
2) 910, and form a n
+-polysilicon film 920 is in this first polysilicon layer 241 of part, and the position is at this n of this first doped region 221
+-polysilicon film 920 is to be the source/drain region 920 of NMOS assembly in order to be used as.
Also have, what will pay special attention to here is that the ion dose of the heavy doping ion injection manufacturing process 710 of aforementioned p type ion must inject more than 10 times of ion dose of manufacturing process 910 greater than the heavy doping ion of this n type ion.So, though the p among Fig. 9
+Have lighter p type ion doped region 722 (can regard PLDD as, p-type lightly doped drain) in-polysilicon film 720, but can be to the PMOS assembly too much influence electrically arranged.
See also Figure 10, insert for example is that the electric conducting material of metal is in these contact holes 822,824,826,828, and form one first connector 1010, one second connector 1020, one the 3rd connector 1030 and one the 4th connector 1040, wherein these first, second connectors 1010,1020 are the source/drain region 920 that electrically connects the NMOS assembly, and these second, third connectors 1030,1040 are the source/drain region 720 that electrically connects the PMOS assembly.
Feature of the present invention and advantage
The invention is characterized in:
After carrying out the patterning manufacturing process of contact hole, carry out the heavy doping ion of N type ion again and inject manufacturing process, to form the source/drain region of NMOS assembly.According to the present invention, can reduce by one photoetching corrosion manufacturing process than existing, and can reduce the photomask use amount.
So,, make CMOS TFT assembly to form with five road photoetching corrosion manufacturing process via the present invention, thus can lack the photoetching corrosion manufacturing process one than prior art, and can reach the purpose that reduces manufacturing cost.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit scope of the present invention; those skilled in the art without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention should be looked the accompanying Claim person of defining and is as the criterion.
Claims (10)
1. the manufacture method of a CMOS thin film transistor (CMOS TFT) assembly comprises the following steps:
(a) provide a substrate, this substrate has a n type metal oxide semiconductor (NMOS) district and a p type metal oxide semiconductor (PMOS) district, wherein this nmos area more comprises one first doped region, a light doping section and a first grid polar region, and this PMOS district more comprises one second doped region and a second grid district;
(b) use one of one first photomask first patterning manufacturing process (patterning process), form one first semiconductor island and one second semiconductor island in this substrate of part, wherein this first semiconductor island is arranged in this nmos area, and this second semiconductor island is arranged in this PMOS district;
(c) use one of one second photomask second patterning manufacturing process, and this first semiconductor island of part and this second semiconductor island are exposed;
(d) inject admixture in this first semiconductor island that exposes and this second semiconductor island, in order to adjust the starting voltage value;
(e) form an insulating barrier in this first semiconductor island, this second semiconductor island and this substrate;
(f) form a conductive layer on this insulating barrier;
(g) use one of one the 3rd photomask the 3rd patterning manufacturing process, remove this conductive layer of part and define a first grid and a second grid, wherein this first grid is positioned at this first grid polar region, and this second grid is positioned at this second grid district;
(h) be mask with these first, second grids, the light dope ion that carries out a n type ion injects manufacturing process, forms a lightly mixed drain area in this first semiconductor island at this light doping section of position;
(i) use one of one the 4th photomask the 4th patterning manufacturing process, expose this PMOS district;
(j) be mask with this second grid, carry out the heavy doping ion of a p type ion and inject manufacturing process, form second source/drain region in this second semiconductor island of position at this second doped region;
(k) form a passivation layer on this insulating barrier and these first, second grids;
(l) use one of one the 5th photomask the 5th patterning manufacturing process, form one first contact hole, one second contact hole, one the 3rd contact hole and one the 4th contact hole and pass through this passivation layer and this insulating barrier, wherein these first contact holes and second contact hole system is to should first doped region, and these grade in an imperial examination three contact holes and the 4th contact hole system are on second source/drain region; And
(m) via these first, second and third and four contact holes, carry out the heavy doping ion of a n type ion and inject manufacturing process, form first source/drain region in this first semiconductor island at this first doped region of position, the heavy doping ion dosage of wherein aforementioned p type ion is greater than the heavy doping ion dosage of this n type ion.
2. the manufacture method of a CMOS thin film transistor (CMOS TFT) assembly comprises the following steps:
(a) provide a substrate, this substrate has a n type metal oxide semiconductor (NMOS) district and a p type metal oxide semiconductor (PMOS) district, wherein this nmos area more comprises one first doped region, a light doping section and a first grid polar region, and this PMOS district more comprises one second doped region and a second grid district;
(b) use one of one first photomask first patterning manufacturing process (patterning process), form one first semiconductor island and one second semiconductor island in this substrate of part, wherein this first semiconductor island is arranged in this nmos area, and this second semiconductor island is arranged in this PMOS district;
(c) use one of one second photomask second patterning manufacturing process, form one first energy-sensitive dye layer on this first semiconductor island of part and this second semiconductor island;
(d) be mask with this first energy-sensitive dye layer, inject admixture, in order to adjust the starting voltage value in this first semiconductor island of part and this second semiconductor island;
(e) remove this first energy-sensitive dye layer;
(f) form an insulating barrier in this first semiconductor island, this second semiconductor island and this substrate;
(g) form a conductive layer on this insulating barrier;
(h) use one of one the 3rd photomask the 3rd patterning manufacturing process, remove this conductive layer of part and define a first grid and a second grid, wherein this first grid is positioned at this first grid polar region, and this second grid is positioned at this second grid district;
(i) be mask with these first, second grids, the light dope ion that carries out a n type ion injects manufacturing process, forms a lightly mixed drain area in this first semiconductor island at this light doping section of position;
(j) use one of one the 4th photomask the 4th patterning manufacturing process, form one second energy-sensitive dye layer and cover this nmos area;
(k) be mask with this second grid, carry out the heavy doping ion of a p type ion and inject manufacturing process, form second source/drain region in this second semiconductor island of position at this second doped region;
(l) remove this second energy-sensitive dye layer;
(m) form a passivation layer on this insulating barrier and these first, second grids;
(n) use one of one the 5th photomask the 5th patterning manufacturing process, form one first contact hole, one second contact hole, one the 3rd contact hole and one the 4th contact hole and pass through this passivation layer and this insulating barrier, wherein these first contact holes and second contact hole system is to should first doped region, and these grade in an imperial examination three contact holes and the 4th contact hole system are on second source/drain region; And
(o) via these first, second and third and four contact holes, carry out the heavy doping ion of a n type ion and inject manufacturing process, form one first source/drain in this first semiconductor island at this first doped region of position, the heavy doping ion dosage of wherein aforementioned p type ion is greater than the heavy doping ion dosage of this n type ion.
3. the manufacture method of CMOS thin film transistor assembly as claimed in claim 2 more comprises the following steps:
(p) insert electric conducting material in these contact holes, and form one first connector, one second connector, one the 3rd connector and one the 4th connector, wherein these first, second connector systems electrically connect this first source/drain region, and these second, third connector systems electrically connect this second source/drain region.
4. the manufacture method of CMOS thin film transistor assembly as claimed in claim 2 more comprises forming a resilient coating in this substrate.
5. the manufacture method of CMOS thin film transistor assembly as claimed in claim 2, wherein this resilient coating comprises a silicon nitride (SiN
x) layer and silicon monoxide (SiO
x) layer.
6. the manufacture method of CMOS thin film transistor assembly as claimed in claim 2, wherein these first, second semiconductor islands comprise silicon.
7. the manufacture method of CMOS thin film transistor assembly as claimed in claim 2, wherein this insulating barrier comprises a silicon nitride (SiN
x) layer and silicon monoxide (SiO
x) layer.
8. the manufacture method of CMOS thin film transistor assembly as claimed in claim 2, wherein the heavy doping ion dosage of this p type ion is more than ten times of heavy doping ion dosage of this n type ion.
9. the manufacture method of CMOS thin film transistor assembly as claimed in claim 2, wherein this passivation layer comprises silicon nitride (SiN
x) or silica (SiO
x).
10. the manufacture method of CMOS thin film transistor assembly as claimed in claim 2, wherein these first, second energy-sensitive series of strata photoresist layers.
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|---|---|---|---|
| CN 03119822 CN1230891C (en) | 2003-03-04 | 2003-03-04 | Manufacture method of CMOS film transistor module |
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|---|---|---|---|
| CN 03119822 CN1230891C (en) | 2003-03-04 | 2003-03-04 | Manufacture method of CMOS film transistor module |
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| CN1230891C CN1230891C (en) | 2005-12-07 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101730939B (en) * | 2007-04-30 | 2012-09-26 | 格罗方德半导体公司 | A technique for enhancing transistor performance by transistor specific contact design |
| CN108666272A (en) * | 2017-03-29 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| WO2021088912A1 (en) * | 2019-11-06 | 2021-05-14 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method therefor, array substrate and preparation method therefor, and display panel |
-
2003
- 2003-03-04 CN CN 03119822 patent/CN1230891C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101730939B (en) * | 2007-04-30 | 2012-09-26 | 格罗方德半导体公司 | A technique for enhancing transistor performance by transistor specific contact design |
| CN108666272A (en) * | 2017-03-29 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| WO2021088912A1 (en) * | 2019-11-06 | 2021-05-14 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method therefor, array substrate and preparation method therefor, and display panel |
| US11699761B2 (en) | 2019-11-06 | 2023-07-11 | Beijing Boe Technology Development Co., Ltd. | Thin film transistor and fabrication method thereof, array substrate and fabrication method thereof, and display panel |
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| Publication number | Publication date |
|---|---|
| CN1230891C (en) | 2005-12-07 |
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