CN1525336A - Storage array apparatus capable of shortening data access time and data access method thereof - Google Patents
Storage array apparatus capable of shortening data access time and data access method thereof Download PDFInfo
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- CN1525336A CN1525336A CNA031052363A CN03105236A CN1525336A CN 1525336 A CN1525336 A CN 1525336A CN A031052363 A CNA031052363 A CN A031052363A CN 03105236 A CN03105236 A CN 03105236A CN 1525336 A CN1525336 A CN 1525336A
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Abstract
The invention is a flash memory array device which can shorten data access time and data access method, mainly attaching a register management device and plural data registers between microcontroller and at least a flash memory array, partitioning the data to be stored by a certain unit bit number into plural data blocks, transmitting the data blocks in sequence by host machine to temporarily store into the corresponding data registers, transferring a data block from the register to the flash memory array, here transferring next data block into another data register in the control of line arrangement of microcontroller and register management device to prepare transferring into the flash memory array, thus repeating transfer lines and transmitting each data block, so as to effectively reduce the idle state of host computer and able to achieve the purpose of shortening data access time.
Description
Technical field
The invention relates to that a kind of memory array devices refers to a kind of flash memory array device and data access method thereof that shortens the data access time especially, not only can effectively reduce the idle state of host waits, also can reach the purpose that shortens the data access time.
Background technology
General flash memory (Flash Memory) because have that volume is less, power consumption is low, impact resistance, and nonvolatile advantage, so generally be used in the products such as portable product, person-to-person communication product or laptop computer.
And the flash memory array device of generally commonly using, as shown in Figure 1, it is mainly combined by an interface controllor 13, microcontroller 15, data working storage 17, data port,input-output 18 and flash memory array 19, wherein this interface controllor 13 by main frame bus-bar 11 and with a main frame 10 lines.When the data desire stores, main frame 10 will be notified microcontroller 15, and microcontroller 15 will be desired the access data and be divided into a plurality of data blocks according to unit bit number (as 512Bytes), the all first unloading of each data blocks sees through data port,input-output 18 by data working storage 17 again and is stored in the flash memory array 19 in data working storage 17.Otherwise, when desiring to read, then return to get final product according to above-mentioned step path inverted sequence as if data.
In the above-mentioned flash memory array device of commonly using, because its product performance, when the access data when data working storage 17 and 19 of flash memory arrays transmit, its speed is relatively slow, the more time must be spent, and design because of single data working storage and single flash memory array, therefore main frame 10 will be required wait and present idle state, must wait data working storage 17 and after the data of 19 of flash memory arrays finishes transmission, carry out the data transmission work of 17 of main frame 10 and data working storages again, so so will significantly prolong the access speed and the time of data, to the imformation age of pursuing fast processing be a big drawback.
Therefore, how to design a kind of memory array devices and data access method, can reduce the idle situation of wait of main frame and the access time of effective reduction data, be not to use for a long time the person eagerly to look forward to always, and the inventor is based on engaging in the relevant research that produces product of storer, exploitation, and the practical experience of selling for many years, poor its people's professional knowledge, through research and design, special topic discussion in many ways, work out a kind of memory array devices and data access method thereof that shortens the data access time finally.
Summary of the invention
Fundamental purpose of the present invention, be to provide a kind of memory array devices and data access method thereof that shortens the data access time, utilize a plurality of data working storages to desire the data that reads or store with segmentation access main frame, and at the data working storage and in the processing time of memory array devices data transmission cost than length, carry out the data blocks transmission work between next main frame and data working storage simultaneously, so can effectively reduce the idle stand-by period of main frame.Secondary objective of the present invention, be to provide a kind of memory array devices and data access method thereof that shortens the data access time, because being forced to the idle situation of waiting for, significantly reduces by main frame, so can effectively promote DATA PROCESSING speed and reduction Data Processing time.
A kind of memory array devices that shortens the data access time, it is mainly constructed is to include: an interface controllor, the one end can connect a main frame by the main frame bus-bar, its other end then line in a microcontroller; A plurality of data working storages can be in order to the temporary data blocks of desiring access; One working storage management devices, its inside are provided with a bus-bar switch at least, and an end line of this bus-bar switch is in this main frame bus-bar, and its other end then is controlled by this microcontroller and switches one of them line that determines with the data working storage; At least one data port,input-output, one end line be in each data working storage, its other end then line at least one memory array that stores data.
A kind of use can be shortened the data access method of the memory array devices of data access time, and its key step that stores data is to include:
The bus-bar switch of a, microprocessor controls working storage manager switches to first place on line with circuit;
B, first data blocks is stored in first working storage;
C, first data blocks is seen through the data port,input-output by first working storage move in the memory array and store, with time bus-bar switch circuit is switched to second place on line, and begin second data blocks is stored in second working storage;
Whether d, detecting and the data in first working storage waited for have been finished and have been deposited in the memory array;
E, second data blocks is seen through the data port,input-output by second working storage move in the memory array and store, with time bus-bar switch circuit is switched to first place on line, and begin next first data blocks is stored in first working storage;
Whether f, detecting and the data in second working storage waited for have been finished and have been deposited in the memory array;
G, the repeated execution of steps that continues c to step f until all data finished be stored in the memory array till.
Thus, the present invention not only can effectively reduce the idle state of host waits, also can reach the purpose that shortens the data access time.
Description of drawings
Fig. 1: be the structure block schematic diagram of commonly using the flash memory array device;
Fig. 2: the preferred embodiment structure block schematic diagram that is flash memory array device of the present invention;
Fig. 3: be the schematic flow sheet that stores data of embodiment as shown in Figure 2;
Fig. 4: be each flow process sequential synoptic diagram of embodiment as shown in Figure 2;
Fig. 5: be as shown in Figure 2 embodiment read the data process synoptic diagram;
Fig. 6: the structure block schematic diagram that is further embodiment of this invention;
Fig. 7: be each flow process sequential synoptic diagram of embodiment as shown in Figure 6.
The figure number explanation:
10 main frames, 11 main frame bus-bars
13 interface controllors, 15 microcontrollers
17 data working storages, 18 data port,input-outputs
19 flash memory arrays
20 main frames, 21 main frame bus-bars
23 interface controllors, 25 microcontrollers
271 first data working storages
272 second data working storages
273 the 3rd data working storages
281 first data port,input-outputs
282 second data port,input-outputs
291 first flash memory arrays
292 second flash memory arrays
30 working storage management devices
31 bus-bar switchs
33 switch controllers
35 first port,input-output switchs
37 second port,input-output switchs
Embodiment
At first, seeing also Fig. 2, is the preferred embodiment structure block schematic diagram for flash memory array device of the present invention; As shown in the figure, it is to include an interface controllor 23, a microcontroller 25, a working storage management devices 30, the first data working storage 271, the second data working storage 272, the first data port,input-output 281, the second data port,input-output 282, and first flash memory array 291, second flash memory array 292 that the present invention mainly constructs, wherein an end of interface controllor can connect a main frame 20 by main frame bus-bar 21, its other end then line in this microcontroller 25; And be provided with a bus-bar switch 31 in the working storage management devices 30 at least, one end line in this main frame bus-bar 21 in order to as and main frame 20 lines, the other end of bus-bar switch 31 then be controlled by this microcontroller 25 and switch decision and data working storage 271,272 one of them carry out line work; 281,282 of data port,input-outputs can be distinguished line in each data working storage 271,272, its other end then line in the corresponding memory array that stores data 291,292.
Please consult Fig. 2 and Fig. 3 again, when the data desire stored data to flash memory array 291,292 from main frame 20 ends, its storing step flow process was as follows:
Step 301, main frame 20 see through main frame bus-bar 21, interface controllor 23 and notice microcontroller 25 is desired to store data;
Step 302, the bus-bar switch 31 in the microcontroller 25 control working storage management devices 30 switches to connection line in first circuit 3171 that is connected with the first data working storage 271;
The data that step 303, microcontroller 25 store desire is with logic array block (LAB according to certain unit bit number as the present invention; 512Bytes) be unit, cut apart pluralize data blocks of whole data, and be temporary in the first data working storage 27 first data blocks (belonging to N data blocks series) (certain, the capacity of all data working storages also requires to be not less than 512Bytes), and will carry out step 304 and step 314 simultaneously after finishing this temporary step;
Step 304, first data blocks (N data blocks) be controlled by microcontroller 25 and via the first data port,input-output 281 from the first data working storage 271 and first flash memory array 291 is gone in unloading; Because the flash memory characteristic, in step 304 the employed time longer, so at one time, microcontroller 25 will promote step 314 simultaneously;
Step 314, bus-bar switch 31 switches to the main frame 20 and the second data working storage with circuit
Does step 305 detect and waits for whether the data in first working storage 271 has finished the work that deposits first memory array 291 in? if finish unloading work, then continue and carry out step 306 and step 316 simultaneously;
Step 306 because the flash memory characteristic makes so, so the time 272 morning of the second data working storage
Finished the temporary work of second data blocks (N+1 data blocks), moved to storage in the second memory array 292 so second data blocks is seen through the second data port,input-output 282 by second working storage 272;
Step 316, when carrying out with step 306, bus-bar switch 31 switches to first circuit, 3171 positions with circuit, and begins next first data blocks (N data blocks) is stored in first working storage 271; And
Step 307 detects and waits for whether temporary data in second working storage 272 have been finished deposits in the second memory array 292; And continue and heavily cover execution in step 304 to step 307, until all data finished be stored in the memory array till.
Moreover, see also Fig. 4, be each flow process sequential chart for this embodiment of the present invention; As shown in the figure,
It is walked crosswise is to be unit with each data working storage, and file then is to represent respectively to handle the period:
In first period, main frame 20 inputs first data blocks to the first data working storage 271, with
Symbol H-1B represents; This moment second data working storage 272 and attonity;
In second period, first data blocks is stored to first flash memory array 291 by the first data working storage 271, and 1B-1M represents with symbol; At this moment, in main frame 20 inputs second data blocks to the second data working storage 272, H-2B represents with symbol;
In the 3rd period, second data blocks is stored to second flash memory array 292 by the second data working storage 272, and 2B-2M represents with symbol; At this moment, main frame 20 is imported in next first data blocks to the first data working storage 271 again, and H-1B represents with symbol;
In the 4th period period, first data blocks is stored to first flash memory array 291 by the first data working storage 271, and 1B-1M represents with symbol; At this moment, in main frame 20 inputs second data blocks to the second data working storage 272, H-2B represents with symbol; So the action of the 4th period is identical with the action of second period, is all the replacement of heavily covering and moves till all data storage are finished so continue.
Stop standby time by can find out obviously in the sequential chart of Fig. 4 that main frame of the present invention there is no in day part, so the speed of data storage can effectively be promoted and save time.
Again, please consulting Fig. 5 again, is to be the data action flow chart that reads of the present invention:
Step 502 moves to storage in first working storage 271 with first data blocks by first memory array 291;
Step 513 in same period of step 503, moves to second data blocks in second working storage 272 by second memory array 292 and to store, and continues and carry out step 505;
Step 504 sees through first circuit 3171 with first data blocks by first working storage 271 and moves in the main frame 20 and read data;
Step 505 detects and waits for whether second data blocks has been finished is stored in second working storage 272;
Step 507 sees through second circuit 3172 with second data blocks by second working storage 272 and moves in the main frame 20 and read data;
Step 517 in same time of step 507, moves in first working storage 271 with next first data blocks by first memory array 291 and stores;
Step 508 detects and waits for whether next first data blocks has finished the action that is stored in first working storage 271; Afterwards, continue and heavily cover execution in step 503 to step 508, until all data finished read by main frame till.
Moreover, please consult Fig. 6 again, be the structure block schematic diagram of another embodiment of the present invention; As shown in the figure, though be to be example explanation in the above-described embodiments, do not represent data working storage of the present invention to be restricted or necessary identical with the quantity of flash memory array with 271,272 and two flash memory arrays 291,292 of two data working storages.In this embodiment, just designed the situation that three flash memory arrays 271,272,273 correspond to two data port,input-outputs 281,282 and two flash memory arrays 291,292.And temporarily be stored in each data working storage 271 in order to allow transmit by main frame 20,272, data blocks in 273 order is to some extent followed, so in working storage management devices 30, also be provided with the first port,input-output switch 35 and the second port,input-output switch 37, each port,input-output switch 35,37 end difference line is in its corresponding data port,input-output 281,282, its other end is then distinguished line in each data working storage 271,272,273, the switch controller 33 that is controlled by a line microcontroller 25, all switchs 31 in working storage management devices 30,35,37 all can arrange the transmission line of data blocks in regular turn.
At last, seeing also Fig. 7, is each the flow process sequential synoptic diagram that is had in the embodiment shown in fig. 6 for the present invention, equally its to walk crosswise be to be unit with each data working storage, file then is to represent respectively to handle the period:
In first period, main frame 20 inputs first data blocks to the first data working storage 271, H → 1B represents with symbol; This moment the second data working storage 272 and the 3rd data working storage 273 and attonity;
In second period, first data blocks is stored to first flash memory array 291 by the first data working storage 271, and 1B → 1M represents with symbol; At this moment, in main frame 20 inputs second data blocks to the second data working storage 272, H → 2B represents with symbol, and the 3rd data working storage 273 still is an attonity;
In the 3rd period, second data blocks is stored to second flash memory array 292 by the second data working storage 272, and 2B → 2M represents with symbol; At this moment, in main frame 20 inputs the 3rd data blocks to the three data working storages 273, H → 3B represents with symbol; The first data working storage 271 is the bye attonity then, but can utilize this period to write the record time as the data of first flash memory;
In the 4th period, the 3rd data blocks is stored to first flash memory array 291 by the 3rd data working storage 273, and 3B → 1M represents with symbol; At this moment, in next first data blocks to the first data working storage 271 of main frame 20 inputs, H → 1B represents with symbol: the second data working storage 271 is the bye attonity then, but can utilize this period to write the record time as the data of second flash memory;
In the 5th period, next first data blocks is stored to second flash memory array 292 by the first data working storage 271, and 1B → 2M represents with symbol; At this moment, in next second data blocks to the second data working storage 272 of main frame 20 inputs, H → 2B represents with symbol; The 3rd data working storage 273 is the bye attonity then, but can utilize this period to write the record time as the data of first flash memory, and for main frame and each data working storage, this period is identical with first period;
In the 6th period, the action of its each data working storage is identical with the 3rd period, thus continue be all the replacement action heavily covered until all data read finish till.
Though idle motionless in turn by also finding out obviously in the sequential chart of Fig. 7 that each data working storage has, main frame does not have the standby time of stopping, so integral body is still had the speed and the time saving purpose of effective lifting data storage.
In sum, memory array devices of the present invention is a kind of flash memory array device that shortens the data access time, and the access method of data, not only can effectively reduce the idle state of host waits, also can reach the purpose that shortens the data access time.
Claims (7)
1, a kind of memory array devices that shortens the data access time, it is mainly constructed is to include:
One interface controllor, the one end can connect a main frame by the main frame bus-bar, its other end then line in a microcontroller;
A plurality of data working storages can be in order to the temporary data blocks of desiring access;
One working storage management devices, its inside are provided with a bus-bar switch at least, and an end line of this bus-bar switch is in this main frame bus-bar, and its other end then is controlled by this microcontroller and switches one of them line that determines with the data working storage;
At least one data port,input-output, one end line be in each data working storage, its other end then line at least one memory array that stores data.
2, memory array devices according to claim 1, it is characterized in that: still can include in this working storage management devices and at least onely be controlled by microcontroller and determine to switch the port,input-output switch of line with one of them of this data working storage, its other end then line in each data port,input-output.
3, memory array devices according to claim 2, it is characterized in that: still can include a switch controller in this working storage management devices, one end line is in this microcontroller, and the one end is then distinguished line in this bus-bar switch and port,input-output switch.
4, memory array devices according to claim 1 is characterized in that: the quantity that is provided with of this data working storage is to be not less than the memory array number of columns.
5, a kind of data access method that uses according to the described memory array devices of claim 1, its key step that stores data is to include:
The bus-bar switch of a, microprocessor controls working storage manager switches to first place on line with circuit;
B, first data blocks is stored in first working storage;
C, first data blocks is seen through the data port,input-output by first working storage move in the memory array and store, with time bus-bar switch circuit is switched to second place on line, and begin second data blocks is stored in second working storage;
Whether d, detecting and the data in first working storage waited for have been finished and have been deposited in the memory array;
E, second data blocks is seen through the data port,input-output by second working storage move in the memory array and store, with time bus-bar switch circuit is switched to first place on line, and begin next first data blocks is stored in first working storage;
Whether f, detecting and the data in second working storage waited for have been finished and have been deposited in the memory array;
G, the repeated execution of steps that continues c to step f until all data finished be stored in the memory array till.
6, data access method according to claim 5, wherein first data blocks is to be stored in the first memory array, second data blocks then is stored in the second memory array.
7, a kind of data access method that uses according to the described memory array devices of claim 1, its step that reads data is to include:
A, first data blocks moved in first working storage by memory array store;
The bus-bar switch of b, microprocessor controls working storage manager switches to first place on line with circuit, with the time second data blocks is moved in second working storage by memory array to store;
C, first data blocks is seen through first circuit by first working storage move in the main frame and read;
D, detecting also wait for that second data blocks is stored in second working storage;
The bus-bar switch of e, microprocessor controls working storage manager switches to second place on line with circuit;
F, second data blocks is seen through second circuit by second working storage move in the main frame and read, with the time next first data blocks is moved in first working storage by memory array and store;
G, detecting also wait for that next first data blocks is stored in first working storage;
H, the repeated execution of steps that continues b be to step g, until all data finished read by main frame till.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA031052363A CN1525336A (en) | 2003-02-25 | 2003-02-25 | Storage array apparatus capable of shortening data access time and data access method thereof |
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| CNA031052363A CN1525336A (en) | 2003-02-25 | 2003-02-25 | Storage array apparatus capable of shortening data access time and data access method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102457725A (en) * | 2010-10-18 | 2012-05-16 | 曜鹏科技股份有限公司 | Temporary storage device and method for image coding data |
| US8983276B2 (en) | 2010-09-09 | 2015-03-17 | Alpha Imaging Technology Corp. | Apparatus and method for temporary storage of image-encoding data |
-
2003
- 2003-02-25 CN CNA031052363A patent/CN1525336A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8983276B2 (en) | 2010-09-09 | 2015-03-17 | Alpha Imaging Technology Corp. | Apparatus and method for temporary storage of image-encoding data |
| CN102457725A (en) * | 2010-10-18 | 2012-05-16 | 曜鹏科技股份有限公司 | Temporary storage device and method for image coding data |
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