CN1521828A - Process for forming double mosaic structure - Google Patents
Process for forming double mosaic structure Download PDFInfo
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- CN1521828A CN1521828A CNA031026575A CN03102657A CN1521828A CN 1521828 A CN1521828 A CN 1521828A CN A031026575 A CNA031026575 A CN A031026575A CN 03102657 A CN03102657 A CN 03102657A CN 1521828 A CN1521828 A CN 1521828A
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- damascene structure
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Abstract
A method for forming double lineage structure comprises the steps of, first forming a substrate having a conductor layer, later forming a low dielectric layer on the substrate, then forming an opening in the dielectric layer which includes a groove and a hole, wherein the bottom of the hole is the exposed conductor layer, later, proceeding a plasma process of NO2 or inactive gas to the dielectric layer surface in the opening, then filling conductor material into the opening so as to form a double lineage structure, thus improving the quality for the double mosaic process and increasing the adhesion between the dielectric layer and the conductor material.
Description
Technical field
The present invention is about the double-insert process in the semiconductor technology, and particularly relevant for a kind of lifting conductor (conductor) and the low dielectric method for tack (adhesion) between the number materials (low-k dielectric).
Background technology
In recent years, development along with semiconductor integrated circuit (IC) manufacturing technology, the quantity of contained assembly constantly increases in the chip, the size of assembly is also constantly dwindled because of the lifting of integration, so double-insert process (dualdam scene process) has become the main flow of plain conductor connecting technology now.For instance, deposit an insulating barrier earlier, pass through then after this insulating barrier of planarization and patterning, form the opening that groove (trench) and hole (viahole) are formed, and then metal material inserted in groove and the hole, and form a lead (conductive wire) coupling one connector (plug), and then carry out a cmp (chemicalmechanical polishing, CMP) planarization processing procedure, in order to the surface of smooth (planarize) assembly, thereby obtain a dual-damascene structure.Because dual-damascene structure can be avoided the restriction that overlaps error (overlay error) and solve known metal procedure, so double-insert process just is widely used in the manufacture of semiconductor and the lifting subassembly reliability.
Below utilize Figure 1A～1D that known double-insert process profile is described.
At first, see also Figure 1A, a substrate 100 is provided, this substrate 100 has a metal level 102.Then, utilize chemical vapour deposition technique (CVD), form an etching stopping layer 104 of the layer of silicon nitride (SiN) for example and a dielectric layer 106 in order in this substrate 100.
Secondly, see also Figure 1B, for example etching is removed this dielectric layer 106 of part and is formed a hole 112, and this hole 112 is for exposing this etching stopping layer 104.The below, position of this hole 112 is corresponding to this metal level 102.
Secondly, see also Fig. 1 C, utilizing a patterned light blockage layer (not shown) to be used as is a cover curtain (mask), and the etching removal is positioned at etching stopping layer 104 and the part dielectric layer 106 under the hole 102, and forming an opening 114, this opening 114 exposes this metal level 102.Wherein, this opening 114 is by being made up of a hole 116 and a groove 118.
Secondly, see also Fig. 1 D, form the barrier layer 122 (for example being Ta/TaN) of compliance and a metal level 124 (for example Cu) in this opening 114 and form a dual-damascene structure 126.Afterwards, carry out a CMP (cmp) processing procedure, the undesired barrier layer 122 and the metal level 124 at dielectric layer 106 tops are removed.
Lifting along with IC assembly integration, by dielectric layer between metal layers (inter-metal dielectriclayer, IMD, for example dielectric layer shown in Fig. 1 D 106) parasitic capacitance (parasiticcapacitance) that produced can increase residual capacitance and postpone (resistance-capacitance delay).Therefore, generally in inferior micron system, often use dielectric materials to make dielectric layer between metal layers.Known dielectric materials can be organic material (organic material) or non-organic material (inorganic material).Wherein, organic material is SILK for example, FLARE... or the like, but not organic material for example is HSQ, FSG... or the like.
Yet, inserting conductor material in the processing procedure of opening 114, normal resistance barrier metal level 122 and the low dielectric found has be full of cracks (cracking) and other tack problem for the interface between the number dielectric layer 106.The bad problem of this tack seriously influences the assembly reliability.
Therefore, work out how to form a dual-damascene structure and can address the above problem and just become an important topic.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of method that forms dual-damascene structure.
Another object of the present invention provides a kind of method of improving adhesive force between dielectric layer in the dual-damascene structure and the conductor material.
For reaching above-mentioned purpose, the invention provides a kind of method that forms dual-damascene structure, comprise the following steps:
One substrate is provided, and this substrate has a conductor layer;
Form a dielectric layer in this substrate;
Form one and be opened in this dielectric layer, this opening comprises a groove and a hole, and wherein this hole is beneath for exposing this conductor layer;
The plasma processing of a N2O or inert gas is carried out on this dielectric layer surface that is positioned at this opening, and form a noncrystalline domain in this dielectric layer surface, this noncrystalline domain has a degree of depth; And
Insert conductor material in this opening and form a dual-damascene structure.
Via method of the present invention, by a N is carried out on this dielectric layer surface that is positioned at this opening
2The plasma processing of O or inert gas, and form a noncrystalline domain in this dielectric layer surface, and can increase bond number between dielectric layer and the conductor material and can promote adhesive force, thereby make the double-insert process quality be improved.Person more is because N
2The plasma processing of O or inert gas makes the dielectric layer surface coarsening, and this has also promoted the adhesive force between dielectric layer and the conductor material.
Description of drawings
Figure 1A to 1D is the processing procedure generalized section of known dual-damascene structure; And
Fig. 2 A to 2E is the processing procedure generalized section of the dual-damascene structure of the embodiment of the invention.
[symbol description]:
Known part (Figure 1A to 1D)
100 substrates; 102～conductor layer; 104 etching stopping layers;
106～dielectric layer; 112～hole; 114～opening;
116～hole; 118～groove; 122～barrier layer;
124～copper layer; 126～mosaic texture.
This case part (Fig. 2 A to 2E)
200～substrate; 202～conductor layer; 204～etching stopping layer;
206～dielectric layer; 212～hole; 214～opening;
216～hole; 218～groove;
The plasma processing of 220～N2O or inert gas; 221～noncrystalline domain;
222～barrier layer; 224～metal level; 226～mosaic texture.
Embodiment
Below utilize Fig. 2 A to 2E that double-insert process of the present invention is described, the present invention has promoted the adhesive force between dielectric layer (for example: low dielectric is the number dielectric layer) and the conductor material (for example: resistance hinders metal level) effectively.
At first, see also Fig. 2 A, a substrate 200 is provided, this substrate 200 has a conductor layer 202.Wherein, this conductor layer 202 for example is the copper layer.Then, form an etching stopping layer (etching stop layer) 204 and one dielectric layer (dielectric layer) 206 in regular turn in this substrate 200.Wherein, this etching stopping layer 204 for example is SiN or SiON layer.The thickness of this etching stopping layer 204 for example is about 500 dusts, and the thickness of this dielectric layer 206 for example is about 3000 dusts.For fear of the problem of parasitic capacitance, the material of this dielectric layer 206 preferably adopts low dielectric to be number dielectric material (low-k dielectric).For instance, this dielectric layer 206 can comprise non-organic material (inorganic materials), for example SiO
2, doped with fluorine SiO
2(FSG) or phosphorosilicate glass (PSG) or the like.This dielectric layer 206 can comprise organic material (organic materials), and for example spin-coating polymer (spin-on-polymer, SOP), FLARE or SILK or the like.
Then, lift the processing procedure that example explanation forms the opening of dual-damascene structure, but and non-limiting the present invention.See also Fig. 2 B, via traditional micro image etching procedure, remove part dielectric layer 206 and form a hole 212, these hole 212 bottoms are for exposing this etching stopping layer 204.Below, the position of this hole 212 is to position that should conductor layer 202.
Secondly, see also Fig. 2 C, utilize a patterned light blockage layer (not shown) to be the cover curtain, this etching stopping layer 204 and the part dielectric layer 206 that is positioned at hole 212 bottoms and exposes removed in etching, and forming an opening 214, this opening 214 is for exposing this conductor layer 202.That is to say that this opening 214 comprises a hole (via hole) 216 and one groove (trench) 218.The degree of depth of this hole 216 can be 3000 dusts, and the degree of depth of this groove 218 can be 3000 dusts.Then, aforementioned photoresistance pattern (not icon) is removed.What will specify here is that this opening 214 of dual-damascene structure can use other processing procedure to make, and for example adopts United States Patent (USP) to number the disclosed method of utilizing the rigid cover curtain of multilayer (multi-layer hard mask) No. 6479391.Yet, being this pattern characteristics of avoiding confusion, the above-mentioned method of the rigid cover curtain of multilayer of utilizing will not be narrated at this.
Secondly, see also Fig. 2 D, Fig. 2 D carries out a N for showing committed step of the present invention to these dielectric layer 206 surfaces that are positioned at this opening 214
2Plasma (plasma) processing procedure 220 of O or inert gas (inert gas), wherein the plasma processing 220 of this inert gas preferably adopts the plasma processing of helium (He), because helium has more suitable atomic wts.Through after this plasma processing procedure 220, can form a noncrystalline domain (amorphous region) 221 in these dielectric layer 206 surfaces, this noncrystalline domain 221 has a degree of depth, on the whole this degree of depth is 100 dusts, this noncrystalline domain 221 can increase bond number (number of bonds) between dielectric layer 206 and the conductor material (226, aftermentioned) and can promote adhesive force.Person more is because N
2The plasma bump (bombardment) of O or inert gas, understand by alligatoring (roughed) on these dielectric layer 206 surfaces of exposure, and can promote the adhesive force between dielectric layer 206 and the conductor material (226, aftermentioned).
In addition, at this measure one example explanation N
2The process conditions of the plasma processing 220 of O or inert gas, but and non-limiting the present invention.Its process conditions for example includes: 100～500W, 10～15MHz, 1～10Torr and 400 ℃ carried out 10～30 seconds.
Secondly, see also Fig. 2 E, insert conductor material 226 in this opening 214 and form a dual-damascene structure 226, wherein this conductor material 226 is by being made of a barrier layer 222 and a metal level 224, and this barrier layer 222 is between metal level 224 and dielectric layer 206.The fabrication steps of Fig. 2 E is described below, and at first forms the barrier layer 222 (for example being Ta/TaN or Ti/TiN) of compliance and a metal level 224 (for example being Cu, Al, AlSiCu or W) in this opening 114 and form a dual-damascene structure 226.Afterwards, carry out a CMP processing procedure, the undesired barrier layer 222 and the metal level 224 at dielectric layer 206 tops are removed, and obtained a smooth surface.Side by side, a fraction of dielectric layer 206 top surfaces also can be removed in above-mentioned CMP processing procedure, and form the profile of the dual-damascene structure shown in Fig. 2 E.
The invention is characterized in: pass through N
2The plasma processing of O or inert gas and can increase adhesive force between low dielectric permittivity dielectric layer and the conductor material.According to the present invention, by a N is carried out on this dielectric layer surface that is positioned at this opening
2The plasma processing of O or inert gas, and form a noncrystalline domain in this dielectric layer surface, and can increase bond number between dielectric layer and the conductor material and can promote adhesive force, thereby make the double-insert process quality be improved.Person more is because N
2The plasma processing of O or inert gas makes the dielectric layer surface coarsening, and this has also promoted the adhesive force between dielectric layer and the conductor material.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (21)
1. a method that forms dual-damascene structure is characterized in that: comprise the following steps:
One substrate is provided, and this substrate has a conductor layer;
Form a dielectric layer in this substrate;
Form one and be opened in this dielectric layer, this opening comprises a groove and a hole, wherein exposes this conductor layer under this hole;
A N is carried out on this dielectric layer surface that is positioned at this opening
2The plasma processing of O or inert gas; And
Insert conductor material in this opening and form a dual-damascene structure.
2. the method for formation dual-damascene structure as claimed in claim 1 is characterized in that: this conductor layer is the copper layer.
3. the method for formation dual-damascene structure as claimed in claim 1 is characterized in that: this dielectric layer is a low dielectric permittivity dielectric layer.
4. the method for formation dual-damascene structure as claimed in claim 3 is characterized in that: this dielectric layer is SiO
2, doped with fluorine SiO
2Or phosphorosilicate glass layer.
5. the method for formation dual-damascene structure as claimed in claim 3 is characterized in that: this dielectric layer is an organic layer.
6. the method for formation dual-damascene structure as claimed in claim 1 is characterized in that: the plasma processing of this inert gas is the helium plasma processing.
7. the method for formation dual-damascene structure as claimed in claim 1 is characterized in that: this N
2The energy condition of the plasma processing of O or inert gas is 100～500W.
8. the method for formation dual-damascene structure as claimed in claim 1 is characterized in that: this conductor material comprises a barrier layer and a metal level.
9. the method for formation dual-damascene structure as claimed in claim 8 is characterized in that: this barrier layer is the Ta/TaN layer.
10. the method for formation dual-damascene structure as claimed in claim 8 is characterized in that: this metal level is the copper layer.
11. a method that forms dual-damascene structure is characterized in that: comprise the following steps:
One substrate is provided, and this substrate has a conductor layer;
Form a dielectric layer in this substrate;
Form one and be opened in this dielectric layer, this opening comprises a groove and a hole, and wherein this hole is beneath for exposing this conductor layer;
A N is carried out on this dielectric layer surface that is positioned at this opening
2The plasma processing of O or inert gas, and form a noncrystalline domain in this dielectric layer surface, this noncrystalline domain has a degree of depth; And
Insert conductor material in this opening and form a dual-damascene structure.
12. the method for formation dual-damascene structure as claimed in claim 11 is characterized in that: this conductor layer is the copper layer.
13. the method for formation dual-damascene structure as claimed in claim 11 is characterized in that: this dielectric layer is the number dielectric layer for low dielectric.
14. the method for formation dual-damascene structure as claimed in claim 13 is characterized in that: this dielectric layer is SiO
2, doped with fluorine SiO
2Or phosphorosilicate glass layer.
15. the method for formation dual-damascene structure as claimed in claim 13 is characterized in that: this dielectric layer is an organic layer.
16. the method for formation dual-damascene structure as claimed in claim 11 is characterized in that: the plasma processing of this inert gas is the helium plasma processing.
17. the method for formation dual-damascene structure as claimed in claim 11 is characterized in that: this N
2The energy condition of the plasma processing of O or inert gas is 100～500W.
18. the method for formation dual-damascene structure as claimed in claim 11 is characterized in that: on the whole this degree of depth that this noncrystalline domain has is 100 dusts.
19. the method for formation dual-damascene structure as claimed in claim 11 is characterized in that: this conductor material comprises a barrier layer and a metal level.
20. the method for formation dual-damascene structure as claimed in claim 19 is characterized in that: this barrier layer is the Ta/TaN layer.
21. the method for formation dual-damascene structure as claimed in claim 19 is characterized in that: this metal level is the copper layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031026575A CN1521828A (en) | 2003-02-13 | 2003-02-13 | Process for forming double mosaic structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031026575A CN1521828A (en) | 2003-02-13 | 2003-02-13 | Process for forming double mosaic structure |
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| Publication Number | Publication Date |
|---|---|
| CN1521828A true CN1521828A (en) | 2004-08-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA031026575A Pending CN1521828A (en) | 2003-02-13 | 2003-02-13 | Process for forming double mosaic structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328616A (en) * | 2015-07-06 | 2017-01-11 | 旺宏电子股份有限公司 | Conductor plug and method for manufacturing same |
-
2003
- 2003-02-13 CN CNA031026575A patent/CN1521828A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328616A (en) * | 2015-07-06 | 2017-01-11 | 旺宏电子股份有限公司 | Conductor plug and method for manufacturing same |
| CN106328616B (en) * | 2015-07-06 | 2019-07-05 | 旺宏电子股份有限公司 | Conductive plugs and its manufacturing method |
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