CN1510861A - Method for controlling system clock frequency - Google Patents

Abstract

A method for controlling the frequency of system clock, setups the accumulator having the digital input end of frequency control, when the system is at rising edge execute accumulation, then takes the certain bit in accumulator as clock output, and filter the clock output, it saves checking sine table and digital analog conversion that need special chip to implement.

Description

A kind of method of control system clock frequency

Technical field

The present invention relates to communication technical field, relate in particular to a kind of method of control system clock frequency.

Background technology

Continuous increase along with communication system functionality, wherein the signal of Chu Liing also becomes increasingly complex, often need in a system, handle the different multiple signal of frequency, as seen how very accurately to control clock rate and make data sync in the system, avoiding transmitting data produces and to overflow or get sky, the stable operation of assurance system just becomes the problem that the industry utmost point need solve.

In Design of Digital System, the clock of a plurality of speed usually need be set in same system, and the general requirement of speed of these clocks can be changed according to the variation of transmit data rate, to reach the purpose that guarantees whole digital communication system data sync.

Please refer to Fig. 1, be the part in the common digital communication system, at first the data of input receive through Data Receiving unit 1, be sent to data processing unit 2 according to the speed of system clock unit 5 then and carry out data processing, data after data processing unit 2 will be handled are simultaneously sent into buffer FIFO3 by certain speed f1, data among the FIFO3 are under the clock effect of tranmitting data register unit 6 generations, send into data transmission unit 4 by the speed f2 of tranmitting data register and send, thereby finish the communication work of whole system.

In said system, in case in a single day the data among the buffer FIFO3 overflow or got sky, just will cause system's error code, influence the operate as normal of system.Because input buffer, the data rate f1 of FIFO3 is constantly changing often, therefore, the tranmitting data register speed f2 that just requires tranmitting data register unit 6 to produce can dynamically adjust according to the data volume among the buffer FIFO3, in order to avoid cause data to overflow or get sky.

Thereby just become the technical issues that need to address for the FREQUENCY CONTROL of clock unit, the method for available technology adopting digital control variable frequency clock has following several:

Method one: as shown in Figure 2, wherein, fin is the clock of fixed frequency, under the control of FREQUENCY CONTROL information, and the clock pulse of clock pulse deduction circuit period property ground deduction some in input clock, thus the Mean Speed of fout is reduced.Shortcoming is: because the clock pulse of clock deduction circuit period property ground deduction some in input clock, cause the Mean Speed of fout to reduce, and then making this method owing to deduct the effect of pulse, clock jitter is bigger, is not suitable for using in the system that clock jitter is had requirement.

Method two: as shown in Figure 4, at first be that FREQUENCY CONTROL information via DAC (digital-to-analog converter) with digital quantity is converted to after the aanalogvoltage, then it is sent into the frequency control terminal of voltage controlled oscillator, utilize owing to become certain functional relation between the output frequency of voltage controlled oscillator and FREQUENCY CONTROL terminal voltage, go just can realize adjustment output frequency by therefore changing FREQUENCY CONTROL information.Shortcoming is: one but this method because the restriction of the figure place of DAC, it is bigger to cause frequency to adjust step-length; Two,, and the reliability of voltage controlled oscillator is lower, and then makes the reliability of system also reduce, and stability reaches less than guarantee.Failure rate is higher, reduces system reliability.

Method three: as shown in Figure 5, the output of accumulator 10 is under the triggering of each system clock fs, and the amount of increase is frequency control word M, and the data width of supposing accumulator 10 is n, and then mould is 2 ⁿ, when the value of accumulator 10 surpasses 2 ⁿThe time, accumulator 10 overflows, and proceeds then to add up.2 of corresponding accumulator 10 ⁿIndividual may output stored corresponding sinusoidal wave range value in the sine table 11.So, when the output of accumulator 10 2 ⁿWithin when changing, sine table 11 will be exported the digitized sine wave of a complete cycle, the output of sine table 11 after DAC12 carries out digital to analog conversion, the analog sine fout of output corresponding frequencies.In this kind method, the frequency of sine wave output is fout=(M * fs)/2 ⁿ, therefore both can change output frequency fout by the value that changes M, fout frequency change minimum step is fs/2 ⁿ, according to Nyquist (Nyquist) law, the theoretical maximum of output frequency is fs/2 ⁿThe major defect of this method is for being: output signal is an analog signal, uses inconvenience in digital system, and in addition, and the cost that the special chip that adopts also causes rises higher.

Summary of the invention

The invention provides a kind of method of control system clock frequency, to solve the big and inconvenient problem of application of the clock jitter that exists in the prior art.

For addressing the above problem, the present invention adopts following technical scheme:

A kind of method of control system clock frequency may further comprise the steps:

A, setting have the accumulator of FREQUENCY CONTROL digital input end, and this accumulator is carried out with following step and added up:

(1) when system clock is in rising edge, with the data output of storage;

(2) with the input data of FREQUENCY CONTROL digital input end and the data addition of step (1) output;

(3) if the sum of step (2) greater than the mould of accumulator, the remainder that sum is deducted the mould of accumulator deposits accumulator in; Otherwise, deposit sum in accumulator;

(4) getting a certain position digital in the accumulator exports as clock;

B, filtering is shaken in output to the clock of steps A.

Advantage of the present invention is: with the shake of the digital signal filtering in the accumulator and directly as clock output, saved and looked into the step that sine table and digital to analog conversion etc. need special chip to realize, it is simple and convenient to put into practice, and cost reduces.

Description of drawings

Fig. 1 is common digital communication system transfer of data and clock setting graph of a relation;

Fig. 2 is the schematic diagram that one of art methods changes clock frequency;

Fig. 3 is the input and the output waveform figure of one of art methods;

Fig. 4 is the schematic diagram that two pairs of clock frequencies of art methods change;

Fig. 5 is the schematic diagram that three pairs of clock frequencies of art methods change;

Fig. 6 is the embodiment flow chart of the method for the invention;

Fig. 7 is the principle schematic of a kind of embodiment of the inventive method.

Embodiment

As a kind of method of control system clock frequency, be exactly will calculate the FREQUENCY CONTROL numeral of gained as parameter, through a series of processing, system clock frequency is transformed into required frequency values, the inventive method may further comprise the steps, with reference to figure 6:

Step 101, setting have the accumulator of FREQUENCY CONTROL digital input end, and this accumulator is carried out with following step and added up:

(1) when system clock is in rising edge, with the data output of storage;

(2) with the input data of FREQUENCY CONTROL digital input end and the data addition of step (1) output;

(3) if the sum of step (2) greater than the mould of accumulator, the remainder that sum is deducted the mould of accumulator deposits accumulator in; Otherwise, deposit sum in accumulator;

(4) getting a certain position digital in the accumulator exports as clock;

Step 102, filtering is shaken in output to the clock of above-mentioned steps 101.

Shown in Figure 7 is the principle schematic of a kind of embodiment of the inventive method, it is the binary accumulator of n that accumulator is wherein selected figure place, the input data of FREQUENCY CONTROL digital input end are binary number m, can select the top digit MSB of accumulator as the position of clock output.In the present embodiment the clock of steps A output MSB is shaken filtering and undertaken by phase-locked loop, experiment shows uses the monolithic integrated phase lock can make the shake of exporting clock fout less than 1ns (nanosecond) when system clock fs reaches 155MHz (megahertz).

In execution mode shown in Figure 7, in order to make clock frequency obtain the control of continuous and effective, further be provided with have the FREQUENCY CONTROL digital input end, the latch of enable signal Load input and output that the FREQUENCY CONTROL numeral is transmitted to accumulator FREQUENCY CONTROL digital input end, this latch is carried out according to following step:

When system clock is in rising edge, if the enable signal input is effectively, then export the FREQUENCY CONTROL numeral of current input, if the enable signal input is invalid, then still export last time FREQUENCY CONTROL numeral.

By above setting, the variation of signal is carried out to 1.5 according to step 1.1 in the input process of FREQUENCY CONTROL numeral.

1.1, the Load signal keeps high level, the enable signal input end is in invalid.

1.2, in the FREQUENCY CONTROL digital input end of latch input m bit (bit) binary system FREQUENCY CONTROL numeral, and keep stable.

1.3, the Load signal is become low level, the enable signal input end is in effectively, and keeps a system clock cycle at least.

1.4, when the fs rising edge of clock signal arrives, make the output of latch equal the input of latch, and keep.

1.5, the Load signal is become high level, the enable signal input end is in invalid.

After said process was finished, even the input end signal of latch changes arbitrarily, when the fs rising edge of clock signal arrived, as long as the enable signal input end is in invalid, the output of latch still remained unchanged.

Following steps 2.1 to 2.4 are job steps of accumulator under the present embodiment:

2.1, when the fs clock signal is in rising edge, accumulator is the output n bit binary data of itself and the m bit binary data addition of latch output, the result of addition is as this output of accumulator.

2.2, when the accumulated value of accumulator surpasses the mould 2n of accumulator, not zero clearing of remainder directly participates in adding up as output next time.

2.3, the highest order MSB of accumulator since the variation of accumulated value between low level and high level, overturn, with this as clock output send into phase-locked loop.

2.4, return step 2.1.

The MSB clock that accumulator is sent into phase-locked loop can contain a certain amount of shake, and its maximum can reach the shake of a fs clock cycle, and phase-locked loop carries out filtering to this shake, thus clock signal fout.

The input process of the course of work of accumulator and FREQUENCY CONTROL numeral is separate in the present embodiment, has only when needing to change the output frequency of fout, just 1.1 to 1.5 imports new FREQUENCY CONTROL numeral set by step.

Claims (4)

1, a kind of method of control system clock frequency may further comprise the steps:

A, setting have the accumulator of FREQUENCY CONTROL digital input end, and this accumulator is carried out with following step and added up:

(1) when system clock is in rising edge, with the data output of storage;

(2) with the input data of FREQUENCY CONTROL digital input end and the data addition of step (1) output;

(3) if the sum of step (2) greater than the mould of accumulator, the remainder that sum is deducted the mould of accumulator deposits accumulator in; Otherwise, deposit sum in accumulator;

(4) getting a certain position digital in the accumulator exports as clock;

B, filtering is shaken in output to the clock of steps A.

2, the method for control system clock frequency as claimed in claim 1 is characterized in that: described is the top digit of accumulator as clock output.

3, the method for control system clock frequency as claimed in claim 1 is characterized in that: filtering is shaken in the clock output of steps A undertaken by phase-locked loop.

4, as the method for claim 1,2 or 3 described control system clock frequencies, it is characterized in that: be provided with have the FREQUENCY CONTROL digital input end, the latch of enable signal input and output that the FREQUENCY CONTROL numeral is transmitted to accumulator FREQUENCY CONTROL digital input end, this latch is carried out according to following step:

When system clock is in rising edge, if the enable signal input is effectively, then export the FREQUENCY CONTROL numeral of current input, if the enable signal input is invalid, then still export last time FREQUENCY CONTROL numeral.

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